ARM: tegra11: clock: Add graphics bus capping interface
Alex Frid [Sat, 2 Feb 2013 07:59:04 +0000 (23:59 -0800)]
Added sysfs nodes to limit Tegra11 graphics bus rate:

/sys/kernel/tegra_cap/cbus_cap_level
/sys/kernel/tegra_cap/cbus_cap_state

Bug 1186037

Change-Id: I8659f8ac25eea78f8fb7fadda0130fc32c884e02
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196731
(cherry picked from commit 5100dadf197587e9d5afca110811c0121aac20b6)
Reviewed-on: http://git-master/r/199180
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra11_dvfs.c

index dd077d5..11df9c6 100644 (file)
@@ -6639,6 +6639,7 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("override.c2bus",    "override.c2bus",       NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.c2bus",         "edp.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("battery.c2bus",     "battery_edp",          "gpu",  &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.c2bus", "profile.c2bus",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
 
        DUAL_CBUS_CLK("msenc.cbus",     "tegra_msenc",          "msenc",  &tegra_clk_c3bus, "msenc", 0, 0),
        DUAL_CBUS_CLK("tsec.cbus",      "tegra_tsec",           "tsec",   &tegra_clk_c3bus, "tsec", 0, 0),
@@ -6662,6 +6663,7 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("override.cbus", "override.cbus",    NULL,   &tegra_clk_cbus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.cbus",  "edp.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("battery.cbus", "battery_edp",       "gpu",  &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.cbus", "profile.cbus",  NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
 #endif
 };
 
index 6cff1e2..1dc216f 100644 (file)
@@ -770,7 +770,7 @@ int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
        return 0;
 }
 
-/* Core cap object and table */
+/* Core voltage and bus cap object and tables */
 static struct kobject *cap_kobj;
 
 static struct core_dvfs_cap_table tegra11_core_cap_table[] = {
@@ -784,6 +784,24 @@ static struct core_dvfs_cap_table tegra11_core_cap_table[] = {
        { .cap_name = "cap.emc" },
 };
 
+/*
+ * Keep sys file names the same for dual and single cbus configurations to
+ * avoid changes in user space GPU capping interface.
+ */
+static struct core_bus_cap_table tegra11_bus_cap_table[] = {
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+       { .cap_name = "cap.profile.c2bus",
+         .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} },
+         .level_attr  = {.attr = {.name = "cbus_cap_level", .mode = 0644} },
+       },
+#else
+       { .cap_name = "cap.profile.cbus",
+         .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} },
+         .level_attr  = {.attr = {.name = "cbus_cap_level", .mode = 0644} },
+       },
+#endif
+};
+
 static int __init tegra11_dvfs_init_core_cap(void)
 {
        int ret;
@@ -794,6 +812,16 @@ static int __init tegra11_dvfs_init_core_cap(void)
                return 0;
        }
 
+       ret = tegra_init_shared_bus_cap(
+               tegra11_bus_cap_table, ARRAY_SIZE(tegra11_bus_cap_table),
+               cap_kobj);
+       if (ret) {
+               pr_err("tegra11_dvfs: failed to init bus cap interface (%d)\n",
+                      ret);
+               kobject_del(cap_kobj);
+               return 0;
+       }
+
        ret = tegra_init_core_cap(
                tegra11_core_cap_table, ARRAY_SIZE(tegra11_core_cap_table),
                core_millivolts, ARRAY_SIZE(core_millivolts), cap_kobj);