arm64: boot: dts: fix xusb prod settings for RX_DFE
Ajay Gupta [Wed, 20 May 2015 18:02:24 +0000 (11:02 -0700)]
Recommended value of RX_DFE is 0xC0077F1F as per bug 1547690
Also added code to print prod settings.

Bug 1567693
Bug 1647326
Bug 1644248

Change-Id: I1d6602b35b03b27f01ed981dc9fe1808724763eb
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/745104
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

arch/arm/mach-tegra/include/mach/tegra_usb_pad_ctrl.h
arch/arm64/boot/dts/tegra210-platforms/tegra210-prods.dtsi
drivers/platform/tegra/tegra_usb_pad_ctrl.c

index a1bcac9..253d046 100644 (file)
@@ -458,6 +458,13 @@ static inline enum padctl_lane usb3_laneowner_to_lane_enum(u8 laneowner)
 #define SS_PORT_MAP(_p, val) \
        ((val & 0x7) << (_p * 5))
 
+#define XUSB_PADCTL_UPHY_USB3_ECTL_2_0(p) (0xa64 + p * 0x40)
+#define XUSB_PADCTL_UPHY_USB3_ECTL_2_0_RX_CTLE_MASK 0xffff
+#define XUSB_PADCTL_UPHY_USB3_ECTL_3_0(p) (0xa68 + p * 0x40)
+#define XUSB_PADCTL_UPHY_USB3_ECTL_4_0(p) (0xa6c + p * 0x40)
+#define XUSB_PADCTL_UPHY_USB3_ECTL_4_0_RX_CDR_CTRL_MASK (0xffff << 16)
+#define XUSB_PADCTL_UPHY_USB3_ECTL_6_0(p) (0xa74 + p * 0x40)
+
 #define XUSB_PADCTL_USB2_VBUS_ID_0     0xc60
 #define VBUS_SOURCE_SELECT(val)        ((val & 0x3) << 12)
 #define ID_SOURCE_SELECT(val)  ((val & 0x3) << 16)
index f30576b..0168f2c 100644 (file)
                            prod = <
                                3 0x00000a60 0xfffcffff 0x00020000
                                3 0x00000a64 0xffff0000 0x000000fc
-                               3 0x00000a68 0x00000000 0x00077f17
+                               3 0x00000a68 0x00000000 0xc0077f1f
                                3 0x00000a74 0x00000000 0xfcf01368
                            >;
                        };
                            prod = <
                                3 0x00000aa0 0xfffcffff 0x00020000
                                3 0x00000aa4 0xffff0000 0x000000fc
-                               3 0x00000aa8 0x00000000 0x00077f17
+                               3 0x00000aa8 0x00000000 0xc0077f1f
                                3 0x00000ab4 0x00000000 0xfcf01368
                            >;
                        };
                            prod = <
                                3 0x00000ae0 0xfffcffff 0x00020000
                                3 0x00000ae4 0xffff0000 0x000000fc
-                               3 0x00000ae8 0x00000000 0x00077f17
+                               3 0x00000ae8 0x00000000 0xc0077f1f
                                3 0x00000af4 0x00000000 0xfcf01368
                            >;
                        };
                            prod = <
                                3 0x00000b20 0xfffcffff 0x00020000
                                3 0x00000b24 0xffff0000 0x000000fc
-                               3 0x00000b28 0x00000000 0x00077f17
+                               3 0x00000b28 0x00000000 0xc0077f1f
                                3 0x00000b34 0x00000000 0xfcf01368
                            >;
                        };
index a918920..ac39661 100644 (file)
@@ -976,6 +976,23 @@ void xusb_ss_pad_init(int pad, int port_map, u32 cap)
        pr_debug("[%s] ss pad %d\n", __func__ , pad);
        pr_debug("XUSB_PADCTL_SS_PORT_MAP = 0x%x\n"
                        , readl(pad_base + XUSB_PADCTL_SS_PORT_MAP));
+
+#ifdef CONFIG_ARCH_TEGRA_21x_SOC
+       /* read and print xusb prod settings for the SS pad */
+       val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_2_0(pad));
+       val &= XUSB_PADCTL_UPHY_USB3_ECTL_2_0_RX_CTLE_MASK;
+       pr_info("xusb_prod port%d RX_CTLE = 0x%lx\n", pad, val);
+
+       val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_3_0(pad));
+       pr_info("xusb_prod port%d RX_DFE = 0x%lx\n", pad, val);
+
+       val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_4_0(pad));
+       val &= XUSB_PADCTL_UPHY_USB3_ECTL_4_0_RX_CDR_CTRL_MASK;
+       pr_info("xusb_prod port%d RX_CDR_CTRL = 0x%lx\n", pad, val >> 16);
+
+       val = readl(pad_base + XUSB_PADCTL_UPHY_USB3_ECTL_6_0(pad));
+       pr_info("xusb_prod port%d RX_EQ_CTRL_H = 0x%lx\n", pad, val);
+#endif
 }
 EXPORT_SYMBOL_GPL(xusb_ss_pad_init);