video: tegra: host: Remove 32 sync point limit
Terje Bergstrom [Thu, 22 Nov 2012 06:42:02 +0000 (08:42 +0200)]
Introduce new getter ioctls that take an index as parameter, and
return the syncpt/waitbase/mutex corresponding to that index. This
removes the 32 sync point restriction.

Remove limit of 32 sync points, wait bases and modmutexes in the
device data.

Fixes two off-by-one errors in intr code and adds a check for syncpt
id in submit.

Bug 1050376
Bug 1034424

Change-Id: I5f55e59e36f5e3183395d425103a2c386afb87b9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/167710
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

drivers/video/tegra/host/bus_client.c
drivers/video/tegra/host/chip_support.h
drivers/video/tegra/host/host1x/host1x_cdma.c
drivers/video/tegra/host/host1x/host1x_channel.c
drivers/video/tegra/host/host1x/host1x_intr.c
drivers/video/tegra/host/t114/t114.c
drivers/video/tegra/host/t148/t148.c
drivers/video/tegra/host/t20/t20.c
drivers/video/tegra/host/t30/t30.c
include/linux/nvhost.h
include/linux/nvhost_ioctl.h

index ce25a0f..5b24096 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Client Module
  *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -416,6 +416,7 @@ static int nvhost_ioctl_channel_submit(struct nvhost_channel_userctx *ctx,
        struct nvhost_reloc_shift __user *reloc_shifts = args->reloc_shifts;
        struct nvhost_waitchk __user *waitchks = args->waitchks;
        struct nvhost_syncpt_incr syncpt_incr;
+       struct nvhost_master *host = nvhost_get_host(ctx->ch->dev);
        int err;
 
        /* We don't yet support other than one nvhost_syncpt_incrs per submit */
@@ -467,6 +468,10 @@ static int nvhost_ioctl_channel_submit(struct nvhost_channel_userctx *ctx,
        if (err)
                goto fail;
        job->syncpt_id = syncpt_incr.syncpt_id;
+       if (job->syncpt_id > host->info.nb_pts) {
+               err = -EINVAL;
+               goto fail;
+       }
        job->syncpt_incrs = syncpt_incr.syncpt_incrs;
 
        trace_nvhost_channel_submit(ctx->ch->dev->name,
@@ -598,6 +603,16 @@ static int nvhost_ioctl_channel_module_regrdwr(
        return 0;
 }
 
+static u32 create_mask(u32 *words, int num)
+{
+       int i;
+       u32 word = 0;
+       for (i = 0; i < num && words[i] && words[i] < BITS_PER_LONG; i++)
+               word |= BIT(words[i]);
+
+       return word;
+}
+
 static long nvhost_channelctl(struct file *filp,
        unsigned int cmd, unsigned long arg)
 {
@@ -658,11 +673,22 @@ static long nvhost_channelctl(struct file *filp,
        }
        case NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS:
        {
-               /* host syncpt ID is used by the RM (and never be given out) */
                struct nvhost_device_data *pdata = \
                        platform_get_drvdata(priv->ch->dev);
                ((struct nvhost_get_param_args *)buf)->value =
-                       pdata->syncpts;
+                       create_mask(pdata->syncpts, NVHOST_MODULE_MAX_SYNCPTS);
+               break;
+       }
+       case NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT:
+       {
+               struct nvhost_device_data *pdata = \
+                       platform_get_drvdata(priv->ch->dev);
+               struct nvhost_get_param_arg *arg =
+                       (struct nvhost_get_param_arg *)buf;
+               if (arg->param >= NVHOST_MODULE_MAX_SYNCPTS
+                               || !pdata->syncpts[arg->param])
+                       return -EINVAL;
+               arg->value = pdata->syncpts[arg->param];
                break;
        }
        case NVHOST_IOCTL_CHANNEL_GET_WAITBASES:
@@ -670,7 +696,20 @@ static long nvhost_channelctl(struct file *filp,
                struct nvhost_device_data *pdata = \
                        platform_get_drvdata(priv->ch->dev);
                ((struct nvhost_get_param_args *)buf)->value =
-                       pdata->waitbases;
+                       create_mask(pdata->waitbases,
+                                       NVHOST_MODULE_MAX_WAITBASES);
+               break;
+       }
+       case NVHOST_IOCTL_CHANNEL_GET_WAITBASE:
+       {
+               struct nvhost_device_data *pdata = \
+                       platform_get_drvdata(priv->ch->dev);
+               struct nvhost_get_param_arg *arg =
+                       (struct nvhost_get_param_arg *)buf;
+               if (arg->param >= NVHOST_MODULE_MAX_WAITBASES
+                               || !pdata->waitbases[arg->param])
+                       return -EINVAL;
+               arg->value = pdata->waitbases[arg->param];
                break;
        }
        case NVHOST_IOCTL_CHANNEL_GET_MODMUTEXES:
@@ -678,7 +717,20 @@ static long nvhost_channelctl(struct file *filp,
                struct nvhost_device_data *pdata = \
                        platform_get_drvdata(priv->ch->dev);
                ((struct nvhost_get_param_args *)buf)->value =
-                       pdata->modulemutexes;
+                       create_mask(pdata->modulemutexes,
+                                       NVHOST_MODULE_MAX_MODMUTEXES);
+               break;
+       }
+       case NVHOST_IOCTL_CHANNEL_GET_MODMUTEX:
+       {
+               struct nvhost_device_data *pdata = \
+                       platform_get_drvdata(priv->ch->dev);
+               struct nvhost_get_param_arg *arg =
+                       (struct nvhost_get_param_arg *)buf;
+               if (arg->param >= NVHOST_MODULE_MAX_MODMUTEXES
+                               || !pdata->modulemutexes[arg->param])
+                       return -EINVAL;
+               arg->value = pdata->modulemutexes[arg->param];
                break;
        }
        case NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD:
index c583e4f..62d7c76 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Chip Support
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ struct nvhost_cdma_ops {
                                 u32 syncpt_incrs,
                                 u32 syncval,
                                 u32 nr_slots,
-                                u32 waitbases);
+                                u32 *waitbases);
 };
 
 struct nvhost_pushbuffer_ops {
index 1892c7a..1365746 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Command DMA
  *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -225,7 +225,7 @@ static void cdma_timeout_destroy(struct nvhost_cdma *cdma)
  */
 static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
                                u32 syncpt_incrs, u32 syncval, u32 nr_slots,
-                               u32 waitbases)
+                               u32 *waitbases)
 {
        struct nvhost_master *dev = cdma_to_dev(cdma);
        struct push_buffer *pb = &cdma->push_buffer;
@@ -240,12 +240,12 @@ static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
        /* Synchronize wait bases. 2D wait bases are synchronized with
         * syncpoint 19. Hence wait bases are not updated when syncptid=18. */
 
-       if (cdma->timeout.syncpt_id != NVSYNCPT_2D_0 && waitbases) {
+       if (cdma->timeout.syncpt_id != NVSYNCPT_2D_0 && waitbases[0]) {
                void __iomem *p;
                p = dev->sync_aperture + host1x_sync_syncpt_base_0_r() +
-                               (__ffs(waitbases) * sizeof(u32));
+                               (waitbases[0] * sizeof(u32));
                writel(syncval, p);
-               dev->syncpt.base_val[__ffs(waitbases)] = syncval;
+               dev->syncpt.base_val[waitbases[0]] = syncval;
        }
 
        /* NOP all the PB slots */
index 3da0d67..c0fc048 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Channel
  *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -39,9 +39,8 @@ static void sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val)
 {
        unsigned long waitbase;
        struct nvhost_device_data *pdata = platform_get_drvdata(ch->dev);
-       unsigned long int waitbase_mask = pdata->waitbases;
        if (pdata->waitbasesync) {
-               waitbase = find_first_bit(&waitbase_mask, BITS_PER_LONG);
+               waitbase = pdata->waitbases[0];
                nvhost_cdma_push(&ch->cdma,
                        nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
                                host1x_uclass_load_syncpt_base_r(),
@@ -481,10 +480,8 @@ static inline int host1x_hwctx_handler_init(struct nvhost_channel *ch)
        int err = 0;
 
        struct nvhost_device_data *pdata = platform_get_drvdata(ch->dev);
-       unsigned long syncpts = pdata->syncpts;
-       unsigned long waitbases = pdata->waitbases;
-       u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
-       u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
+       u32 syncpt = pdata->syncpts[0];
+       u32 waitbase = pdata->waitbases[0];
 
        if (pdata->alloc_hwctx_handler) {
                ch->ctxhandler = pdata->alloc_hwctx_handler(syncpt,
index 3a17294..e63d32f 100644 (file)
@@ -4,7 +4,7 @@
  * Tegra Graphics Host Interrupt Management
  *
  * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -46,7 +46,7 @@ static irqreturn_t syncpt_thresh_cascade_isr(int irq, void *dev_id)
        unsigned long reg;
        int i, id;
 
-       for (i = 0; i < dev->info.nb_pts / BITS_PER_LONG; i++) {
+       for (i = 0; i < DIV_ROUND_UP(dev->info.nb_pts, BITS_PER_LONG); i++) {
                reg = readl(sync_regs +
                                host1x_sync_syncpt_thresh_cpu0_int_status_r() +
                                i * REGISTER_STRIDE);
@@ -143,7 +143,7 @@ static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
        void __iomem *sync_regs = dev->sync_aperture;
        u32 reg;
 
-       for (reg = 0; reg <= BIT_WORD(dev->info.nb_pts) * REGISTER_STRIDE;
+       for (reg = 0; reg < BIT_WORD(dev->info.nb_pts) * REGISTER_STRIDE;
                        reg += REGISTER_STRIDE) {
                /* disable interrupts for both cpu's */
                writel(0xffffffffu, sync_regs +
index 9d4a3ca..207fd5a 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for Tegra11 Architecture Chips
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -116,9 +116,9 @@ static struct platform_device tegra_host1x02_device = {
 static struct nvhost_device_data tegra_gr3d03_info = {
        .version        = 3,
        .index          = 1,
-       .syncpts        = BIT(NVSYNCPT_3D),
-       .waitbases      = BIT(NVWAITBASE_3D),
-       .modulemutexes  = BIT(NVMODMUTEX_3D),
+       .syncpts        = {NVSYNCPT_3D},
+       .waitbases      = {NVWAITBASE_3D},
+       .modulemutexes  = {NVMODMUTEX_3D},
        .class          = NV_GRAPHICS_3D_CLASS_ID,
        .clocks         = { {"gr3d", UINT_MAX, 8, true},
                            {"emc", UINT_MAX, 75} },
@@ -141,10 +141,10 @@ static struct platform_device tegra_gr3d03_device = {
 static struct nvhost_device_data tegra_gr2d03_info = {
        .version        = 2,
        .index          = 2,
-       .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-       .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-       .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-                         BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+       .syncpts        = {NVSYNCPT_2D_0, NVSYNCPT_2D_1},
+       .waitbases      = {NVWAITBASE_2D_0, NVWAITBASE_2D_1},
+       .modulemutexes  = {NVMODMUTEX_2D_FULL, NVMODMUTEX_2D_SIMPLE,
+                         NVMODMUTEX_2D_SB_A, NVMODMUTEX_2D_SB_B},
        .clocks         = { {"gr2d", 0, 7, true}, {"epp", 0, 10, true},
                            {"emc", 300000000, 75 } },
        .powergate_ids  = { TEGRA_POWERGATE_HEG, -1 },
@@ -174,8 +174,8 @@ static struct resource isp_resources[] = {
 
 static struct nvhost_device_data tegra_isp01_info = {
        .index          = 3,
-       .syncpts        = BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
+       .syncpts        = {NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
        .clocks         = { {"epp", 0} },
        .keepalive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
@@ -204,11 +204,11 @@ static struct resource vi_resources[] = {
 
 static struct nvhost_device_data tegra_vi01_info = {
        .index          = 4,
-       .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-                         BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-                         BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
-       .modulemutexes  = BIT(NVMODMUTEX_VI),
+       .syncpts        = {NVSYNCPT_CSI_VI_0, NVSYNCPT_CSI_VI_1,
+                         NVSYNCPT_VI_ISP_0, NVSYNCPT_VI_ISP_1,
+                         NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
+       .modulemutexes  = {NVMODMUTEX_VI},
        .exclusive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
@@ -237,8 +237,8 @@ static struct resource msenc_resources[] = {
 static struct nvhost_device_data tegra_msenc02_info = {
        .version        = NVHOST_ENCODE_MSENC_VER(2, 0),
        .index          = 5,
-       .syncpts        = BIT(NVSYNCPT_MSENC),
-       .waitbases      = BIT(NVWAITBASE_MSENC),
+       .syncpts        = {NVSYNCPT_MSENC},
+       .waitbases      = {NVWAITBASE_MSENC},
        .class          = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
        .clocks        = { {"msenc", UINT_MAX, 107, true},
                           {"emc", 300000000, 75} },
@@ -271,8 +271,8 @@ static struct resource tsec_resources[] = {
 static struct nvhost_device_data tegra_tsec01_info = {
        .version        = NVHOST_ENCODE_TSEC_VER(1, 0),
        .index          = 7,
-       .syncpts        = BIT(NVSYNCPT_TSEC),
-       .waitbases      = BIT(NVWAITBASE_TSEC),
+       .syncpts        = {NVSYNCPT_TSEC},
+       .waitbases      = {NVWAITBASE_TSEC},
        .class          = NV_TSEC_CLASS_ID,
        .exclusive      = false,
        .clocks        = { {"tsec", UINT_MAX, 108, true},
index ee17b24..b7dc657 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for T148 Architecture Chips
  *
- * Copyright (c) 2012, NVIDIA Corporation.
+ * Copyright (c) 2012-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -117,9 +117,9 @@ static struct platform_device tegra_host1x03_device = {
 static struct nvhost_device_data tegra_gr3d03_info = {
        .version        = 3,
        .index          = 1,
-       .syncpts        = BIT(NVSYNCPT_3D),
-       .waitbases      = BIT(NVWAITBASE_3D),
-       .modulemutexes  = BIT(NVMODMUTEX_3D),
+       .syncpts        = {NVSYNCPT_3D},
+       .waitbases      = {NVWAITBASE_3D},
+       .modulemutexes  = {NVMODMUTEX_3D},
        .class          = NV_GRAPHICS_3D_CLASS_ID,
        .clocks         = { {"gr3d", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
        NVHOST_MODULE_NO_POWERGATE_IDS,
@@ -137,10 +137,10 @@ static struct platform_device tegra_gr3d03_device = {
 
 static struct nvhost_device_data tegra_gr2d03_info = {
        .index          = 2,
-       .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-       .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-       .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-                         BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+       .syncpts        = {NVSYNCPT_2D_0, NVSYNCPT_2D_1},
+       .waitbases      = {NVWAITBASE_2D_0, NVWAITBASE_2D_1},
+       .modulemutexes  = {NVMODMUTEX_2D_FULL, NVMODMUTEX_2D_SIMPLE,
+                         NVMODMUTEX_2D_SB_A, NVMODMUTEX_2D_SB_B},
        .clocks         = { {"gr2d", 0}, {"epp", UINT_MAX},
                            {"emc", HOST_EMC_FLOOR} },
        NVHOST_MODULE_NO_POWERGATE_IDS,
@@ -167,7 +167,8 @@ static struct resource isp_resources[] = {
 
 static struct nvhost_device_data tegra_isp01_info = {
        .index          = 3,
-       .syncpts        = 0,
+       .syncpts        = {NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_ISP,
@@ -194,11 +195,11 @@ static struct resource vi_resources[] = {
 
 static struct nvhost_device_data tegra_vi01_info = {
        .index          = 4,
-       .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-                         BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-                         BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
-       .modulemutexes  = BIT(NVMODMUTEX_VI_0),
+       .syncpts        = {NVSYNCPT_CSI_VI_0, NVSYNCPT_CSI_VI_1,
+                         NVSYNCPT_VI_ISP_0, NVSYNCPT_VI_ISP_1,
+                         NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
+       .modulemutexes  = {NVMODMUTEX_VI_0},
        .exclusive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
@@ -227,8 +228,8 @@ static struct resource msenc_resources[] = {
 static struct nvhost_device_data tegra_msenc03_info = {
        .version        = NVHOST_ENCODE_MSENC_VER(3, 0),
        .index          = 5,
-       .syncpts        = BIT(NVSYNCPT_MSENC),
-       .waitbases      = BIT(NVWAITBASE_MSENC),
+       .syncpts        = {NVSYNCPT_MSENC},
+       .waitbases      = {NVWAITBASE_MSENC},
        .class          = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
        .clocks         = { {"msenc", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
        .powergate_ids = { TEGRA_POWERGATE_MPE, -1 },
@@ -260,8 +261,8 @@ static struct resource tsec_resources[] = {
 static struct nvhost_device_data tegra_tsec01_info = {
        .version        = NVHOST_ENCODE_TSEC_VER(1,0),
        .index          = 7,
-       .syncpts        = BIT(NVSYNCPT_TSEC),
-       .waitbases      = BIT(NVWAITBASE_TSEC),
+       .syncpts        = {NVSYNCPT_TSEC},
+       .waitbases      = {NVWAITBASE_TSEC},
        .class          = NV_TSEC_CLASS_ID,
        .exclusive      = false,
        .clocks         = { {"tsec", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
index 26e54f3..5ed4523 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for T20 Architecture Chips
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -109,9 +109,9 @@ struct platform_device tegra_host1x01_device = {
 static struct nvhost_device_data tegra_gr3d01_info = {
        .version        = 1,
        .index          = 1,
-       .syncpts        = BIT(NVSYNCPT_3D),
-       .waitbases      = BIT(NVWAITBASE_3D),
-       .modulemutexes  = BIT(NVMODMUTEX_3D),
+       .syncpts        = {NVSYNCPT_3D},
+       .waitbases      = {NVWAITBASE_3D},
+       .modulemutexes  = {NVMODMUTEX_3D},
        .class          = NV_GRAPHICS_3D_CLASS_ID,
        .clocks         = {{"gr3d", UINT_MAX, 8, true},
                           {"emc", UINT_MAX, 75}, {} },
@@ -131,10 +131,10 @@ static struct platform_device tegra_gr3d01_device = {
 static struct nvhost_device_data tegra_gr2d01_info = {
        .version        = 1,
        .index          = 2,
-       .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-       .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-       .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-                         BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+       .syncpts        = {NVSYNCPT_2D_0, NVSYNCPT_2D_1},
+       .waitbases      = {NVWAITBASE_2D_0, NVWAITBASE_2D_1},
+       .modulemutexes  = {NVMODMUTEX_2D_FULL, NVMODMUTEX_2D_SIMPLE,
+                         NVMODMUTEX_2D_SB_A, NVMODMUTEX_2D_SB_B},
        .clocks         = { {"gr2d", UINT_MAX, 7, true},
                            {"epp", UINT_MAX, 10, true},
                            {"emc", UINT_MAX, 75} },
@@ -172,7 +172,6 @@ static struct resource isp_resources[] = {
 
 static struct nvhost_device_data tegra_isp01_info = {
        .index          = 3,
-       .syncpts        = 0,
        .keepalive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
@@ -200,11 +199,11 @@ static struct resource vi_resources[] = {
 
 static struct nvhost_device_data tegra_vi01_info = {
        .index          = 4,
-       .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-                         BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-                         BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
-       .modulemutexes  = BIT(NVMODMUTEX_VI),
+       .syncpts        = {NVSYNCPT_CSI_VI_0, NVSYNCPT_CSI_VI_1,
+                         NVSYNCPT_VI_ISP_0, NVSYNCPT_VI_ISP_1,
+                         NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
+       .modulemutexes  = {NVMODMUTEX_VI},
        .exclusive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
@@ -224,9 +223,9 @@ static struct platform_device tegra_vi01_device = {
 static struct nvhost_device_data tegra_mpe01_info = {
        .version        = 1,
        .index          = 5,
-       .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
-                         BIT(NVSYNCPT_MPE_WR_SAFE),
-       .waitbases      = BIT(NVWAITBASE_MPE),
+       .syncpts        = {NVSYNCPT_MPE, NVSYNCPT_MPE_EBM_EOF,
+                         NVSYNCPT_MPE_WR_SAFE},
+       .waitbases      = {NVWAITBASE_MPE},
        .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
        .waitbasesync   = true,
        .keepalive      = true,
index 9406a0c..1618217 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for T30 Architecture Chips
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -111,9 +111,9 @@ static struct platform_device tegra_host1x01_device = {
 static struct nvhost_device_data tegra_gr3d02_info = {
        .version        = 2,
        .index          = 1,
-       .syncpts        = BIT(NVSYNCPT_3D),
-       .waitbases      = BIT(NVWAITBASE_3D),
-       .modulemutexes  = BIT(NVMODMUTEX_3D),
+       .syncpts        = {NVSYNCPT_3D},
+       .waitbases      = {NVWAITBASE_3D},
+       .modulemutexes  = {NVMODMUTEX_3D},
        .class          = NV_GRAPHICS_3D_CLASS_ID,
        .clocks         = { {"gr3d", UINT_MAX, 8, true},
                            {"gr3d2", UINT_MAX, 0, true},
@@ -138,10 +138,10 @@ static struct platform_device tegra_gr3d02_device = {
 static struct nvhost_device_data tegra_gr2d02_info = {
        .version        = 1,
        .index          = 2,
-       .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
-       .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
-       .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
-                         BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+       .syncpts        = {NVSYNCPT_2D_0, NVSYNCPT_2D_1},
+       .waitbases      = {NVWAITBASE_2D_0, NVWAITBASE_2D_1},
+       .modulemutexes  = {NVMODMUTEX_2D_FULL, NVMODMUTEX_2D_SIMPLE,
+                         NVMODMUTEX_2D_SB_A, NVMODMUTEX_2D_SB_B},
        .clocks         = { {"gr2d", 0, 7, true},
                          {"epp", 0, 10, true},
                          {"emc", 300000000, 75} },
@@ -170,8 +170,8 @@ static struct resource isp_resources[] = {
 
 static struct nvhost_device_data tegra_isp01_info = {
        .index          = 3,
-       .syncpts        = BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
+       .syncpts        = {NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
        .clocks         = { {"epp", 0, 10} },
        .keepalive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
@@ -200,11 +200,11 @@ static struct resource vi_resources[] = {
 
 static struct nvhost_device_data tegra_vi01_info = {
        .index          = 4,
-       .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
-                         BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
-                         BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
-                         BIT(NVSYNCPT_VI_ISP_4),
-       .modulemutexes  = BIT(NVMODMUTEX_VI),
+       .syncpts        = {NVSYNCPT_CSI_VI_0, NVSYNCPT_CSI_VI_1,
+                         NVSYNCPT_VI_ISP_0, NVSYNCPT_VI_ISP_1,
+                         NVSYNCPT_VI_ISP_2, NVSYNCPT_VI_ISP_3,
+                         NVSYNCPT_VI_ISP_4},
+       .modulemutexes  = {NVMODMUTEX_VI},
        .exclusive      = true,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
@@ -233,9 +233,9 @@ static struct resource tegra_mpe01_resources[] = {
 static struct nvhost_device_data tegra_mpe02_info = {
        .version        = 2,
        .index          = 5,
-       .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
-                         BIT(NVSYNCPT_MPE_WR_SAFE),
-       .waitbases      = BIT(NVWAITBASE_MPE),
+       .syncpts        = {NVSYNCPT_MPE, NVSYNCPT_MPE_EBM_EOF,
+                         NVSYNCPT_MPE_WR_SAFE},
+       .waitbases      = {NVWAITBASE_MPE},
        .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
        .waitbasesync   = true,
        .keepalive      = true,
index 62ced30..59c075a 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra graphics host driver
  *
- * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2009-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,6 +34,9 @@ struct nvhost_device_power_attr;
 
 #define NVHOST_MODULE_MAX_CLOCKS               3
 #define NVHOST_MODULE_MAX_POWERGATE_IDS        2
+#define NVHOST_MODULE_MAX_SYNCPTS              8
+#define NVHOST_MODULE_MAX_WAITBASES            3
+#define NVHOST_MODULE_MAX_MODMUTEXES           5
 #define NVHOST_MODULE_NO_POWERGATE_IDS         .powergate_ids = {-1, -1}
 #define NVHOST_DEFAULT_CLOCKGATE_DELAY         .clockgate_delay = 25
 #define NVHOST_NAME_SIZE                       24
@@ -88,9 +91,9 @@ struct nvhost_device_data {
        int             index;          /* Hardware channel number */
        void __iomem    *aperture;      /* Iomem mapped to kernel */
 
-       u32             syncpts;        /* Bitfield of sync points used */
-       u32             waitbases;      /* Bit field of wait bases */
-       u32             modulemutexes;  /* Bit field of module mutexes */
+       u32             syncpts[NVHOST_MODULE_MAX_SYNCPTS];
+       u32             waitbases[NVHOST_MODULE_MAX_WAITBASES];
+       u32             modulemutexes[NVHOST_MODULE_MAX_MODMUTEXES];
        u32             moduleid;       /* Module id for user space API */
 
        u32             class;          /* Device class */
index 43498cd..bf65474 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Tegra graphics host driver
  *
- * Copyright (c) 2009-2012, NVIDIA Corporation.
+ * Copyright (c) 2009-2013, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -96,6 +96,11 @@ struct nvhost_get_param_args {
        __u32 value;
 };
 
+struct nvhost_get_param_arg {
+       __u32 param;
+       __u32 value;
+};
+
 struct nvhost_set_nvmap_fd_args {
        __u32 fd;
 };
@@ -174,8 +179,14 @@ struct nvhost_submit_args {
        _IOWR(NVHOST_IOCTL_MAGIC, 14, struct nvhost_ctrl_module_regrdwr_args)
 #define NVHOST_IOCTL_CHANNEL_SUBMIT            \
        _IOWR(NVHOST_IOCTL_MAGIC, 15, struct nvhost_submit_args)
+#define NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT     \
+       _IOWR(NVHOST_IOCTL_MAGIC, 16, struct nvhost_get_param_arg)
+#define NVHOST_IOCTL_CHANNEL_GET_WAITBASE      \
+       _IOWR(NVHOST_IOCTL_MAGIC, 17, struct nvhost_get_param_arg)
+#define NVHOST_IOCTL_CHANNEL_GET_MODMUTEX      \
+       _IOWR(NVHOST_IOCTL_MAGIC, 23, struct nvhost_get_param_arg)
 #define NVHOST_IOCTL_CHANNEL_LAST              \
-       _IOC_NR(NVHOST_IOCTL_CHANNEL_SUBMIT)
+       _IOC_NR(NVHOST_IOCTL_CHANNEL_GET_MODMUTEX)
 #define NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvhost_submit_args)
 
 struct nvhost_ctrl_syncpt_read_args {