ARM: tegra11: clock: Remove non-existed 3D2 clock
Alex Frid [Thu, 10 May 2012 00:24:01 +0000 (17:24 -0700)]
Change-Id: I768b86ce93c5a2875a6f2b1406f7e02094aa55b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/101812
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: R9e9aadb2e23ab91318e922a4d4d7008447f68d71

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra11_dvfs.c

index 771cbb1..1f0956a 100644 (file)
@@ -5018,7 +5018,6 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd",65,     0x1c0,  800000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uarte_dbg", "serial8250.0",         "uarte",66,     0x1c4,  800000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  600000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_MANUAL_RESET),
-       PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  600000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  600000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
@@ -5090,7 +5089,6 @@ struct clk tegra_list_clks[] = {
 
        SHARED_CLK("host1x.cbus", "tegra_host1x",       "host1x", &tegra_clk_cbus, "host1x", 2, 0),
        SHARED_CLK("3d.cbus",   "tegra_gr3d",           "gr3d", &tegra_clk_cbus, "3d",  0, 0),
-       SHARED_CLK("3d2.cbus",  "tegra_gr3d",           "gr3d2", &tegra_clk_cbus, "3d2", 0, 0),
        SHARED_CLK("2d.cbus",   "tegra_gr2d",           "gr2d", &tegra_clk_cbus, "2d",  0, 0),
        SHARED_CLK("epp.cbus",  "tegra_gr2d",           "epp",  &tegra_clk_cbus, "epp", 0, 0),
        SHARED_CLK("msenc.cbus","tegra_msenc",          "msenc",&tegra_clk_cbus, "msenc", 0, 0),
index 051a916..bd1905a 100644 (file)
@@ -111,7 +111,6 @@ static struct dvfs core_dvfs_table[] = {
        CORE_DVFS("epp",    0, 1, KHZ,    60400, 110500, 148000, 186400, 248500,  248500,  313000,  391800),
        CORE_DVFS("2d",     0, 1, KHZ,    77200, 141200, 189200, 238200, 317500,  317500,  400000,  500700),
        CORE_DVFS("3d",     0, 1, KHZ,    86800, 158900, 212800, 267900, 357200,  357200,  450000,  563300),
-       CORE_DVFS("3d2",    0, 1, KHZ,    86800, 158900, 212800, 267900, 357200,  357200,  450000,  563300),
        CORE_DVFS("msenc",  0, 1, KHZ,    64200, 117600, 157500, 198300, 264300,  264300,  333000,  416900),
        CORE_DVFS("se",     0, 1, KHZ,    67500, 123600, 165500, 208400, 277800,  277800,  350000,  438100),
        CORE_DVFS("tsec",   0, 1, KHZ,    67500, 123600, 165500, 208400, 277800,  277800,  350000,  438100),