ARM: tegra11: clock: Always enable common XUSB gate
Alex Frid [Sat, 2 Mar 2013 07:16:51 +0000 (23:16 -0800)]
Added separate common XUSB gate clock. It has to be always enabled,
so that h/w sequencers that automatically control XUSB operations can
properly work.

Bug 1227562

Change-Id: Iaa02b4c3d95b288eb3c47d00fd2054f96dc6dfe7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/205748
(cherry picked from commit 9c35e1c37ee64d9e2244a08d4193710f07bf3f59)
Reviewed-on: http://git-master/r/210254
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 8e33a4a..a550209 100644 (file)
@@ -4295,6 +4295,16 @@ static struct clk_ops tegra_dsi_clk_ops = {
        .reset                  = &tegra11_periph_clk_reset,
 };
 
+/* xusb common clock gate - enabled on init and never disabled */
+static void tegra11_xusb_gate_clk_init(struct clk *c)
+{
+       tegra11_periph_clk_enable(c);
+}
+
+static struct clk_ops tegra_xusb_gate_clk_ops = {
+       .init    = tegra11_xusb_gate_clk_init,
+};
+
 /* pciex clock support only reset function */
 static struct clk_ops tegra_pciex_clk_ops = {
        .reset    = tegra11_periph_clk_reset,
@@ -6763,6 +6773,17 @@ struct clk tegra_list_clks[] = {
 /* XUSB clocks */
 #define XUSB_ID "tegra-xhci"
 
+static struct clk tegra_clk_xusb_gate = {
+       .name      = "xusb_gate",
+       .flags     = ENABLE_ON_INIT | PERIPH_NO_RESET,
+       .ops       = &tegra_xusb_gate_clk_ops,
+       .rate      = 12000000,
+       .max_rate  = 48000000,
+       .u.periph = {
+               .clk_num   = 143,
+       },
+};
+
 static struct clk tegra_xusb_source_clks[] = {
        PERIPH_CLK("xusb_host_src",     XUSB_ID, "host_src",    143,    0x600,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
        PERIPH_CLK("xusb_falcon_src",   XUSB_ID, "falcon_src",  143,    0x604,  350000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
@@ -6911,6 +6932,7 @@ struct clk *tegra_ptr_clks[] = {
        &tegra_pll_d_out0,
        &tegra_pll_d2,
        &tegra_pll_d2_out0,
+       &tegra_clk_xusb_gate,
        &tegra_pll_u,
        &tegra_pll_u_480M,
        &tegra_pll_u_60M,