gpu: nvgpu: Do not touch gr status mask
Terje Bergstrom [Wed, 18 Mar 2015 22:28:23 +0000 (15:28 -0700)]
GR status disable mask was never set, so driver always disabled all
engines from status rollup.

Change-Id: I500a127be9253294f73d1f42ce89b886471a9117
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719141
(cherry picked from commit 34a5ffe7e7dcc4df5f3a11848b828e96c43d2c4d)
Reviewed-on: http://git-master/r/752092
GVS: Gerrit_Virtual_Submit

drivers/gpu/nvgpu/gk20a/gr_gk20a.c
drivers/gpu/nvgpu/gk20a/gr_gk20a.h

index 37b4786..66ebfb9 100644 (file)
@@ -4235,10 +4235,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
        gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF);
        gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF);
 
-       /* ignore status from some units */
-       data = gk20a_readl(g, gr_status_mask_r());
-       gk20a_writel(g, gr_status_mask_r(), data & gr->status_disable_mask);
-
        if (gr->sw_ready)
                gr_gk20a_load_zbc_table(g, gr);
        else
index 8a6df3d..2a31aa0 100644 (file)
@@ -271,8 +271,6 @@ struct gr_gk20a {
        s32 max_used_color_index;
        s32 max_used_depth_index;
 
-       u32 status_disable_mask;
-
 #define GR_CHANNEL_MAP_TLB_SIZE                2 /* must of power of 2 */
        struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
        u32 channel_tlb_flush_index;