video: tegra: dc: update sor programming
Chao Xu [Tue, 7 Aug 2012 23:36:46 +0000 (16:36 -0700)]
- Update SOR register definitions.
- Program SOR power up/power down sequencer.
- Enhance dp enable/disable functions.
- Add lvds enable/disable.

Change-Id: I1e3265d7fbe30bf8c11ea5309917425dfc33bda2
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/127304
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>

drivers/video/tegra/dc/dc_reg.h
drivers/video/tegra/dc/dp.c
drivers/video/tegra/dc/dp.h
drivers/video/tegra/dc/sor.c
drivers/video/tegra/dc/sor.h
drivers/video/tegra/dc/sor_regs.h

index 3762819..b9b5976 100644 (file)
 
 #define DC_DISP_DISP_WIN_OPTIONS               0x402
 #define  CURSOR_ENABLE                 (1 << 16)
+#define  SOR_ENABLE                     (1 << 25)
 #define  TVO_ENABLE                    (1 << 28)
 #define  DSI_ENABLE                    (1 << 29)
 #define  HDMI_ENABLE                   (1 << 30)
 #define  WIN_BLEND_ENABLE              (0 << 24)
 #define  WIN_BLEND_BYPASS              (1 << 24)
 
-#define DC_WINBUF_BLEND_MATCH_SELECT           0x717
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO \
-                                       (0 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE \
-                                       (1 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 \
-                                       (2 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST \
-                                       (3 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST \
-                                       (4 << 0)
-#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC \
-                                       (5 << 0)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO \
-                                       (0 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE \
-                                       (1 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1 \
-                                       (2 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2 \
-                                       (3 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST \
-                                       (4 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST \
-                                       (5 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC \
-                                       (6 << 4)
-#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 \
-                                       (7 << 4)
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO \
-                                       (0 << 8)
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1 \
-                                       (1 << 8)
-#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 \
-                                       (2 << 8)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO \
-                                       (0 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE \
-                                       (1 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC \
-                                       (2 << 12)
-#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2 \
-                                       (3 << 12)
+#define DC_WINBUF_BLEND_MATCH_SELECT           0x717
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO               (0 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE                        (1 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1                 (2 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST       (3 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST   (4 << 0)
+#define  WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC       (5 << 0)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO               (0 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE                        (1 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1                 (2 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2                 (3 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST       (4 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST   (5 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC   (6 << 4)
+#define  WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1             (7 << 4)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO               (0 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1                 (1 << 8)
+#define  WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2                 (2 << 8)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO               (0 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE                        (1 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC   (2 << 12)
+#define  WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2                 (3 << 12)
 
 #define DC_WINBUF_BLEND_ALPHA_1BIT             0x719
 #define  WIN_ALPHA_1BIT_WEIGHT0(x)     (((x) & 0xff) << 0)
index b5ffeeb..dec8da9 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dp.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -466,15 +466,15 @@ static int tegra_dc_init_max_link_cfg(struct tegra_dc_dp_data *dp,
 static bool tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp,
        struct tegra_dc_dp_link_config *cfg)
 {
-       if (cfg->link_bw == DP_LINK_SPEED_G1_62) {
-               if (cfg->max_link_bw > DP_LINK_SPEED_G1_62)
-                       cfg->link_bw = DP_LINK_SPEED_G2_7;
+       if (cfg->link_bw == SOR_LINK_SPEED_G1_62) {
+               if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
+                       cfg->link_bw = SOR_LINK_SPEED_G2_7;
                cfg->lane_count /= 2;
-       } else if (cfg->link_bw == DP_LINK_SPEED_G2_7)
-               cfg->link_bw = DP_LINK_SPEED_G1_62;
-       else if (cfg->link_bw == DP_LINK_SPEED_G5_4) {
+       } else if (cfg->link_bw == SOR_LINK_SPEED_G2_7)
+               cfg->link_bw = SOR_LINK_SPEED_G1_62;
+       else if (cfg->link_bw == SOR_LINK_SPEED_G5_4) {
                if (cfg->lane_count == 1) {
-                       cfg->link_bw = DP_LINK_SPEED_G2_7;
+                       cfg->link_bw = SOR_LINK_SPEED_G2_7;
                        cfg->lane_count = cfg->max_lane_count;
                } else
                        cfg->lane_count /= 2;
@@ -503,8 +503,8 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
        u64     activecount_f;
        u32     activecount;
        u32     activepolarity;
-       u32     activefrac;
        u64     approx_value_f;
+       u32     activefrac                = 0;
        u64     accumulated_error_f       = 0;
        u32     lowest_neg_activecount    = 0;
        u32     lowest_neg_activepolarity = 0;
@@ -699,7 +699,7 @@ static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
        tegra_dc_sor_set_lane_count(dp->sor, cfg->lane_count);
 
        /* Also power down lanes that will not be used */
-       return tegra_dc_sor_powerdown_dplanes(dp->sor, cfg->lane_count);
+       return tegra_dc_sor_power_dplanes(dp->sor, cfg->lane_count);
 }
 
 static int tegra_dc_dp_set_lane_config(struct tegra_dc_dp_data *dp,
@@ -806,7 +806,7 @@ static int tegra_dc_dp_set_lane_config(struct tegra_dc_dp_data *dp,
 
 
 static int tegra_dc_dpcd_read_lane_request(struct tegra_dc_dp_data *dp,
-       u32 lane_count, u8 *edc, u8* c2)
+       u32 lane_count, u8 *edc, u8 *c2)
 {
        u32 size;
        int ret;
@@ -1413,7 +1413,7 @@ static void tegra_dc_dp_enable(struct tegra_dc *dc)
        }
 
        /* enable SOR by programming the watermark/v/hblank_sym etc */
-       tegra_dc_sor_enable(dp->sor);
+       tegra_dc_sor_enable_dp(dp->sor);
 }
 
 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
@@ -1437,7 +1437,7 @@ static void tegra_dc_dp_disable(struct tegra_dc *dc)
        tegra_dc_dpaux_disable(dp);
 
        /* Power down SOR */
-       tegra_dc_sor_disable(dp->sor);
+       tegra_dc_sor_disable(dp->sor, false);
 
        clk_disable(dp->clk);
        /* TODO: Now power down the panel -- through GPIO */
index 138dc8a..e5a72fc 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dp.h
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
 
 #include "sor.h"
 
-#define DP_AUX_DEFER_MAX_TRIES     7
-#define DP_AUX_TIMEOUT_MAX_TRIES    2
-#define DP_POWER_ON_MAX_TRIES      3
-#define DP_CLOCK_RECOVERY_MAX_TRIES 7
-#define DP_CLOCK_RECOVERY_TOT_TRIES 15
+#define DP_AUX_DEFER_MAX_TRIES         7
+#define DP_AUX_TIMEOUT_MAX_TRIES       2
+#define DP_POWER_ON_MAX_TRIES          3
+#define DP_CLOCK_RECOVERY_MAX_TRIES    7
+#define DP_CLOCK_RECOVERY_TOT_TRIES    15
 
-#define DP_AUX_MAX_BYTES           16
+#define DP_AUX_MAX_BYTES               16
 
-#define DP_LCDVCC_TO_HPD_DELAY_MS   200
-#define DP_AUX_TIMEOUT_MS          40
-#define DP_DPCP_RETRY_SLEEP_NS     400
-
-
-#define DP_LINK_SPEED_G1_62        6
-#define DP_LINK_SPEED_G2_7         10
-#define DP_LINK_SPEED_G5_4         20
+#define DP_LCDVCC_TO_HPD_DELAY_MS      200
+#define DP_AUX_TIMEOUT_MS              40
+#define DP_DPCP_RETRY_SLEEP_NS         400
 
 enum {
        driveCurrent_Level0 = 0,
index 3b3d330..e7fc70d 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2102, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -105,6 +105,14 @@ static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
        writel(val, sor->base + reg * 4);
 }
 
+static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
+       unsigned long reg, u32 mask, u32 val)
+{
+       u32 reg_val = tegra_sor_readl(sor, reg);
+       reg_val &= ~mask;
+       reg_val |= val;
+       tegra_sor_writel(sor, reg, reg_val);
+}
 
 static unsigned long tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
        u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
@@ -151,28 +159,19 @@ static int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor,
 
        reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER;
        tegra_sor_writel(sor, NV_SOR_PWR, reg_val);
-       return 0;
-}
-
-void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor)
-{
-       /* Power down the SOR sequencer */
-       if ((tegra_dc_sor_set_power_state(sor, 0))) {
-               dev_err(&sor->dc->ndev->dev,
-                       "Failed to power down SOR sequencer\n");
-               return;
-       }
 
-       /* Power down DP lanes */
-       if (tegra_dc_sor_powerdown_dplanes(sor, 0)) {
+       /* Poll to confirm it is done */
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+                       NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
+                       NV_SOR_PWR_SETTING_NEW_DONE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
                dev_err(&sor->dc->ndev->dev,
-                       "Failed to power down dp lanes\n");
-               return;
+                       "dc timeout waiting for SOR_PWR = NEW_DONE\n");
+               return -EFAULT;
        }
-
-       clk_disable(sor->clk);
+       return 0;
 }
-EXPORT_SYMBOL(tegra_dc_sor_disable);
+
 
 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor)
 {
@@ -274,20 +273,29 @@ void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
 EXPORT_SYMBOL(tegra_dc_sor_set_dp_lanedata);
 
 
-int tegra_dc_sor_powerdown_dplanes(struct tegra_dc_sor_data *sor,
+int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
        u32 lane_count)
 {
        unsigned long reg_val;
 
-       reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
+       reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)) | 0xf;
 
-       if (lane_count < 4)
+       switch (lane_count) {
+       case 4:
                reg_val &= (NV_SOR_DP_PADCTL_PD_TXD_3_YES |
                        NV_SOR_DP_PADCTL_PD_TXD_2_YES);
-       if (lane_count < 2)
+               /* fall through */
+       case 2:
                reg_val &= NV_SOR_DP_PADCTL_PD_TXD_1_YES;
-       if (lane_count < 1)
+       case 1:
                reg_val &= NV_SOR_DP_PADCTL_PD_TXD_0_YES;
+               break;
+       default:
+               dev_dbg(&sor->dc->ndev->dev,
+                       "dp: invalid lane number %d\n", lane_count);
+               return -EFAULT;
+       }
+
        tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
 
        /* SOR lane sequencer */
@@ -306,7 +314,7 @@ int tegra_dc_sor_powerdown_dplanes(struct tegra_dc_sor_data *sor,
        }
        return 0;
 }
-EXPORT_SYMBOL(tegra_dc_sor_powerdown_dplanes);
+EXPORT_SYMBOL(tegra_dc_sor_power_dplanes);
 
 
 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
@@ -329,17 +337,13 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
 EXPORT_SYMBOL(tegra_dc_sor_set_panel_power);
 
 
-void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
-       u32 pwm_dutycycle, u32 pwm_clksrc)
+static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
+       u32 pwm_dutycycle)
 {
-       unsigned long reg_val;
-
        tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
-
-       reg_val = pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK;
-       reg_val |= (pwm_clksrc << NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT);
-       reg_val |= NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER;
-       tegra_sor_writel(sor, NV_SOR_PWM_CTL, reg_val);
+       tegra_sor_writel(sor, NV_SOR_PWM_CTL,
+               (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
+               NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
 
        if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
                        NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
@@ -349,16 +353,13 @@ void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
                        "dp: timeout while waiting for SOR PWM setting\n");
        }
 }
-EXPORT_SYMBOL(tegra_dc_sor_config_pwm);
 
 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
        const struct tegra_dc_dp_link_config *cfg)
 {
        unsigned long reg_val;
 
-       reg_val = NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
-       reg_val |= (cfg->link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
-       tegra_sor_writel(sor, NV_SOR_CLK_CNTRL, reg_val);
+       tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
 
        /* TODO: SOR_NV_PDISP_SOR_REFCL */
        /* tegra_dc_sor_set_dp_linkctl(sor, true,
@@ -395,13 +396,483 @@ static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
                reg_val);
 }
 
-void tegra_dc_sor_enable(struct tegra_dc_sor_data *sor)
+static void tegra_dc_sor_poweron(struct tegra_dc_sor_data *sor, u32 vdd_mode)
+{
+       /* enable PLL */
+       tegra_sor_writel(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
+               NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE |
+               NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE |
+               NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE |
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
+       tegra_sor_writel(sor, NV_SOR_PLL0,
+               NV_SOR_PLL0_VCOPD_RESCIND |
+               NV_SOR_PLL0_PWR_ON);
+       tegra_sor_writel(sor, NV_SOR_PLL3, vdd_mode);
+}
+
+static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 {
-       enable_clk(sor->clk);
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1);
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
+}
+
+static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
+{
+       tegra_sor_writel(sor, NV_SOR_STATE0, 0);
+       tegra_sor_writel(sor, NV_SOR_STATE0, 1);
+       tegra_sor_writel(sor, NV_SOR_STATE0, 0);
+}
+
+static inline void tegra_dc_sor_enable_sequencer(struct tegra_dc_sor_data *sor)
+{
+       tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum),
+               NV_SOR_DP_SPARE_SEQ_ENABLE_YES);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_CTL,
+               (8 << NV_SOR_SEQ_CTL_PD_PC_SHIFT) |
+               (8 << NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT));
+
+       tegra_sor_write_field(sor, NV_SOR_LANE_SEQ_CTL,
+               NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK, 0);
+}
+
+static void tegra_dc_sor_sequencer_dp_start(struct tegra_dc_sor_data *sor)
+{
+       tegra_dc_sor_enable_sequencer(sor);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
+               NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+               NV_SOR_SEQ_INST_HALT_TRUE |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_LANE_SEQ_RUN);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(8),
+               NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+               NV_SOR_SEQ_INST_HALT_TRUE |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_LANE_SEQ_RUN |
+               NV_SOR_SEQ_INST_SEQUENCE_DOWN);
+}
+
+static void tegra_dc_sor_sequencer_lvds_start(struct tegra_dc_sor_data *sor)
+{
+       tegra_dc_sor_enable_sequencer(sor);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_BLACK |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
+               NV_SOR_SEQ_INST_PIN_A_LOW |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_STOP |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_FALSE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_US |
+               0 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(1),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_BLACK |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
+               NV_SOR_SEQ_INST_PIN_A_HIGH |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_STOP |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_FALSE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_US |
+               1 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(2),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
+               NV_SOR_SEQ_INST_PIN_A_HIGH |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_RUN |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_FALSE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_US |
+               33 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(3),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
+               NV_SOR_SEQ_INST_PIN_A_HIGH |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_STOP |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_FALSE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_US |
+               205 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(4),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE |
+               NV_SOR_SEQ_INST_PIN_B_HIGH |
+               NV_SOR_SEQ_INST_PIN_A_HIGH |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_STOP |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_FALSE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+               0 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(5),
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE |
+               NV_SOR_SEQ_INST_PIN_B_HIGH |
+               NV_SOR_SEQ_INST_PIN_A_HIGH |
+               NV_SOR_SEQ_INST_SEQUENCE_UP |
+               NV_SOR_SEQ_INST_LANE_SEQ_STOP |
+               NV_SOR_SEQ_INST_PDPORT_NO |
+               NV_SOR_SEQ_INST_PDPLL_NO |
+               NV_SOR_SEQ_INST_HALT_TRUE |
+               NV_SOR_SEQ_INST_WAIT_UNITS_US |
+               0 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+                       NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
+                       NV_SOR_PWR_SETTING_NEW_DONE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for SOR_PWR = DONE\n");
+               return;
+       }
+}
+
+static void tegra_dc_sor_sequencer_lvds_stop(struct tegra_dc_sor_data *sor)
+{
+       tegra_dc_sor_enable_sequencer(sor);
+
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
+               NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+               1 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(1),
+               NV_SOR_SEQ_INST_BLANK_V_INACTIVE |
+               NV_SOR_SEQ_INST_BLANK_H_INACTIVE |
+               NV_SOR_SEQ_INST_BLANK_DE_INACTIVE |
+               NV_SOR_SEQ_INST_BLACK_DATA_BLACK |
+               NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+               1 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT);
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(2),
+               NV_SOR_SEQ_INST_PIN_B_LOW |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE);
+       tegra_sor_writel(sor, NV_SOR_SEQ_INST(3),
+               NV_SOR_SEQ_INST_LANE_SEQ_RUN |
+               NV_SOR_SEQ_INST_SEQUENCE_DOWN);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+                       NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
+                       NV_SOR_PWR_SETTING_NEW_DONE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for SOR_PWR = DONE\n");
+               return;
+       }
+}
+
+static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
+       bool is_lvds)
+{
+       const struct tegra_dc_out_pin   *pins     = sor->dc->out->out_pins;
+       const struct tegra_dc_mode      *dc_mode  = sor->dc->out->modes;
+
+       const int       head_num = sor->dc->ndev->id;
+       u32             reg_val  = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
+       u32             vtotal, htotal;
+       u32             vsync_end, hsync_end;
+       u32             vblank_end, hblank_end;
+       u32             vblank_start, hblank_start;
+       int             i;
+
+       reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
+               NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
+       reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_BOTH;
+
+       for (i = 0; pins && (i < sor->dc->out->n_out_pins); i++) {
+               switch (pins[i].name) {
+               case TEGRA_DC_OUT_PIN_DATA_ENABLE:
+                       if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
+                               reg_val |=
+                               NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE;
+                       break;
+               case TEGRA_DC_OUT_PIN_H_SYNC:
+                       if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
+                               reg_val |=
+                               NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
+                       break;
+               case TEGRA_DC_OUT_PIN_V_SYNC:
+                       if (pins[i].pol == TEGRA_DC_OUT_PIN_POL_LOW)
+                               reg_val |=
+                               NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
+                       break;
+               default:        /* Ignore other pin setting */
+                       break;
+               }
+       }
+
+       reg_val |= (sor->dc->pdata->fb->bits_per_pixel > 16) ?
+               NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
+               NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
+
+       BUG_ON(!dc_mode);
+       vtotal = dc_mode->v_sync_width + dc_mode->v_back_porch +
+               dc_mode->v_active + dc_mode->v_front_porch;
+       htotal = dc_mode->h_sync_width + dc_mode->h_back_porch +
+               dc_mode->h_active + dc_mode->h_front_porch;
+       tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
+               vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
+               htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
+
+       vsync_end = dc_mode->v_sync_width - dc_mode->v_ref_to_sync;
+       hsync_end = dc_mode->h_sync_width - dc_mode->h_ref_to_sync;
+       tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
+               vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
+               hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
+
+       vblank_end = dc_mode->v_sync_width + dc_mode->v_back_porch
+               - dc_mode->v_ref_to_sync;
+       hblank_end = dc_mode->h_sync_width + dc_mode->h_back_porch
+               - dc_mode->h_ref_to_sync;
+       tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
+               vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
+               hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
+
+       vblank_start = vblank_end + dc_mode->v_active;
+       hblank_start = hblank_end + dc_mode->h_active;
+       tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
+               vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
+               hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
+
+       /* TODO: setup rotclk */
+
+       tegra_dc_sor_config_pwm(sor, 1024, 1024);
+}
+
+void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
+{
+       unsigned long reg_val;
+
+       tegra_dc_sor_poweron(sor, NV_SOR_PLL3_PLLVDD_MODE_V3_3);
+       tegra_dc_sor_power_dplanes(sor, sor->link_cfg->lane_count);
        tegra_dc_sor_set_dp_mode(sor, sor->link_cfg);
+
+       tegra_dc_sor_sequencer_dp_start(sor);
+       tegra_dc_sor_set_power_state(sor, 1);
+       tegra_dc_sor_config_panel(sor, false);
+       tegra_dc_sor_update(sor);
+
+       reg_val = NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
+               NV_SOR_SUPER_STATE1_ATTACHED_NO;
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, reg_val);
+       tegra_dc_sor_super_update(sor);
+
+       reg_val |= NV_SOR_SUPER_STATE1_ATTACHED_YES;
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, reg_val);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
+                       NV_SOR_TEST_ATTACHED_TRUE,
+                       100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ATTACHED = TRUE\n");
+       }
 }
-EXPORT_SYMBOL(tegra_dc_sor_enable);
+EXPORT_SYMBOL(tegra_dc_sor_enable_dp);
+
+void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor)
+{
+       tegra_dc_sor_poweron(sor, NV_SOR_PLL3_PLLVDD_MODE_V1_8);
+       tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
+               NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK,
+               NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK);
+
+       /* TODO: check if balanced mode is needed
+                check ROTDAT setting */
+       tegra_sor_writel(sor, NV_SOR_LVDS,
+               NV_SOR_LVDS_LINKACTB_DISABLE |
+               NV_SOR_LVDS_PD_TXCB_DISABLE |
+               NV_SOR_LVDS_PD_TXDB_3_DISABLE |
+               NV_SOR_LVDS_PD_TXDB_2_DISABLE |
+               NV_SOR_LVDS_PD_TXDB_1_DISABLE |
+               NV_SOR_LVDS_PD_TXDB_0_DISABLE |
+               NV_SOR_LVDS_PD_TXDA_2_ENABLE |
+               NV_SOR_LVDS_PD_TXDA_1_ENABLE |
+               NV_SOR_LVDS_PD_TXDA_0_ENABLE);
+
+       tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
+       tegra_dc_sor_config_panel(sor, true);
+       tegra_dc_sor_update(sor);
+
+       /* Attaching */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
+                       NV_SOR_TEST_ATTACHED_TRUE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ATTACHED = TRUE\n");
+               return;
+       }
+
+       /* OR mode: normal */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       /* then awake */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       /* TODO: check if display controller needs to start now*/
+       tegra_dc_sor_sequencer_lvds_start(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+                       NV_SOR_PWR_MODE_DEFAULT_MASK,
+                       NV_SOR_PWR_MODE_NORMAL,
+                       100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ATTACHED = TRUE\n");
+               return;
+       }
+}
+EXPORT_SYMBOL(tegra_dc_sor_enable_lvds);
+
+void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
+{
+       /* #1: safe mode */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+                       NV_SOR_PWR_MODE_DEFAULT_MASK,
+                       NV_SOR_PWR_MODE_SAFE,
+                       100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for SOR_PWR = NEW_DONE\n");
+               return;
+       }
 
+       if (is_lvds)
+               tegra_dc_sor_sequencer_lvds_stop(sor);
+
+       /* #2: sleep */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
+                       NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ACT_HEAD_OPMODE = SLEEP\n");
+               return;
+       }
+
+       /* #3: detach */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+               NV_SOR_SUPER_STATE1_ATTACHED_NO);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
+                       NV_SOR_TEST_ATTACHED_FALSE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ATTACHED = FALSE\n");
+               return;
+       }
+
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_STATE1_ASY_OWNER_NONE |
+               NV_SOR_STATE1_ASY_SUBOWNER_NONE |
+               NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM);
+       tegra_dc_sor_update(sor);
+
+       /* TODO: need to program:
+          DISP_WIN_OPTIONS(SOR_DISABLE)
+          DISPLAY_COMMAND(DISPLAY_CTRL_MODE_STOP)
+          DISPLAY_POWER_CONTROL(POWER_ENABLE_DISABLE)
+        */
+
+       /* Power down the SOR sequencer */
+       if ((tegra_dc_sor_set_power_state(sor, 0))) {
+               dev_err(&sor->dc->ndev->dev,
+                       "Failed to power down SOR sequencer\n");
+               return;
+       }
+
+       /* Power down DP lanes */
+       if (!is_lvds && tegra_dc_sor_power_dplanes(sor, 0)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "Failed to power down dp lanes\n");
+               return;
+       }
+
+       clk_disable(sor->sor_clk);
+}
+EXPORT_SYMBOL(tegra_dc_sor_disable);
 
 int tegra_dc_sor_set_dp_packet(struct tegra_dc_sor_data *sor,
        u8 *packet)
index c3effe8..bb85c07 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * drivers/video/tegra/dc/sor.h
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -26,6 +26,16 @@ enum {
        trainingPattern_None            = 0xff
 };
 
+enum tegra_dc_sor_protocol {
+       SOR_DP,
+       SOR_LVDS,
+};
+
+#define SOR_LINK_SPEED_G1_62   6
+#define SOR_LINK_SPEED_G2_7    10
+#define SOR_LINK_SPEED_G5_4    20
+#define SOR_LINK_SPEED_LVDS    7
+
 struct tegra_dc_dp_link_config {
        bool    is_valid;
 
@@ -66,7 +76,8 @@ struct tegra_dc_sor_data {
        const struct tegra_dc_dp_link_config    *link_cfg;
 };
 
-#define TEGRA_SOR_TIMEOUT_MS  1000
+#define TEGRA_SOR_TIMEOUT_MS           1000
+#define TEGRA_SOR_ATTACH_TIMEOUT_MS    100000
 
 #define CHECK_RET(x)                   \
        do {                            \
@@ -80,8 +91,9 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
        const struct tegra_dc_dp_link_config *cfg);
 
 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor);
-void tegra_dc_sor_enable(struct tegra_dc_sor_data *sor);
-void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds);
 
 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor,
        bool is_int);
@@ -94,8 +106,7 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
        bool power_up);
 void tegra_dc_sor_set_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
        u32 pwm_dutycycle, u32 pwm_clksrc);
-int  tegra_dc_sor_powerdown_dplanes(struct tegra_dc_sor_data *sor,
-       u32 lane_count);
+int  tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, u32 lane_count);
 void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
        u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu);
 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
index 85054a0..1d95a28 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor_regs.h
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
 #define __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
 
 
-#define NV_SOR_CLK_CNTRL                                       (0x7)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT                      (0)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK                       (0x3)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK                        (0)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK                  (1)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK               (2)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK                 (3)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT                   (2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK                    (0x1f << 2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62                   (6 << 2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7                    (10 << 2)
-#define NV_SOR_CAP                                             (0x1e)
-#define NV_SOR_CAP_DP_A_SHIFT                                  (24)
-#define NV_SOR_CAP_DP_A_DEFAULT_MASK                           (0x1 << 24)
-#define NV_SOR_CAP_DP_A_FALSE                                  (0 << 24)
-#define NV_SOR_CAP_DP_A_TRUE                                   (1 << 24)
-#define NV_SOR_CAP_DP_B_SHIFT                                  (25)
-#define NV_SOR_CAP_DP_B_DEFAULT_MASK                           (0x1 << 24)
-#define NV_SOR_CAP_DP_B_FALSE                                  (0 << 24)
-#define NV_SOR_CAP_DP_B_TRUE                                   (1 << 24)
-#define NV_SOR_PWR                                             (0x1f)
-#define NV_SOR_PWR_SETTING_NEW_SHIFT                           (31)
-#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK                    (0x1 << 31)
-#define NV_SOR_PWR_SETTING_NEW_PENDING                         (1 << 31)
-#define NV_SOR_PWR_SETTING_NEW_TRIGGER                         (1 << 31)
-#define NV_SOR_PWR_MODE_SHIFT                                  (28)
-#define NV_SOR_PWR_MODE_DEFAULT_MASK                           (0x1 << 28)
-#define NV_SOR_PWR_MODE_NORMAL                                 (0 << 28)
-#define NV_SOR_PWR_MODE_SAFE                                   (1 << 28)
-#define NV_SOR_PWR_HALT_DELAY_SHIFT                            (24)
-#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK                     (0x1 << 24)
-#define NV_SOR_PWR_HALT_DELAY_DONE                             (0 << 24)
-#define NV_SOR_PWR_HALT_DELAY_ACTIVE                           (1 << 24)
-#define NV_SOR_PWR_SAFE_START_SHIFT                            (17)
-#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK                     (0x1 << 17)
-#define NV_SOR_PWR_SAFE_START_NORMAL                           (0 << 17)
-#define NV_SOR_PWR_SAFE_START_ALT                              (1 << 17)
-#define NV_SOR_PWR_SAFE_STATE_SHIFT                            (16)
-#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK                     (0x1 << 16)
-#define NV_SOR_PWR_SAFE_STATE_PD                               (0 << 16)
-#define NV_SOR_PWR_SAFE_STATE_PU                               (1 << 16)
-#define NV_SOR_PWR_NORMAL_START_SHIFT                          (1)
-#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK                   (0x1 << 1)
-#define NV_SOR_PWR_NORMAL_START_NORMAL                         (0 << 16)
-#define NV_SOR_PWR_NORMAL_START_ALT                            (1 << 16)
-#define NV_SOR_PWR_NORMAL_STATE_SHIFT                          (0)
-#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK                   (0x1)
-#define NV_SOR_PWR_NORMAL_STATE_PD                             (0)
-#define NV_SOR_PWR_NORMAL_STATE_PU                             (1)
-#define NV_SOR_SEQ_CTL                                         (0x2c)
-#define NV_SOR_SEQ_CTL_SWITCH_SHIFT                            (30)
-#define NV_SOR_SEQ_CTL_SWITCH_MASK                             (0x1 << 30)
-#define NV_SOR_SEQ_CTL_SWITCH_WAIT                             (0 << 30)
-#define NV_SOR_SEQ_CTL_SWITCH_FORCE                            (1 << 30)
-#define NV_SOR_SEQ_CTL_STATUS_SHIFT                            (28)
-#define NV_SOR_SEQ_CTL_STATUS_MASK                             (0x1 << 28)
-#define NV_SOR_SEQ_CTL_STATUS_STOPPED                          (0 << 28)
-#define NV_SOR_SEQ_CTL_STATUS_RUNNING                          (1 << 28)
-#define NV_SOR_SEQ_CTL_PC_SHIFT                                        (16)
-#define NV_SOR_SEQ_CTL_PC_MASK                                 (0xf << 16)
-#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT                         (12)
-#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK                          (0xf << 12)
-#define NV_SOR_SEQ_CTL_PD_PC_SHIFT                             (8)
-#define NV_SOR_SEQ_CTL_PD_PC_MASK                              (0xf << 8)
-#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT                         (4)
-#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK                          (0xf << 4)
-#define NV_SOR_SEQ_CTL_PU_PC_SHIFT                             (0)
-#define NV_SOR_SEQ_CTL_PU_PC_MASK                              (0xf)
-#define NV_SOR_LANE_SEQ_CTL                                    (0x2d)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT                  (31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK                       (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING                        (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER                        (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT                    (28)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE                     (0 << 28)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY                     (1 << 28)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT                     (20)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP                                (0 << 20)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN                      (1 << 20)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT              (16)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU                 (0 << 16)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD                 (1 << 16)
-#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT                                (12)
-#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK                 (0xf << 12)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT                  (9)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP                        (0 << 9)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN              (1 << 9)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT                  (8)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP                        (0 << 8)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN              (1 << 8)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT                  (7)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP                        (0 << 7)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN              (1 << 7)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT                  (6)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP                        (0 << 6)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN              (1 << 6)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT                  (5)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP                        (0 << 5)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN              (1 << 5)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT                  (4)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP                        (0 << 4)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN              (1 << 4)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT                  (3)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP                        (0 << 3)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN              (1 << 3)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT                  (2)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP                        (0 << 2)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN              (1 << 2)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT                  (1)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP                        (0 << 1)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN              (1 << 1)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT                  (0)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP                        (0)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN              (1)
-#define NV_SOR_PWM_DIV                                         (0x3e)
-#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_DEFAULT_MASK         (0xffffff)
-#define NV_SOR_PWM_CTL                                         (0x3f)
-#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT                       (31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_DONE                                (0 << 31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING                     (1 << 31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER                     (1 << 31)
-#define NV_SOR_PWM_CTL_CLKSEL_SHIFT                            (30)
-#define NV_SOR_PWM_CTL_CLKSEL_PCLK                             (0 << 30)
-#define NV_SOR_PWM_CTL_CLKSEL_XTAL                             (1 << 30)
-#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT                                (0)
-#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK                         (0xffffff)
-#define NV_SOR_DP_LINKCTL(i)                                   (0x5a + (i))
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT                        (31)
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO                   (0 << 31)
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES                  (1 << 31)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT                        (28)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN            (0 << 28)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE           (1 << 28)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SHIFT                  (26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_MASK                   (0x3 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN              (0 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_D102                   (1 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE             (2 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7                  (3 << 26)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_SHIFT                  (24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_MASK                   (0x3 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_NOPATTERN              (0 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING1              (1 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING2              (2 << 24)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_SHIFT                  (22)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_DISABLE                        (0 << 22)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_ENABLE                 (1 << 22)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT                      (16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK                       (0x1f << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO                       (0 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE                                (1 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO                                (3 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR                       (15 << 16)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT                  (14)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                        (0 << 14)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE                 (1 << 14)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_SHIFT                    (12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_MASK                     (0x3 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_DISABLE                  (0 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_GALIOS            (1 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_FIBONACCI         (2 << 12)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT                       (10)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE                     (0 << 10)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE                      (1 << 10)
-#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT                         (2)
-#define NV_SOR_DP_LINKCTL_TUSIZE_MASK                          (0x7f << 2)
-#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT                         (0)
-#define NV_SOR_DP_LINKCTL_ENABLE_NO                            (0)
-#define NV_SOR_DP_LINKCTL_ENABLE_YES                           (1)
-#define NV_SOR_DC(i)                                           (0x5c + (i))
-#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT                         (24)
-#define NV_SOR_DC_LANE3_DP_LANE3_MASK                          (0xff << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0                     (17 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0                     (21 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0                     (26 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0                     (34 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1                     (26 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1                     (32 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1                     (39 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2                     (34 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2                     (43 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3                     (51 << 24)
-#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                         (16)
-#define NV_SOR_DC_LANE2_DP_LANE0_MASK                          (0xff << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0                     (17 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0                     (21 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0                     (26 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0                     (34 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1                     (26 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1                     (32 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1                     (39 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2                     (34 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2                     (43 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3                     (51 << 16)
-#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                         (8)
-#define NV_SOR_DC_LANE1_DP_LANE1_MASK                          (0xff << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0                     (17 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0                     (21 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0                     (26 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0                     (34 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1                     (26 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1                     (32 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1                     (39 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2                     (34 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2                     (43 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3                     (51 << 8)
-#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                         (0)
-#define NV_SOR_DC_LANE0_DP_LANE2_MASK                          (0xff)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0                     (17)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0                     (21)
-#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0                     (26)
-#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0                     (34)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1                     (26)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1                     (32)
-#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1                     (39)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2                     (34)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2                     (43)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3                     (51)
-#define NV_SOR_LANE4_DRIVE_CURRENT(i)                          (0x5e + (i))
-#define NV_SOR_PR(i)                                           (0x60 + (i))
-#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                         (24)
-#define NV_SOR_PR_LANE3_DP_LANE3_MASK                          (0xff << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0                     (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0                     (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0                     (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0                     (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1                     (4 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1                     (6 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1                     (17 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2                     (8 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2                     (13 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3                     (17 << 24)
-#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT                         (16)
-#define NV_SOR_PR_LANE2_DP_LANE0_MASK                          (0xff << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0                     (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0                     (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0                     (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0                     (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1                     (4 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1                     (6 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1                     (17 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2                     (8 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2                     (13 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3                     (17 << 16)
-#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT                         (8)
-#define NV_SOR_PR_LANE1_DP_LANE1_MASK                          (0xff >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0                     (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0                     (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0                     (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0                     (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1                     (4 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1                     (6 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1                     (17 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2                     (8 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2                     (13 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3                     (17 >> 8)
-#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT                         (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_MASK                          (0xff)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0                     (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0                     (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0                     (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0                     (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1                     (4)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1                     (6)
-#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1                     (17)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2                     (8)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2                     (13)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3                     (17)
-#define NV_SOR_LANE4_PREEMPHASIS(i)                            (0x62 + (i))
-#define NV_SOR_DP_CONFIG(i)                                    (0x64 + (i))
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT                    (31)
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE                 (0 << 31)
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE                 (1 << 31)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT              (28)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE            (0 << 28)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE             (1 << 28)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT                  (26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE                        (0 << 26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE                 (1 << 26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT              (24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE           (0 << 24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE           (1 << 24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT                  (16)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK                   (0xf << 16)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT                 (8)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK                  (0x7f << 8)
-#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT                       (0)
-#define NV_SOR_DP_CONFIG_WATERMARK_MASK                                (0x3f)
-#define NV_SOR_DP_PADCTL(i)                                    (0x68 + (i))
-#define NV_SOR_DP_PADCTL_SPARE_SHIFT                           (25)
-#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK                    (0x7f << 25)
-#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT                          (24)
-#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE                                (0 << 24)
-#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE                         (1 << 24)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT                      (23)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP                    (0 << 23)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN                  (1 << 23)
-#define NV_SOR_DP_PADCTL_TX_PU_SHIFT                           (22)
-#define NV_SOR_DP_PADCTL_TX_PU_DISABLE                         (0 << 22)
-#define NV_SOR_DP_PADCTL_TX_PU_ENABLE                          (1 << 22)
-#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT                                (20)
-#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK                 (0x3 << 20)
-#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT                         (16)
-#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK                  (0xf << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE                      (0 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX                      (1 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN                 (2 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN               (4 << 16)
-#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT                     (8)
-#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK              (0xff << 8)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_3_DP_TXD_3_SHIFT       (7)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_3_DP_TXD_3_DISABLE     (0 << 7)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_3_DP_TXD_3_ENABLE      (1 << 7)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_2_DP_TXD_0_SHIFT       (6)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_2_DP_TXD_0_DISABLE     (0 << 6)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_2_DP_TXD_0_ENABLE      (1 << 6)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_1_DP_TXD_1_SHIFT       (5)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_1_DP_TXD_1_DISABLE     (0 << 5)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_1_DP_TXD_1_ENABLE      (1 << 5)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_0_DP_TXD_2_SHIFT       (4)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_0_DP_TXD_2_DISABLE     (0 << 4)
-#define NV_SOR_DP_PADCTL_COMMONMODE_TXD_0_DP_TXD_2_ENABLE      (1 << 4)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT                                (3)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_YES                          (0 << 3)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_NO                           (1 << 3)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT                                (2)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_YES                          (0 << 2)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_NO                           (1 << 2)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT                                (1)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_YES                          (0 << 1)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_NO                           (1 << 1)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT                                (0)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_YES                          (0)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_NO                           (1)
-#define NV_SOR_DP_SPARE(i)                                     (0x6c + (i))
-#define NV_SOR_DP_SPARE_PANEL_SHIFT                            (1)
-#define NV_SOR_DP_SPARE_PANEL_EXTERNAL                         (0 << 1)
-#define NV_SOR_DP_SPARE_PANEL_INTERNAL                         (1 << 1)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT                       (0)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO                          (0)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES                         (1)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS                         (0x6e)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK                    (0x1ffff)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT             (0)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS                         (0x6f)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK                    (0x1ffff)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT                   (0)
-#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER                     (0x70)
-#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i)                 (0x71 + (i))
+#define NV_SOR_SUPER_STATE0                            (0x1)
+#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT               (0)
+#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK         (0x1)
+#define NV_SOR_SUPER_STATE1                            (0x2)
+#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT             (3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_NO                        (0 << 3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_YES               (1 << 3)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT            (2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE            (0 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL           (1 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT           (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK    (0x3)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP           (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE          (1)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE           (2)
+#define NV_SOR_STATE0                                  (0x3)
+#define NV_SOR_STATE0_UPDATE_SHIFT                     (0)
+#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK              (0x1)
+#define NV_SOR_STATE1                                  (0x4)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT             (17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK       (0xf << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422         (1 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444         (2 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422         (3 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422         (4 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444         (5 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444         (6 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422         (7 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444         (8 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444         (9 << 17)
+#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT              (15)
+#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK        (0x3 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_OFF                        (0 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X2                 (1 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X4                 (2 << 15)
+#define NV_SOR_STATE1_ASY_DEPOL_SHIFT                  (14)
+#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK            (0x1 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE           (0 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE           (1 << 14)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT               (13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK         (0x1 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE        (0 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE        (1 << 13)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT               (12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK         (0x1 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE        (0 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE        (1 << 12)
+#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT               (8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK         (0xf << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM          (0 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A                        (8 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B                        (9 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM              (15 << 8)
+#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT                        (6)
+#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK          (0x3 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER         (0 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER       (1 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER     (2 << 6)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT               (4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK         (0x3 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_NONE                        (0 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0            (1 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1            (2 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH                        (3 << 4)
+#define NV_SOR_STATE1_ASY_OWNER_SHIFT                  (0)
+#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK            (0xf)
+#define NV_SOR_STATE1_ASY_OWNER_NONE                   (0)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD0                  (1)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD1                  (2)
+#define NV_HEAD_STATE1(i)                              (0x7 + i)
+#define NV_HEAD_STATE1_VTOTAL_SHIFT                    (16)
+#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK             (0x7fff  << 16)
+#define NV_HEAD_STATE1_HTOTAL_SHIFT                    (0)
+#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK             (0x7fff)
+#define NV_HEAD_STATE2(i)                              (0x9 + i)
+#define NV_HEAD_STATE2_VSYNC_END_SHIFT                 (16)
+#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK          (0x7fff << 16)
+#define NV_HEAD_STATE2_HSYNC_END_SHIFT                 (0)
+#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK          (0x7fff)
+#define NV_HEAD_STATE3(i)                              (0xb + i)
+#define NV_HEAD_STATE3_VBLANK_END_SHIFT                        (16)
+#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK          (0x7fff << 16)
+#define NV_HEAD_STATE3_HBLANK_END_SHIFT                        (0)
+#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK          (0x7fff)
+#define NV_HEAD_STATE4(i)                              (0xd + i)
+#define NV_HEAD_STATE4_VBLANK_START_SHIFT              (16)
+#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK        (0x7fff << 16)
+#define NV_HEAD_STATE4_HBLANK_START_SHIFT              (0)
+#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK        (0x7fff)
+#define NV_SOR_CLK_CNTRL                               (0x13)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT              (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK               (0x3)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK                (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK          (1)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK       (2)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK         (3)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT           (2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK            (0x1f << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62           (6 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7            (10 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS            (7 << 2)
+#define NV_SOR_CAP                                     (0x14)
+#define NV_SOR_CAP_DP_A_SHIFT                          (24)
+#define NV_SOR_CAP_DP_A_DEFAULT_MASK                   (0x1 << 24)
+#define NV_SOR_CAP_DP_A_FALSE                          (0 << 24)
+#define NV_SOR_CAP_DP_A_TRUE                           (1 << 24)
+#define NV_SOR_CAP_DP_B_SHIFT                          (25)
+#define NV_SOR_CAP_DP_B_DEFAULT_MASK                   (0x1 << 24)
+#define NV_SOR_CAP_DP_B_FALSE                          (0 << 24)
+#define NV_SOR_CAP_DP_B_TRUE                           (1 << 24)
+#define NV_SOR_PWR                                     (0x15)
+#define NV_SOR_PWR_SETTING_NEW_SHIFT                   (31)
+#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK            (0x1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_DONE                    (0 << 31)
+#define NV_SOR_PWR_SETTING_NEW_PENDING                 (1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_TRIGGER                 (1 << 31)
+#define NV_SOR_PWR_MODE_SHIFT                          (28)
+#define NV_SOR_PWR_MODE_DEFAULT_MASK                   (0x1 << 28)
+#define NV_SOR_PWR_MODE_NORMAL                         (0 << 28)
+#define NV_SOR_PWR_MODE_SAFE                           (1 << 28)
+#define NV_SOR_PWR_HALT_DELAY_SHIFT                    (24)
+#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK             (0x1 << 24)
+#define NV_SOR_PWR_HALT_DELAY_DONE                     (0 << 24)
+#define NV_SOR_PWR_HALT_DELAY_ACTIVE                   (1 << 24)
+#define NV_SOR_PWR_SAFE_START_SHIFT                    (17)
+#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK             (0x1 << 17)
+#define NV_SOR_PWR_SAFE_START_NORMAL                   (0 << 17)
+#define NV_SOR_PWR_SAFE_START_ALT                      (1 << 17)
+#define NV_SOR_PWR_SAFE_STATE_SHIFT                    (16)
+#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK             (0x1 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PD                       (0 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PU                       (1 << 16)
+#define NV_SOR_PWR_NORMAL_START_SHIFT                  (1)
+#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK           (0x1 << 1)
+#define NV_SOR_PWR_NORMAL_START_NORMAL                 (0 << 16)
+#define NV_SOR_PWR_NORMAL_START_ALT                    (1 << 16)
+#define NV_SOR_PWR_NORMAL_STATE_SHIFT                  (0)
+#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK           (0x1)
+#define NV_SOR_PWR_NORMAL_STATE_PD                     (0)
+#define NV_SOR_PWR_NORMAL_STATE_PU                     (1)
+#define NV_SOR_TEST                                    (0x16)
+#define NV_SOR_TEST_TESTMUX_SHIFT                      (24)
+#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK               (0xff << 24)
+#define NV_SOR_TEST_TESTMUX_AVSS                       (0 << 24)
+#define NV_SOR_TEST_TESTMUX_CLOCKIN                    (2 << 24)
+#define NV_SOR_TEST_TESTMUX_PLL_VOL                    (4 << 24)
+#define NV_SOR_TEST_TESTMUX_SLOWCLKINT                 (8 << 24)
+#define NV_SOR_TEST_TESTMUX_AVDD                       (16 << 24)
+#define NV_SOR_TEST_TESTMUX_VDDREG                     (32 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG              (64 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_AVDD                        (128 << 24)
+#define NV_SOR_TEST_CRC_SHIFT                          (23)
+#define NV_SOR_TEST_CRC_PRE_SERIALIZE                  (0 << 23)
+#define NV_SOR_TEST_CRC_POST_DESERIALIZE               (1 << 23)
+#define NV_SOR_TEST_TPAT_SHIFT                         (20)
+#define NV_SOR_TEST_TPAT_DEFAULT_MASK                  (0x7 << 20)
+#define NV_SOR_TEST_TPAT_LO                            (0 << 20)
+#define NV_SOR_TEST_TPAT_TDAT                          (1 << 20)
+#define NV_SOR_TEST_TPAT_RAMP                          (2 << 20)
+#define NV_SOR_TEST_TPAT_WALK                          (3 << 20)
+#define NV_SOR_TEST_TPAT_MAXSTEP                       (4 << 20)
+#define NV_SOR_TEST_TPAT_MINSTEP                       (5 << 20)
+#define NV_SOR_TEST_DSRC_SHIFT                         (16)
+#define NV_SOR_TEST_DSRC_DEFAULT_MASK                  (0x3 << 16)
+#define NV_SOR_TEST_DSRC_NORMAL                                (0 << 16)
+#define NV_SOR_TEST_DSRC_DEBUG                         (1 << 16)
+#define NV_SOR_TEST_DSRC_TGEN                          (2 << 16)
+#define NV_SOR_TEST_HEAD_NUMBER_SHIFT                  (12)
+#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK            (0x0 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_NONE                   (0 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD0                  (1 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD1                  (2 << 12)
+#define NV_SOR_TEST_ATTACHED_SHIFT                     (10)
+#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK              (0x1  << 10)
+#define NV_SOR_TEST_ATTACHED_FALSE                     (0 << 10)
+#define NV_SOR_TEST_ATTACHED_TRUE                      (1 << 10)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT              (8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK        (0x0 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP              (0 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE             (1 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE              (2 << 8)
+#define NV_SOR_TEST_INVD_SHIFT                         (6)
+#define NV_SOR_TEST_INVD_DISABLE                       (0 << 6)
+#define NV_SOR_TEST_INVD_ENABLE                                (1 << 6)
+#define NV_SOR_TEST_TEST_ENABLE_SHIFT                  (1)
+#define NV_SOR_TEST_TEST_ENABLE_DISABLE                        (0 << 1)
+#define NV_SOR_TEST_TEST_ENABLE_ENABLE                 (1 << 1)
+#define NV_SOR_PLL0                                    (0x17)
+#define NV_SOR_PLL0_PWR_SHIFT                          (0)
+#define NV_SOR_PLL0_PWR_ON                             (0)
+#define NV_SOR_PLL0_PWR_OFF                            (1)
+#define NV_SOR_PLL0_VCOPD_SHIFT                                (2)
+#define NV_SOR_PLL0_VCOPD_RESCIND                      (0 << 2)
+#define NV_SOR_PLL0_VCOPD_ASSERT                       (1 << 2)
+#define NV_SOR_PLL2                                    (0x19)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT               (0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE            (0 << 0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW               (1 << 0)
+#define NV_SOR_PLL2_AUX1_SHIFT                         (17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW            (0 << 17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE         (1 << 17)
+#define NV_SOR_PLL2_AUX2_SHIFT                         (18)
+#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN            (0 << 18)
+#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN               (1 << 18)
+#define NV_SOR_PLL2_AUX6_SHIFT                         (22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE     (0 << 22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE      (1 << 22)
+#define NV_SOR_PLL2_AUX7_SHIFT                         (23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE                (0 << 23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE         (1 << 23)
+#define NV_SOR_PLL2_AUX8_SHIFT                         (24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE  (0 << 24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE   (1 << 24)
+#define NV_SOR_PLL3                                    (0x1a)
+#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT                  (13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V1_8                   (0 << 13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V3_3                   (1 << 13)
+#define NV_SOR_LVDS                                    (0x1c)
+#define NV_SOR_LVDS_ROTDAT_SHIFT                       (28)
+#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK                        (0x7 << 28)
+#define NV_SOR_LVDS_ROTDAT_RST                         (0 << 28)
+#define NV_SOR_LVDS_ROTCLK_SHIFT                       (24)
+#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK                        (0xf << 24)
+#define NV_SOR_LVDS_ROTCLK_RST                         (0 << 24)
+#define NV_SOR_LVDS_PLLDIV_SHIFT                       (21)
+#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK                        (0x1 << 21)
+#define NV_SOR_LVDS_PLLDIV_BY_7                                (0 << 21)
+#define NV_SOR_LVDS_BALANCED_SHIFT                     (19)
+#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK              (0x1 << 19)
+#define NV_SOR_LVDS_BALANCED_DISABLE                   (0 << 19)
+#define NV_SOR_LVDS_BALANCED_ENABLE                    (1 << 19)
+#define NV_SOR_LVDS_NEW_MODE_SHIFT                     (18)
+#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK              (0x1 << 18)
+#define NV_SOR_LVDS_NEW_MODE_DISABLE                   (0 << 18)
+#define NV_SOR_LVDS_NEW_MODE_ENABLE                    (1 << 18)
+#define NV_SOR_LVDS_DUP_SYNC_SHIFT                     (17)
+#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK              (0x1 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_DISABLE                   (0 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_ENABLE                    (1 << 17)
+#define NV_SOR_LVDS_LVDS_EN_SHIFT                      (16)
+#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK               (0x1 << 16)
+#define NV_SOR_LVDS_LVDS_EN_ENABLE                     (1 << 16)
+#define NV_SOR_LVDS_LINKACTB_SHIFT                     (15)
+#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK              (0x1 << 15)
+#define NV_SOR_LVDS_LINKACTB_DISABLE                   (0 << 15)
+#define NV_SOR_LVDS_LINKACTB_ENABLE                    (1 << 15)
+#define NV_SOR_LVDS_LINKACTA_SHIFT                     (14)
+#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK              (0x1 << 14)
+#define NV_SOR_LVDS_LINKACTA_ENABLE                    (1 << 14)
+#define NV_SOR_LVDS_MODE_SHIFT                         (12)
+#define NV_SOR_LVDS_MODE_DEFAULT_MASK                  (0x3 << 12)
+#define NV_SOR_LVDS_MODE_LVDS                          (0 << 12)
+#define NV_SOR_LVDS_UPPER_SHIFT                                (11)
+#define NV_SOR_LVDS_UPPER_DEFAULT_MASK                 (0x1 << 11)
+#define NV_SOR_LVDS_UPPER_FALSE                                (0 << 11)
+#define NV_SOR_LVDS_UPPER_TRUE                         (1 << 11)
+#define NV_SOR_LVDS_PD_TXCB_SHIFT                      (9)
+#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK               (0x1 << 9)
+#define NV_SOR_LVDS_PD_TXCB_ENABLE                     (0 << 9)
+#define NV_SOR_LVDS_PD_TXCB_DISABLE                    (1 << 9)
+#define NV_SOR_LVDS_PD_TXCA_SHIFT                      (8)
+#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK               (0x1 << 8)
+#define NV_SOR_LVDS_PD_TXCA_ENABLE                     (0 << 8)
+#define NV_SOR_LVDS_PD_TXDB_3_SHIFT                    (7)
+#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK             (0x1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_ENABLE                   (0 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_DISABLE                  (1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_2_SHIFT                    (6)
+#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK             (0x1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_ENABLE                   (0 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_DISABLE                  (1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_1_SHIFT                    (5)
+#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK             (0x1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_ENABLE                   (0 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_DISABLE                  (1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_0_SHIFT                    (4)
+#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK             (0x1 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_ENABLE                   (0 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_DISABLE                  (1 << 4)
+#define NV_SOR_LVDS_PD_TXDA_3_SHIFT                    (3)
+#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK             (0x1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_ENABLE                   (0 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_DISABLE                  (1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_2_SHIFT                    (2)
+#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK             (0x1 << 2)
+#define NV_SOR_LVDS_PD_TXDA_2_ENABLE                   (0 << 2)
+#define NV_SOR_LVDS_PD_TXDA_1_SHIFT                    (1)
+#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK             (0x1 << 1)
+#define NV_SOR_LVDS_PD_TXDA_1_ENABLE                   (0 << 1)
+#define NV_SOR_LVDS_PD_TXDA_0_SHIFT                    (0)
+#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK             (0x1)
+#define NV_SOR_LVDS_PD_TXDA_0_ENABLE                   (0)
+#define NV_SOR_SEQ_CTL                                 (0x20)
+#define NV_SOR_SEQ_CTL_SWITCH_SHIFT                    (30)
+#define NV_SOR_SEQ_CTL_SWITCH_MASK                     (0x1 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_WAIT                     (0 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_FORCE                    (1 << 30)
+#define NV_SOR_SEQ_CTL_STATUS_SHIFT                    (28)
+#define NV_SOR_SEQ_CTL_STATUS_MASK                     (0x1 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_STOPPED                  (0 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_RUNNING                  (1 << 28)
+#define NV_SOR_SEQ_CTL_PC_SHIFT                                (16)
+#define NV_SOR_SEQ_CTL_PC_MASK                         (0xf << 16)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT                 (12)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK                  (0xf << 12)
+#define NV_SOR_SEQ_CTL_PD_PC_SHIFT                     (8)
+#define NV_SOR_SEQ_CTL_PD_PC_MASK                      (0xf << 8)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT                 (4)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK                  (0xf << 4)
+#define NV_SOR_SEQ_CTL_PU_PC_SHIFT                     (0)
+#define NV_SOR_SEQ_CTL_PU_PC_MASK                      (0xf)
+#define NV_SOR_LANE_SEQ_CTL                            (0x21)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT          (31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK               (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING                (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER                (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT            (28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE             (0 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY             (1 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT             (20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP                        (0 << 20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN              (1 << 20)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT      (16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU         (0 << 16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD         (1 << 16)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT                        (12)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK         (0xf << 12)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT          (9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP                (0 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN      (1 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT          (8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP                (0 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN      (1 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT          (7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP                (0 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN      (1 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT          (6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP                (0 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN      (1 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT          (5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP                (0 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN      (1 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT          (4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP                (0 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN      (1 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT          (3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP                (0 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN      (1 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT          (2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP                (0 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN      (1 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT          (1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP                (0 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN      (1 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT          (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP                (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN      (1)
+#define NV_SOR_SEQ_INST(i)                             (0x22 + i)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT             (31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE           (0 << 31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE            (1 << 31)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT          (30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL         (0 << 30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN      (1 << 30)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT         (29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL                (0 << 29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST           (1 << 29)
+#define NV_SOR_SEQ_INST_BLANK_V_SHIFT                  (28)
+#define NV_SOR_SEQ_INST_BLANK_V_NORMAL                 (0 << 28)
+#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE               (1 << 28)
+#define NV_SOR_SEQ_INST_BLANK_H_SHIFT                  (27)
+#define NV_SOR_SEQ_INST_BLANK_H_NORMAL                 (0 << 27)
+#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE               (1 << 27)
+#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT                 (26)
+#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL                        (0 << 26)
+#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE              (1 << 26)
+#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT               (25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL              (0 << 25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK               (1 << 25)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT             (24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS       (0 << 24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE          (1 << 24)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT         (23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE         (0 << 23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE          (1 << 23)
+#define NV_SOR_SEQ_INST_PIN_B_SHIFT                    (22)
+#define NV_SOR_SEQ_INST_PIN_B_LOW                      (0 << 22)
+#define NV_SOR_SEQ_INST_PIN_B_HIGH                     (1 << 22)
+#define NV_SOR_SEQ_INST_PIN_A_SHIFT                    (21)
+#define NV_SOR_SEQ_INST_PIN_A_LOW                      (0 << 21)
+#define NV_SOR_SEQ_INST_PIN_A_HIGH                     (1 << 21)
+#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT                 (19)
+#define NV_SOR_SEQ_INST_SEQUENCE_UP                    (0 << 19)
+#define NV_SOR_SEQ_INST_SEQUENCE_DOWN                  (1 << 19)
+#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT                 (18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_STOP                  (0 << 18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_RUN                   (1 << 18)
+#define NV_SOR_SEQ_INST_PDPORT_SHIFT                   (17)
+#define NV_SOR_SEQ_INST_PDPORT_NO                      (0 << 17)
+#define NV_SOR_SEQ_INST_PDPORT_YES                     (1 << 17)
+#define NV_SOR_SEQ_INST_PDPLL_SHIFT                    (16)
+#define NV_SOR_SEQ_INST_PDPLL_NO                       (0 << 16)
+#define NV_SOR_SEQ_INST_PDPLL_YES                      (1 << 16)
+#define NV_SOR_SEQ_INST_HALT_SHIFT                     (15)
+#define NV_SOR_SEQ_INST_HALT_FALSE                     (0 << 15)
+#define NV_SOR_SEQ_INST_HALT_TRUE                      (1 << 15)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT               (12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK                (0x3 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_US                  (0 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_MS                  (1 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC               (2 << 12)
+#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT                        (0)
+#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK         (0x3ff)
+#define NV_SOR_PWM_DIV                                 (0x32)
+#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK             (0xffffff)
+#define NV_SOR_PWM_CTL                                 (0x33)
+#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT               (31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_DONE                        (0 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING             (1 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER             (1 << 31)
+#define NV_SOR_PWM_CTL_CLKSEL_SHIFT                    (30)
+#define NV_SOR_PWM_CTL_CLKSEL_PCLK                     (0 << 30)
+#define NV_SOR_PWM_CTL_CLKSEL_XTAL                     (1 << 30)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT                        (0)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK                 (0xffffff)
+#define NV_SOR_DP_LINKCTL(i)                           (0x4e + (i))
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT                (31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO           (0 << 31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES          (1 << 31)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT                (28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN    (0 << 28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE   (1 << 28)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SHIFT          (26)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_MASK           (0x3 << 26)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN      (0 << 26)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_D102           (1 << 26)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE     (2 << 26)
+#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7          (3 << 26)
+#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_SHIFT          (24)
+#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_MASK           (0x3 << 24)
+#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_NOPATTERN      (0 << 24)
+#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING1      (1 << 24)
+#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING2      (2 << 24)
+#define NV_SOR_DP_LINKCTL_CHANNELCODING_SHIFT          (22)
+#define NV_SOR_DP_LINKCTL_CHANNELCODING_DISABLE                (0 << 22)
+#define NV_SOR_DP_LINKCTL_CHANNELCODING_ENABLE         (1 << 22)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT              (16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK               (0x1f << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO               (0 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE                        (1 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO                        (3 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR               (15 << 16)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT          (14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                (0 << 14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE         (1 << 14)
+#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_SHIFT            (12)
+#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_MASK             (0x3 << 12)
+#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_DISABLE          (0 << 12)
+#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_GALIOS    (1 << 12)
+#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT               (10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE             (0 << 10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE              (1 << 10)
+#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT                 (2)
+#define NV_SOR_DP_LINKCTL_TUSIZE_MASK                  (0x7f << 2)
+#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT                 (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_NO                    (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_YES                   (1)
+#define NV_SOR_DC(i)                                   (0x50 + (i))
+#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT                 (24)
+#define NV_SOR_DC_LANE3_DP_LANE3_MASK                  (0xff << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0             (17 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0             (21 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0             (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0             (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1             (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1             (32 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1             (39 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2             (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2             (43 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3             (51 << 24)
+#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                 (16)
+#define NV_SOR_DC_LANE2_DP_LANE0_MASK                  (0xff << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0             (17 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0             (21 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0             (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0             (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1             (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1             (32 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1             (39 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2             (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2             (43 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3             (51 << 16)
+#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                 (8)
+#define NV_SOR_DC_LANE1_DP_LANE1_MASK                  (0xff << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0             (17 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0             (21 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0             (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0             (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1             (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1             (32 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1             (39 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2             (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2             (43 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3             (51 << 8)
+#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                 (0)
+#define NV_SOR_DC_LANE0_DP_LANE2_MASK                  (0xff)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0             (17)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0             (21)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0             (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0             (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1             (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1             (32)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1             (39)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2             (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2             (43)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3             (51)
+#define NV_SOR_LANE4_DRIVE_CURRENT(i)                  (0x52 + (i))
+#define NV_SOR_PR(i)                                   (0x54 + (i))
+#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                 (24)
+#define NV_SOR_PR_LANE3_DP_LANE3_MASK                  (0xff << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0             (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0             (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0             (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0             (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1             (4 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1             (6 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1             (17 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2             (8 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2             (13 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3             (17 << 24)
+#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT                 (16)
+#define NV_SOR_PR_LANE2_DP_LANE0_MASK                  (0xff << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0             (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0             (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0             (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0             (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1             (4 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1             (6 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1             (17 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2             (8 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2             (13 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3             (17 << 16)
+#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT                 (8)
+#define NV_SOR_PR_LANE1_DP_LANE1_MASK                  (0xff >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0             (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0             (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0             (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0             (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1             (4 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1             (6 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1             (17 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2             (8 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2             (13 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3             (17 >> 8)
+#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT                 (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_MASK                  (0xff)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0             (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0             (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0             (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0             (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1             (4)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1             (6)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1             (17)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2             (8)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2             (13)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3             (17)
+#define NV_SOR_LANE4_PREEMPHASIS(i)                    (0x57 + (i))
+#define NV_SOR_DP_CONFIG(i)                            (0x5a + (i))
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT            (31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE         (0 << 31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE         (1 << 31)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT      (28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE    (0 << 28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE     (1 << 28)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT          (26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE                (0 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE         (1 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT      (24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE   (0 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE   (1 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT          (16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK           (0xf << 16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT         (8)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK          (0x7f << 8)
+#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT               (0)
+#define NV_SOR_DP_CONFIG_WATERMARK_MASK                        (0x3f)
+#define NV_SOR_DP_PADCTL(i)                            (0x5e + (i))
+#define NV_SOR_DP_PADCTL_SPARE_SHIFT                   (25)
+#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK            (0x7f << 25)
+#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT                  (24)
+#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE                        (0 << 24)
+#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE                 (1 << 24)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT              (23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP            (0 << 23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN          (1 << 23)
+#define NV_SOR_DP_PADCTL_TX_PU_SHIFT                   (22)
+#define NV_SOR_DP_PADCTL_TX_PU_DISABLE                 (0 << 22)
+#define NV_SOR_DP_PADCTL_TX_PU_ENABLE                  (1 << 22)
+#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT                        (20)
+#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK         (0x3 << 20)
+#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT                 (16)
+#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK          (0xf << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE              (0 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX              (1 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN         (2 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN       (4 << 16)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT             (8)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK      (0xff << 8)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT   (7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE  (1 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT   (6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE  (1 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT   (5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE  (1 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT   (4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE  (1 << 4)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT                        (3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_YES                  (0 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_NO                   (1 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT                        (2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_YES                  (0 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_NO                   (1 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT                        (1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_YES                  (0 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_NO                   (1 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT                        (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_YES                  (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_NO                   (1)
+#define NV_SOR_DP_SPARE(i)                             (0x62 + (i))
+#define NV_SOR_DP_SPARE_REG_SHIFT                      (3)
+#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK               (0x1fffffff << 3)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT              (2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK        (0x1 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK         (0 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK        (1 << 2)
+#define NV_SOR_DP_SPARE_PANEL_SHIFT                    (1)
+#define NV_SOR_DP_SPARE_PANEL_EXTERNAL                 (0 << 1)
+#define NV_SOR_DP_SPARE_PANEL_INTERNAL                 (1 << 1)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT               (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO                  (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES                 (1)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS                 (0x65)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK            (0x1ffff)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT     (0)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS                 (0x66)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK            (0x1ffff)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT           (0)
+#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER             (0x67)
+#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i)         (0x68 + (i))
 
 #endif