m68k: use ColdFire MMU read/write bit flags when ioremapping
Greg Ungerer [Tue, 18 Oct 2011 06:16:43 +0000 (16:16 +1000)]
The ColdFire MMU has separate read and write bits, unlike the Motorola
m68k MMU which has a single read-only bit.

Define a _PAGE_READWRITE value for the Motorola MMU, which is 0, so we
can unconditionaly include that in the page table entry bits when setting
up ioremapped pages.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Acked-by: Matt Waddel <mwaddel@yahoo.com>
Acked-by: Kurt Mahan <kmahan@xmission.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>

arch/m68k/include/asm/motorola_pgtable.h
arch/m68k/mm/kmap.c

index 45bd3f5..e0fdd4d 100644 (file)
@@ -8,6 +8,7 @@
 #define _PAGE_PRESENT  0x001
 #define _PAGE_SHORT    0x002
 #define _PAGE_RONLY    0x004
+#define _PAGE_READWRITE        0x000
 #define _PAGE_ACCESSED 0x008
 #define _PAGE_DIRTY    0x010
 #define _PAGE_SUPER    0x080   /* 68040 supervisor only */
index 6934584..1cc2bed 100644 (file)
@@ -171,7 +171,8 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla
                        break;
                }
        } else {
-               physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+               physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED |
+                            _PAGE_DIRTY | _PAGE_READWRITE);
                switch (cacheflag) {
                case IOMAP_NOCACHE_SER:
                case IOMAP_NOCACHE_NONSER: