tegra: power: correct LP0 sequence
Jay Cheng [Tue, 16 Aug 2011 18:57:59 +0000 (14:57 -0400)]
Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7
Reviewed-on: http://git-master/r/47365
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e

arch/arm/mach-tegra/pm.c

index 8fda333..2ff62d3 100644 (file)
@@ -639,7 +639,7 @@ static void tegra_suspend_wake(void)
 
 static void tegra_pm_set(enum tegra_suspend_mode mode)
 {
-       u32 reg;
+       u32 reg, boot_flag;
        unsigned long rate = 32768;
 
        reg = readl(pmc + PMC_CTRL);
@@ -656,17 +656,19 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
                 */
                writel(0x0, pmc + PMC_SCRATCH39);
                __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
-               reg |= TEGRA_POWER_EFFECT_LP0;
+               wmb();
 
                /* Enable DPD sample to trigger sampling pads data and direction
                 * in which pad will be driven during lp0 mode*/
                writel(0x1, pmc + PMC_DPD_SAMPLE);
 
                /* Set warmboot flag */
-               reg = readl(pmc + PMC_SCRATCH0);
-               pmc_32kwritel(reg | 1, PMC_SCRATCH0);
+               boot_flag = readl(pmc + PMC_SCRATCH0);
+               pmc_32kwritel(boot_flag | 1, PMC_SCRATCH0);
 
                pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
+
+               reg |= TEGRA_POWER_EFFECT_LP0;
                break;
        case TEGRA_SUSPEND_LP1:
                break;