arm: tegra: p1761: enable OC1 throttling
Timo Alho [Fri, 10 Jan 2014 14:14:33 +0000 (16:14 +0200)]
This patch enables soc_therm OC1 throttling on p1761 platform
 - Configure soc_therm with 75% for CPU and "medium_throttling" for
   GPU
 - Configure KB_ROW15 as input with PULL-UP

Change-Id: I8c8f597b8b62c77099ea43cf14362a6a5197f622
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/354260
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Rogers <srogers@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Vandana Bansal <vandanab@nvidia.com>
Tested-by: Vandana Bansal <vandanab@nvidia.com>

arch/arm/boot/dts/tegra124-platforms/tegra124-p1761-pinmux.dtsi
arch/arm/mach-tegra/board-ardbeg-power.c

index 13b30a7..1605d10 100644 (file)
 
                        kb_row15_ps7 {
                                nvidia,pins = "kb_row15_ps7";
-                               nvidia,function = "safe";
-                               nvidia,enable-input = <TEGRA_PIN_OUTPUT>;
-                               nvidia,pull = <TEGRA_PIN_PUPD_PULL_DOWN>;
-                               nvidia,tristate = <TEGRA_PIN_TRISTATE>;
+                               nvidia,function = "soc";
+                               nvidia,enable-input = <TEGRA_PIN_INPUT>;
+                               nvidia,pull = <TEGRA_PIN_PUPD_PULL_UP>;
+                               nvidia,tristate = <TEGRA_PIN_NORMAL>;
                        };
 
                        kb_row16_pt0 {
index ff7d50a..859d8db 100644 (file)
@@ -1411,6 +1411,22 @@ struct soctherm_throttle battery_oc_throttle = {
        },
 };
 
+struct soctherm_throttle voltmon_throttle = {
+       .throt_mode = BRIEF,
+       .polarity = 1,
+       .priority = 50,
+       .devs = {
+               [THROTTLE_DEV_CPU] = {
+                       .enable = true,
+                       .depth = 75,
+               },
+               [THROTTLE_DEV_GPU] = {
+                       .enable = true,
+                       .throttling_depth = "medium_throttling",
+               },
+       },
+};
+
 int __init ardbeg_soctherm_init(void)
 {
        s32 base_cp, shft_cp;
@@ -1461,6 +1477,10 @@ int __init ardbeg_soctherm_init(void)
                memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
                       &battery_oc_throttle,
                       sizeof(battery_oc_throttle));
+               memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC1],
+                      &voltmon_throttle,
+                      sizeof(voltmon_throttle));
+
                break;
        default:
                break;