[ARM] tegra_i2s_audio: support mono capture
Chris Fries [Wed, 20 Oct 2010 18:10:29 +0000 (13:10 -0500)]
Support mono data formats such as DSP PCM Mode with 16 bit mono capture.

This patch also disables the in-driver downsampler.

Signed-off-by: Iliyan Malchev <malchev@google.com>

Rebase-Id: R1a6370af71568e6e2cf4e85058c6ebcc95947fb6

arch/arm/mach-tegra/include/mach/audio.h
arch/arm/mach-tegra/include/mach/i2s.h

index 1d631db..80f8b2c 100644 (file)
@@ -46,9 +46,8 @@ struct tegra_audio_platform_data {
        int bit_size;
        int i2s_bus_width; /* 32-bit for 16-bit packed I2S */
        int dsp_bus_width; /* 16-bit for DSP data format */
-
        int mask; /* enable tx and rx? */
-
+       bool stereo_capture; /* True if hardware supports stereo */
        void *driver_data;
 };
 
index ed8bc14..42cce88 100644 (file)
 
 #define I2S_I2S_PCM_CTRL_RCV_MODE                      (1<<0)
 
+/*
+ * I2S_I2S_NW_CTRL_0
+ */
+
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT1                   0
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT2                   1
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT3                   2
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT4                   3
+#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT            4
+
+#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_MASK             \
+               (3 << I2S_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT1               \
+               (I2S_TRM_TLPHY_SLOT_SEL_SLOT1           \
+               << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT2               \
+               (I2S_TRM_TLPHY_SLOT_SEL_SLOT2           \
+               << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT3               \
+               (I2S_TRM_TLPHY_SLOT_SEL_SLOT3           \
+               << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT4               \
+               (I2S_TRM_TLPHY_SLOT_SEL_SLOT4           \
+               << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+
+#define I2S_I2S_NW_CTRL_TRM_TLPHY_MODE                 (1<<3)
+
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT1                   0
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT2                   1
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT3                   2
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT4                   3
+#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT            1
+
+#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_MASK             \
+               (3 << I2S_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT1               \
+               (I2S_RCV_TLPHY_SLOT_SEL_SLOT1           \
+               << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT2               \
+               (I2S_RCV_TLPHY_SLOT_SEL_SLOT2           \
+               << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT3               \
+               (I2S_RCV_TLPHY_SLOT_SEL_SLOT3           \
+               << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT4               \
+               (I2S_RCV_TLPHY_SLOT_SEL_SLOT4           \
+               << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+
+#define I2S_I2S_NW_CTRL_RCV_TLPHY_MODE                 (1<<0)
 
 #endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */