clock: tegra21: Fix pex_uphy clock
Hoang Pham [Thu, 24 Jul 2014 08:32:29 +0000 (01:32 -0700)]
The pex_uphy clock should have only reset clock operation

Bug 1489337

Change-Id: I70d84eea3fbbd4a7654085f38cd422c3733fcf0e
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/441725
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

drivers/platform/tegra/tegra21_clocks.c

index 16800b0..0cb47fa 100644 (file)
@@ -7165,11 +7165,13 @@ static struct clk tegra_pciex_clk = {
        },
 };
 
+static struct clk_ops tegra_pex_uphy_ops = {
+       .reset    = tegra21_periph_clk_reset,
+};
+
 static struct clk tegra_pex_uphy_clk = {
        .name      = "pex_uphy",
-       .parent    = &tegra_pll_e,
-       .ops       = &tegra_pciex_clk_ops,
-       .max_rate  = 500000000,
+       .ops       = &tegra_pex_uphy_ops,
        .u.periph  = {
                .clk_num   = 205,
        },