ARM: tegra11: clock: Put PLLE under h/w control
Alex Frid [Tue, 23 Oct 2012 05:57:27 +0000 (22:57 -0700)]
Change-Id: Ifa0621f2d3bb7c0f8f52a0f9947990b789e1241b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/188900
(cherry picked from commit e0ba7cf05c8bd41dc65be7a59d9996a0ec96a2c1)
Reviewed-on: http://git-master/r/190213
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/tegra11_clocks.c

index 2cca50f..4257b39 100644 (file)
@@ -48,7 +48,7 @@ struct clk;
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 #define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */
 #else
-#define USE_PLLE_SWCTL 1       /* Use s/w controls for PLLE */
+#define USE_PLLE_SWCTL 0       /* Use s/w controls for PLLE */
 #define PLL_POST_LOCK_DELAY 10 /* Safety delay after lock is detected */
 #endif
 #endif
index 84b0852..954d82e 100644 (file)
 #define PLLE_AUX_PLLRE_SEL             (1<<28)
 #define PLLE_AUX_SEQ_STATE_SHIFT       26
 #define PLLE_AUX_SEQ_STATE_MASK                (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
+#define PLLE_AUX_SEQ_START_STATE       (1<<25)
 #define PLLE_AUX_SEQ_ENABLE            (1<<24)
+#define PLLE_AUX_SS_SWCTL              (1<<6)
 #define PLLE_AUX_ENABLE_SWCTL          (1<<4)
 #define PLLE_AUX_USE_LOCKDET           (1<<3)
 #define PLLE_AUX_PLLP_SEL              (1<<2)
 
 /* USB PLLs PD HW controls */
 #define XUSBIO_PLL_CFG0                                0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE                (1<<25)
 #define XUSBIO_PLL_CFG0_SEQ_ENABLE             (1<<24)
 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET     (1<<6)
 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL       (1<<2)
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL       (1<<0)
 
 #define PLLU_HW_PWRDN_CFG0                     0x530
+#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE     (1<<25)
 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE          (1<<24)
 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET         (1<<6)
 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL    (1<<2)
@@ -1746,7 +1750,7 @@ static int tegra11_pll_clk_wait_for_lock(
 static void usb_plls_hw_control_enable(u32 reg)
 {
        u32 val = clk_readl(reg);
-       val |= USB_PLLS_USE_LOCKDET;
+       val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
        val &= ~USB_PLLS_ENABLE_SWCTL;
        val |= USB_PLLS_SEQ_START_STATE;
        pll_writel_delay(val, reg);
@@ -3237,11 +3241,6 @@ static int tegra11_plle_clk_enable(struct clk *c)
        val &= ~PLLE_BASE_LOCK_OVERRIDE;
        clk_writel(val, c->reg + PLL_BASE);
 
-       val = clk_readl(PLLE_AUX);
-       val |= PLLE_AUX_ENABLE_SWCTL;
-       val &= ~PLLE_AUX_SEQ_ENABLE;
-       pll_writel_delay(val, PLLE_AUX);
-
        val = clk_readl(c->reg + PLL_MISC(c));
        val |= PLLE_MISC_LOCK_ENABLE;
        val |= PLLE_MISC_IDDQ_SW_CTRL;
@@ -3281,8 +3280,8 @@ static int tegra11_plle_clk_enable(struct clk *c)
        clk_writel(val, c->reg + PLL_MISC(c));
 
        val = clk_readl(PLLE_AUX);
-       val |= PLLE_AUX_USE_LOCKDET;
-       val &= ~PLLE_AUX_ENABLE_SWCTL;
+       val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
+       val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
        pll_writel_delay(val, PLLE_AUX);
        val |= PLLE_AUX_SEQ_ENABLE;
        pll_writel_delay(val, PLLE_AUX);