ARM: tegra12: clock: Add PERIPH_ON_APB to SATA
Kaz Fukuoka [Wed, 11 Sep 2013 17:41:50 +0000 (10:41 -0700)]
Ported from Tegar30 Change-Id: I12be16dbc2614224ba852216a645d0f84c795334

bug 1363948

Change-Id: If9e59db37969431f5c1f0a51da4c8fe82a22eb9c
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/273269
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra12_clocks.c

index 1506350..15fcb3f 100644 (file)
@@ -7645,9 +7645,9 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("sbc4",      "spi-tegra114.3",       NULL,   68,     0x1b4, 48000000, mux_pllp_pllc_pllm_clkm,       MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc5",      "spi-tegra114.4",       NULL,   104,    0x3c8, 48000000, mux_pllp_pllc_pllm_clkm,       MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc6",      "spi-tegra114.5",       NULL,   105,    0x3cc, 48000000, mux_pllp_pllc_pllm_clkm,       MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
+       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  200000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),