ARM: tegra: ardbeg/loki: Set sdmmc autocal offsets
Pavan Kunapuli [Mon, 16 Sep 2013 15:25:12 +0000 (20:25 +0530)]
Passing 1.8V and 3.3V auto calibration offsets and the UHS modes
in which 1.8V calibration offsets need to be set.

Bug 1347531

Change-Id: Id6762301d474e2c2e6f70d2e8e837bf2b9831a0e
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/275198
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
(cherry picked from commit 2f0a934c2851b4faabc542dff3a069a3c84730c1)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-sdhci.c
arch/arm/mach-tegra/board-loki-sdhci.c

index d886263..d41aefa 100644 (file)
@@ -150,6 +150,9 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
 /*FIXME: Enable UHS modes for WiFI */
        .uhs_mask = MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
+       .calib_3v3_offsets = 0x7676,
+       .calib_1v8_offsets = 0x7676,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -162,7 +165,9 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .uhs_mask = MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
                 MMC_UHS_MASK_SDR104 |
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
-/*     .max_clk = 12000000, */
+       .calib_3v3_offsets = 0x7676,
+       .calib_1v8_offsets = 0x7676,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
@@ -180,7 +185,10 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .uhs_mask = MMC_MASK_HS200,
        .ddr_clk_limit = 51000000,
        .max_clk_limit = 102000000,
-/*     .max_clk = 12000000, */
+       .calib_3v3_offsets = 0x0202,
+       .calib_1v8_offsets = 0x0202,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50 |
+               MMC_1V8_CALIB_OFFSET_HS200,
 };
 
 static struct platform_device tegra_sdhci_device0 = {
index 2ca4359..7de81a8 100644 (file)
@@ -150,6 +150,9 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                /* FIXME: Enable UHS mode */
                MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
+       .calib_3v3_offsets = 0x7676,
+       .calib_1v8_offsets = 0x7676,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -162,7 +165,9 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
                /* FIXME: Enable UHS mode */
                MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
-/*     .max_clk = 12000000, */
+       .calib_3v3_offsets = 0x7676,
+       .calib_1v8_offsets = 0x7676,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
@@ -180,7 +185,11 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .uhs_mask = MMC_MASK_HS200,
        .ddr_clk_limit = 51000000,
        .max_clk_limit = 102000000,
-/*     .max_clk = 12000000, */
+       .calib_3v3_offsets = 0x0202,
+       .calib_1v8_offsets = 0x0202,
+       .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50 |
+               MMC_1V8_CALIB_OFFSET_HS200,
+
 };
 
 static struct platform_device tegra_sdhci_device0 = {