ARM: tegra: bonaire: add board files
Jin Qian [Fri, 3 Feb 2012 02:25:15 +0000 (18:25 -0800)]
and the include for host1x init (invoked from board file)

Change-Id: I5a7cb2e074f6c7395aec5ede1db31b2bdeae5cb0
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/82938
Signed-off-by: Mark Stadler <mastadler@nvidia.com>

16 files changed:
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-bonaire-panel.c [new file with mode: 0644]
arch/arm/mach-tegra/board-bonaire-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-bonaire-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-bonaire.c [new file with mode: 0644]
arch/arm/mach-tegra/board-bonaire.h [new file with mode: 0644]
arch/arm/mach-tegra/board.h
arch/arm/mach-tegra/tegra12_host1x_devices.h [new file with mode: 0644]
drivers/video/tegra/nvmap/nvmap.c
drivers/video/tegra/nvmap/nvmap_dev.c
drivers/video/tegra/nvmap/nvmap_handle.c
drivers/video/tegra/nvmap/nvmap_heap.c
drivers/video/tegra/nvmap/nvmap_ioctl.c
drivers/video/tegra/nvmap/nvmap_ioctl.h
drivers/video/tegra/nvmap/nvmap_priv.h
include/linux/nvmap.h

index 5924e2e..5384f06 100644 (file)
@@ -183,6 +183,11 @@ endif
 
 obj-$(CONFIG_TEGRA_USE_SECURE_KERNEL)   += tegra_tzram.o
 
+obj-${CONFIG_MACH_BONAIRE}              += board-bonaire.o
+obj-${CONFIG_MACH_BONAIRE}              += board-bonaire-panel.o
+obj-${CONFIG_MACH_BONAIRE}              += board-bonaire-pinmux.o
+obj-${CONFIG_MACH_BONAIRE}              += board-bonaire-power.o
+
 obj-${CONFIG_MACH_CURACAO}              += board-curacao.o
 obj-${CONFIG_MACH_CURACAO}              += board-curacao-panel.o
 obj-${CONFIG_MACH_CURACAO}              += board-curacao-pinmux.o
diff --git a/arch/arm/mach-tegra/board-bonaire-panel.c b/arch/arm/mach-tegra/board-bonaire-panel.c
new file mode 100644 (file)
index 0000000..b754559
--- /dev/null
@@ -0,0 +1,689 @@
+/*
+ * arch/arm/mach-tegra/board-bonaire-panel.c
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/nvhost.h>
+#include <linux/nvmap.h>
+#include <mach/gpio-tegra.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+
+#include "board.h"
+#include "board-bonaire.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "tegra12_host1x_devices.h"
+
+/* Select panel to be used. */
+#define DSI_PANEL_219 0
+#define DSI_PANEL_218 1
+#define AVDD_LCD PMU_TCA6416_GPIO_PORT17
+#define DSI_PANEL_RESET 0
+
+#define bonaire_lvds_shutdown  TEGRA_GPIO_PB2
+#define bonaire_bl_enb         TEGRA_GPIO_PW1
+#define bonaire_bl_pwm         TEGRA_GPIO_PH0
+
+#if defined(DSI_PANEL_219) || defined(DSI_PANEL_218)
+#define bonaire_dsia_bl_enb    TEGRA_GPIO_PW1
+#define bonaire_dsib_bl_enb    TEGRA_GPIO_PW0
+#define bonaire_dsi_panel_reset        TEGRA_GPIO_PD2
+#endif
+
+static struct regulator *bonaire_dsi_reg;
+
+static atomic_t sd_brightness = ATOMIC_INIT(255);
+
+static int bonaire_backlight_init(struct device *dev)
+{
+       int ret;
+
+#ifndef CONFIG_TEGRA_BONAIRE_DSI
+       tegra_gpio_disable(bonaire_bl_pwm);
+
+       ret = gpio_request(bonaire_bl_enb, "backlight_enb");
+       if (ret < 0)
+               return ret;
+
+       ret = gpio_direction_output(bonaire_bl_enb, 1);
+       if (ret < 0)
+               gpio_free(bonaire_bl_enb);
+       else
+               tegra_gpio_enable(bonaire_bl_enb);
+
+       return ret;
+#endif
+
+#if DSI_PANEL_219 || DSI_PANEL_218
+       /* Enable back light for DSIa panel */
+       printk("bonaire_dsi_backlight_init\n");
+       ret = gpio_request(bonaire_dsia_bl_enb, "dsia_bl_enable");
+       if (ret < 0)
+               return ret;
+
+       ret = gpio_direction_output(bonaire_dsia_bl_enb, 1);
+       if (ret < 0)
+               gpio_free(bonaire_dsia_bl_enb);
+       else
+               tegra_gpio_enable(bonaire_dsia_bl_enb);
+
+       /* Enable back light for DSIb panel */
+       ret = gpio_request(bonaire_dsib_bl_enb, "dsib_bl_enable");
+       if (ret < 0)
+               return ret;
+
+       ret = gpio_direction_output(bonaire_dsib_bl_enb, 1);
+       if (ret < 0)
+               gpio_free(bonaire_dsib_bl_enb);
+       else
+               tegra_gpio_enable(bonaire_dsib_bl_enb);
+#endif
+
+       return ret;
+};
+
+static void bonaire_backlight_exit(struct device *dev)
+{
+#ifndef CONFIG_TEGRA_BONAIRE_DSI
+       gpio_set_value(bonaire_bl_enb, 0);
+       gpio_free(bonaire_bl_enb);
+       tegra_gpio_disable(bonaire_bl_enb);
+       return;
+#endif
+#if DSI_PANEL_219 || DSI_PANEL_218
+       /* Disable back light for DSIa panel */
+       gpio_set_value(bonaire_dsia_bl_enb, 0);
+       gpio_free(bonaire_dsia_bl_enb);
+       tegra_gpio_disable(bonaire_dsia_bl_enb);
+
+       /* Disable back light for DSIb panel */
+       gpio_set_value(bonaire_dsib_bl_enb, 0);
+       gpio_free(bonaire_dsib_bl_enb);
+       tegra_gpio_disable(bonaire_dsib_bl_enb);
+
+       gpio_set_value(bonaire_lvds_shutdown, 1);
+       mdelay(20);
+#endif
+}
+
+static int bonaire_backlight_notify(struct device *unused, int brightness)
+{
+       int cur_sd_brightness = atomic_read(&sd_brightness);
+       int orig_brightness = brightness;
+
+#ifndef CONFIG_TEGRA_BONAIRE_DSI
+       /* Set the backlight GPIO pin mode to 'backlight_enable' */
+       gpio_request(bonaire_bl_enb, "backlight_enb");
+       gpio_set_value(bonaire_bl_enb, !!brightness);
+       goto final;
+#endif
+#if DSI_PANEL_219 || DSI_PANEL_218
+       /* DSIa */
+       gpio_set_value(bonaire_dsia_bl_enb, !!brightness);
+
+       /* DSIb */
+       gpio_set_value(bonaire_dsib_bl_enb, !!brightness);
+#endif
+
+final:
+       /* SD brightness is a percentage, 8-bit value. */
+       brightness = (brightness * cur_sd_brightness) / 255;
+       if (cur_sd_brightness != 255) {
+               printk("NVSD BL - in: %d, sd: %d, out: %d\n",
+                       orig_brightness, cur_sd_brightness, brightness);
+       }
+
+       return brightness;
+}
+
+static struct platform_pwm_backlight_data bonaire_backlight_data = {
+       .pwm_id         = 2,
+       .max_brightness = 255,
+       .dft_brightness = 224,
+       .pwm_period_ns  = 5000000,
+       .init           = bonaire_backlight_init,
+       .exit           = bonaire_backlight_exit,
+       .notify         = bonaire_backlight_notify,
+};
+
+static struct platform_device bonaire_backlight_device = {
+       .name   = "pwm-backlight",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &bonaire_backlight_data,
+       },
+};
+
+static int bonaire_panel_enable(void)
+{
+       static struct regulator *reg;
+
+       if (reg == NULL) {
+               reg = regulator_get(NULL, "avdd_lvds");
+               if (WARN_ON(IS_ERR(reg)))
+                       pr_err("%s: couldn't get regulator avdd_lvds: %ld\n",
+                              __func__, PTR_ERR(reg));
+               else
+                       regulator_enable(reg);
+       }
+
+       gpio_set_value(bonaire_lvds_shutdown, 1);
+       return 0;
+}
+
+static int bonaire_panel_disable(void)
+{
+       gpio_set_value(bonaire_lvds_shutdown, 0);
+       return 0;
+}
+
+static struct resource bonaire_disp1_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_GENERAL,
+               .end    = INT_DISPLAY_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY_BASE,
+               .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0,    /* Filled in by bonaire_panel_init() */
+               .end    = 0,    /* Filled in by bonaire_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+#ifdef CONFIG_TEGRA_DSI_INSTANCE_1
+       {
+               .name   = "dsi_regs",
+               .start  = TEGRA_DSIB_BASE,
+               .end    = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+#else
+       {
+               .name   = "dsi_regs",
+               .start  = TEGRA_DSI_BASE,
+               .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+#endif
+#if defined(CONFIG_TEGRA_DP)
+       {
+               .name   = "sor",
+               .start  = TEGRA_SOR_BASE,
+               .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "dpaux",
+               .start  = TEGRA_DPAUX_BASE,
+               .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+#endif
+};
+
+static struct tegra_dc_mode bonaire_panel_modes[] = {
+       {
+               .pclk = 18000000,
+               .h_ref_to_sync = 8,
+               .v_ref_to_sync = 2,
+               .h_sync_width = 4,
+               .v_sync_width = 1,
+               .h_back_porch = 20,
+               .v_back_porch = 7,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+               .h_active = 240,
+               .v_active = 320,
+#else
+               .h_active = 480,
+               .v_active = 640,
+#endif
+               .h_front_porch = 8,
+               .v_front_porch = 8,
+       },
+};
+
+static struct tegra_fb_data bonaire_fb_data = {
+       .win            = 0,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+       .xres           = 240,
+       .yres           = 320,
+       .bits_per_pixel = 16,
+       .flags          = 0,
+#else
+       .xres           = 480,
+       .yres           = 640,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+#endif
+};
+
+static int bonaire_dsi_panel_enable(void)
+{
+       int ret;
+
+       if (bonaire_dsi_reg == NULL) {
+               bonaire_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
+               if (IS_ERR_OR_NULL(bonaire_dsi_reg)) {
+               pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
+                       bonaire_dsi_reg = NULL;
+                       return PTR_ERR(bonaire_dsi_reg);
+               }
+       }
+       regulator_enable(bonaire_dsi_reg);
+
+       ret = gpio_request(TEGRA_GPIO_PJ1, "DSI TE");
+       if (ret < 0)
+               return ret;
+
+       ret = gpio_direction_input(TEGRA_GPIO_PJ1);
+       if (ret < 0) {
+               gpio_free(TEGRA_GPIO_PJ1);
+               return ret;
+       }
+       tegra_gpio_enable(TEGRA_GPIO_PJ1);
+
+#if DSI_PANEL_219
+
+       ret = gpio_request(TEGRA_GPIO_PH0, "ph0");
+       if (ret < 0)
+               return ret;
+       ret = gpio_direction_output(TEGRA_GPIO_PH0, 0);
+       if (ret < 0) {
+               gpio_free(TEGRA_GPIO_PH0);
+               return ret;
+       } else
+               tegra_gpio_enable(TEGRA_GPIO_PH0);
+
+       ret = gpio_request(TEGRA_GPIO_PH2, "ph2");
+       if (ret < 0)
+               return ret;
+       ret = gpio_direction_output(TEGRA_GPIO_PH2, 0);
+       if (ret < 0) {
+               gpio_free(TEGRA_GPIO_PH2);
+               return ret;
+       } else
+               tegra_gpio_enable(TEGRA_GPIO_PH2);
+
+       ret = gpio_request(TEGRA_GPIO_PU2, "pu2");
+       if (ret < 0)
+               return ret;
+       ret = gpio_direction_output(TEGRA_GPIO_PU2, 0);
+       if (ret < 0) {
+               gpio_free(TEGRA_GPIO_PU2);
+               return ret;
+       } else
+               tegra_gpio_enable(TEGRA_GPIO_PU2);
+
+       gpio_set_value(bonaire_lvds_shutdown, 1);
+       mdelay(20);
+       gpio_set_value(TEGRA_GPIO_PH0, 1);
+       mdelay(10);
+       gpio_set_value(TEGRA_GPIO_PH2, 1);
+       mdelay(15);
+       gpio_set_value(TEGRA_GPIO_PU2, 0);
+       gpio_set_value(TEGRA_GPIO_PU2, 1);
+       mdelay(10);
+       gpio_set_value(TEGRA_GPIO_PU2, 0);
+       mdelay(10);
+       gpio_set_value(TEGRA_GPIO_PU2, 1);
+       mdelay(15);
+#endif
+
+#if DSI_PANEL_218
+       printk("DSI_PANEL_218 is enabled\n");
+       ret = gpio_request(AVDD_LCD, "avdd_lcd");
+       if (ret < 0)
+               gpio_free(AVDD_LCD);
+       ret = gpio_direction_output(AVDD_LCD, 1);
+       if (ret < 0)
+               gpio_free(AVDD_LCD);
+       else
+               tegra_gpio_enable(AVDD_LCD);
+
+#if DSI_PANEL_RESET
+       ret = gpio_request(TEGRA_GPIO_PD2, "pd2");
+       if (ret < 0) {
+               return ret;
+       }
+       ret = gpio_direction_output(TEGRA_GPIO_PD2, 0);
+       if (ret < 0) {
+               gpio_free(TEGRA_GPIO_PD2);
+               return ret;
+       } else
+               tegra_gpio_enable(TEGRA_GPIO_PD2);
+
+       gpio_set_value(TEGRA_GPIO_PD2, 1);
+       gpio_set_value(TEGRA_GPIO_PD2, 0);
+       mdelay(2);
+       gpio_set_value(TEGRA_GPIO_PD2, 1);
+       mdelay(2);
+#endif
+#endif
+
+       return 0;
+}
+
+static int bonaire_dsi_panel_disable(void)
+{
+       int err;
+
+       err = 0;
+       printk(KERN_INFO "DSI panel disable\n");
+
+#if DSI_PANEL_219
+       tegra_gpio_disable(TEGRA_GPIO_PU2);
+       gpio_free(TEGRA_GPIO_PU2);
+       tegra_gpio_disable(TEGRA_GPIO_PH2);
+       gpio_free(TEGRA_GPIO_PH2);
+       tegra_gpio_disable(TEGRA_GPIO_PH0);
+       gpio_free(TEGRA_GPIO_PH0);
+       tegra_gpio_disable(TEGRA_GPIO_PL2);
+       gpio_free(TEGRA_GPIO_PL2);
+#endif
+
+#if DSI_PANEL_218
+       tegra_gpio_disable(TEGRA_GPIO_PD2);
+       gpio_free(TEGRA_GPIO_PD2);
+#endif
+
+       return err;
+}
+
+static int bonaire_dsi_panel_postsuspend(void)
+{
+       int err;
+
+       err = 0;
+       printk(KERN_INFO "DSI panel postsuspend\n");
+
+       if (bonaire_dsi_reg) {
+               err = regulator_disable(bonaire_dsi_reg);
+               if (err < 0)
+                       printk(KERN_ERR
+                       "DSI regulator avdd_dsi_csi disable failed\n");
+               regulator_put(bonaire_dsi_reg);
+               bonaire_dsi_reg = NULL;
+       }
+
+#if DSI_PANEL_218
+       tegra_gpio_disable(AVDD_LCD);
+       gpio_free(AVDD_LCD);
+#endif
+
+       return err;
+}
+
+static struct tegra_dsi_cmd dsi_init_cmd[] = {
+       DSI_CMD_SHORT(0x05, 0x11, 0x00),
+       DSI_DLY_MS(150),
+       DSI_CMD_SHORT(0x05, 0x29, 0x00),
+       DSI_DLY_MS(20),
+};
+
+static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
+       DSI_CMD_SHORT(0x05, 0x28, 0x00),
+       DSI_DLY_MS(20),
+       DSI_CMD_SHORT(0x05, 0x10, 0x00),
+       DSI_DLY_MS(5),
+};
+
+struct tegra_dsi_out bonaire_dsi = {
+       .n_data_lanes = 2,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+       .pixel_format = TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
+#else
+       .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
+#endif
+       .refresh_rate = 60,
+       .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
+
+       .panel_has_frame_buffer = true,
+#ifdef CONFIG_TEGRA_DSI_INSTANCE_1
+       .dsi_instance = 1,
+#else
+       .dsi_instance = 0,
+#endif
+       .panel_reset = DSI_PANEL_RESET,
+
+       .n_init_cmd = ARRAY_SIZE(dsi_init_cmd),
+       .dsi_init_cmd = dsi_init_cmd,
+
+       .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
+       .dsi_suspend_cmd = dsi_suspend_cmd,
+
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+       .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
+#else
+       .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
+#endif
+       .lp_cmd_mode_freq_khz = 430000,
+};
+
+static struct tegra_dc_mode bonaire_dsi_modes[] = {
+#if DSI_PANEL_219
+       {
+               .pclk = 10000000,
+               .h_ref_to_sync = 4,
+               .v_ref_to_sync = 1,
+               .h_sync_width = 16,
+               .v_sync_width = 1,
+               .h_back_porch = 32,
+               .v_back_porch = 1,
+               .h_active = 540,
+               .v_active = 960,
+               .h_front_porch = 32,
+               .v_front_porch = 2,
+       },
+#endif
+
+#if DSI_PANEL_218
+       {
+               .pclk = 323000000,
+               .h_ref_to_sync = 11,
+               .v_ref_to_sync = 1,
+               .h_sync_width = 16,
+               .v_sync_width = 4,
+               .h_back_porch = 16,
+               .v_back_porch = 4,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+               .h_active = 320,
+               .v_active = 240,
+#else
+               .h_active = 864,
+               .v_active = 480,
+#endif
+               .h_front_porch = 16,
+               .v_front_porch = 4,
+       },
+#endif
+
+};
+
+static struct tegra_fb_data bonaire_dsi_fb_data = {
+#if DSI_PANEL_219
+       .win            = 0,
+       .xres           = 540,
+       .yres           = 960,
+       .bits_per_pixel = 32,
+#endif
+
+#if DSI_PANEL_218
+       .win            = 0,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+       .xres           = 320,
+       .yres           = 240,
+       .bits_per_pixel = 16,
+#else
+       .xres           = 864,
+       .yres           = 480,
+       .bits_per_pixel = 32,
+#endif
+#endif
+};
+
+static struct tegra_dc_out bonaire_disp1_out = {
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+#if defined (TEGRA_DC_TEMPORAL_DITHER) /* mds hack */
+       .dither         = TEGRA_DC_TEMPORAL_DITHER,
+#endif
+
+#if defined(CONFIG_TEGRA_DP)
+       .type           = TEGRA_DC_OUT_DP,
+
+       .modes          = bonaire_panel_modes,
+       .n_modes        = ARRAY_SIZE(bonaire_panel_modes),
+
+       .enable         = bonaire_panel_enable,
+       .disable        = bonaire_panel_disable,
+#elif defined(CONFIG_TEGRA_BONAIRE_DSI)
+       .type           = TEGRA_DC_OUT_DSI,
+
+       .modes          = bonaire_dsi_modes,
+       .n_modes        = ARRAY_SIZE(bonaire_dsi_modes),
+
+       .dsi            = &bonaire_dsi,
+
+       .enable         = bonaire_dsi_panel_enable,
+       .disable        = bonaire_dsi_panel_disable,
+       .postsuspend    = bonaire_dsi_panel_postsuspend,
+#else
+       .type           = TEGRA_DC_OUT_RGB,
+
+       .modes          = bonaire_panel_modes,
+       .n_modes        = ARRAY_SIZE(bonaire_panel_modes),
+
+       .enable         = bonaire_panel_enable,
+       .disable        = bonaire_panel_disable,
+#endif
+};
+
+static struct tegra_dc_platform_data bonaire_disp1_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &bonaire_disp1_out,
+       .emc_clk_rate   = 300000000,
+#ifndef CONFIG_TEGRA_BONAIRE_DSI
+       .fb             = &bonaire_fb_data,
+#else
+       .fb             = &bonaire_dsi_fb_data,
+#endif
+};
+
+static struct nvhost_device bonaire_disp1_device = {
+       .name           = "tegradc",
+       .id             = 0,
+       .resource       = bonaire_disp1_resources,
+       .num_resources  = ARRAY_SIZE(bonaire_disp1_resources),
+       .dev = {
+               .platform_data = &bonaire_disp1_pdata,
+       },
+};
+
+static struct nvmap_platform_carveout bonaire_carveouts[] = {
+       [0] = {
+               .name           = "iram",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
+               .base           = TEGRA_IRAM_BASE,
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+               .size           = 0, /* DMA won't work in ASIM IRAM */
+#else
+               .size           = TEGRA_IRAM_SIZE,
+#endif
+               .buddy_size     = 0, /* no buddy allocation for IRAM */
+       },
+       [1] = {
+               .name           = "generic-0",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
+               .base           = 0,    /* Filled in by bonaire_panel_init() */
+               .size           = 0,    /* Filled in by bonaire_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+       [2] = {
+               .name           = "vpr",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
+               .base           = 0,    /* Filled in by bonaire_panel_init() */
+               .size           = 0,    /* Filled in by bonaire_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+};
+
+static struct nvmap_platform_data bonaire_nvmap_data = {
+       .carveouts      = bonaire_carveouts,
+       .nr_carveouts   = ARRAY_SIZE(bonaire_carveouts),
+};
+
+static struct platform_device bonaire_nvmap_device = {
+       .name   = "tegra-nvmap",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &bonaire_nvmap_data,
+       },
+};
+
+static struct platform_device *bonaire_gfx_devices[] __initdata = {
+       &bonaire_nvmap_device,
+       &tegra_pwfm2_device,
+       &bonaire_backlight_device,
+};
+
+int __init bonaire_panel_init(void)
+{
+       int err;
+       struct resource *res;
+
+       bonaire_carveouts[1].base = tegra_carveout_start;
+       bonaire_carveouts[1].size = tegra_carveout_size;
+       bonaire_carveouts[2].base = tegra_vpr_start;
+       bonaire_carveouts[2].size = tegra_vpr_size;
+
+       err = platform_add_devices(bonaire_gfx_devices,
+                                  ARRAY_SIZE(bonaire_gfx_devices));
+
+#ifdef CONFIG_TEGRA_GRHOST
+       err = tegra12_register_host1x_devices();
+       if (err)
+               return err;
+#endif
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+       res = nvhost_get_resource_byname(&bonaire_disp1_device,
+                                        IORESOURCE_MEM, "fbmem");
+       res->start = tegra_fb_start;
+       res->end = tegra_fb_start + tegra_fb_size - 1;
+
+       if (!err)
+               err = nvhost_device_register(&bonaire_disp1_device);
+#endif
+       return err;
+}
diff --git a/arch/arm/mach-tegra/board-bonaire-pinmux.c b/arch/arm/mach-tegra/board-bonaire-pinmux.c
new file mode 100644 (file)
index 0000000..20e3922
--- /dev/null
@@ -0,0 +1,232 @@
+/*
+ * arch/arm/mach-tegra/board-bonaire-pinmux.c
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/bug.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-t12.h>
+
+#define DEFAULT_DRIVE(_name)                                   \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_DISABLE,                       \
+               .schmitt = TEGRA_SCHMITT_ENABLE,                \
+               .drive = TEGRA_DRIVE_DIV_1,                     \
+               .pull_down = TEGRA_PULL_31,                     \
+               .pull_up = TEGRA_PULL_31,                       \
+               .slew_rising = TEGRA_SLEW_SLOWEST,              \
+               .slew_falling = TEGRA_SLEW_SLOWEST,             \
+       }
+
+
+/* !!!FIXME!!!! POPULATE THIS TABLE */
+static __initdata struct tegra_drive_pingroup_config bonaire_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+       }
+
+/* !!!FIXME!!!! POPULATE THIS TABLE */
+static __initdata struct tegra_pingroup_config bonaire_pinmux[] = {
+       DEFAULT_PINMUX(ULPI_DATA0,      UARTA,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,      UARTA,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_CLK,        UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,        UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,        UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_STP,        UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CLK,      CLK12,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,      SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,     SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,     PWM0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,     PWM1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,     RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK2_OUT,        EXTPERIPH2,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DDC_SCL,         I2C4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DDC_SDA,         I2C4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_RXD,       IRDA,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_TXD,       IRDA,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,     UARTB,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_CTS_N,     UARTB,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_TXD,       UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,       UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_CTS_N,     UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,     UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU0,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU1,        RSVD2,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU2,        RSVD2,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU3,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        USB,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN1_I2C_SDA,    I2C1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN1_I2C_SCL,    I2C1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_FS,         I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DIN,        I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK3_OUT,        EXTPERIPH3,      NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK3_REQ,        DEV3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_WAIT,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CLK,         NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS1_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,       NAND_ALT,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       NAND_ALT,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD0,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD1,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD2,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD3,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD4,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD5,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD6,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD7,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD8,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD9,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD10,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD11,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD12,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD14,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD15,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A16,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A18,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A19,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_WR_N,        NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_OE_N,        NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_DQS_P,       NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_RST_N,       GMI,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN2_I2C_SCL,    I2C2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN2_I2C_SDA,    I2C2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CLK,      SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,      SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_RST_N,    RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_MCLK,        VI,              NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_I2C_SCL,     I2C3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_I2C_SDA,     I2C3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB3,       VGP3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB4,       VGP4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       VGP5,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       VGP6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(JTAG_RTCK,       RTCK,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PWR_I2C_SCL,     I2CPWR,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PWR_I2C_SDA,     I2CPWR,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW0,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW1,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW2,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW3,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW5,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW7,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW9,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW10,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL0,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL1,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL2,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL3,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL4,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,          NORMAL,    NORMAL,     OUTPUT),
+#ifdef CONFIG_SND_HDA_TEGRA
+       DEFAULT_PINMUX(DAP1_FS,         HDA,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DIN,        HDA,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,       HDA,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,       HDA,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_REQ,        DAP1,            NORMAL,    NORMAL,     INPUT),
+#else
+       DEFAULT_PINMUX(DAP1_FS,         I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DIN,        I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+#endif
+       DEFAULT_PINMUX(CLK1_OUT,        EXTPERIPH1,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_IN,        SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(DAP2_FS,         I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DIN,        I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MOSI,       SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MISO,       SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_CS0_N,      SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_SCK,        SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MOSI,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_SCK,        SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MISO,       SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_WP_N,     SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CD_N,     RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SPI1_CS1_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_CS2_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+};
+
+void __init bonaire_pinmux_init(void)
+{
+       tegra12x_default_pinmux();
+       tegra_pinmux_config_table(bonaire_pinmux, ARRAY_SIZE(bonaire_pinmux));
+       tegra_drive_pinmux_config_table(bonaire_drive_pinmux,
+                                       ARRAY_SIZE(bonaire_drive_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-bonaire-power.c b/arch/arm/mach-tegra/board-bonaire-power.c
new file mode 100644 (file)
index 0000000..c2808a1
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2011 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/io.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/gpio-tegra.h>
+
+#include "pm.h"
+#include "board.h"
+
+static int ac_online(void)
+{
+       return 1;
+}
+
+static struct resource bonaire_pda_resources[] = {
+       [0] = {
+               .name   = "ac",
+       },
+};
+
+static struct pda_power_pdata bonaire_pda_data = {
+       .is_ac_online   = ac_online,
+};
+
+static struct platform_device bonaire_pda_power_device = {
+       .name           = "pda-power",
+       .id             = -1,
+       .resource       = bonaire_pda_resources,
+       .num_resources  = ARRAY_SIZE(bonaire_pda_resources),
+       .dev    = {
+               .platform_data  = &bonaire_pda_data,
+       },
+};
+
+static struct tegra_suspend_platform_data bonaire_suspend_data = {
+       .cpu_timer      = 2000,
+       .cpu_off_timer  = 0,
+       .suspend_mode   = TEGRA_SUSPEND_NONE,
+       .core_timer     = 0x7e7e,
+       .core_off_timer = 0,
+       .corereq_high   = false,
+       .sysclkreq_high = true,
+};
+
+int __init bonaire_regulator_init(void)
+{
+       platform_device_register(&bonaire_pda_power_device);
+       return 0;
+}
+
+int __init bonaire_suspend_init(void)
+{
+       tegra_init_suspend(&bonaire_suspend_data);
+       return 0;
+}
+
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+
+#define COSIM_SHUTDOWN_REG         0x538f0ffc
+
+static void bonaire_power_off(void)
+{
+       pr_err("Bonaire: Powering off the device\n");
+       writel(1, IO_ADDRESS(COSIM_SHUTDOWN_REG));
+       while (1)
+               ;
+}
+
+int __init bonaire_power_off_init(void)
+{
+       pm_power_off = bonaire_power_off;
+       return 0;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-bonaire.c b/arch/arm/mach-tegra/board-bonaire.c
new file mode 100644 (file)
index 0000000..713ec30
--- /dev/null
@@ -0,0 +1,582 @@
+/*
+ * arch/arm/mach-tegra/board-bonaire.c
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/i2c/panjit_ts.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+
+#include <mach/clk.h>
+#include <mach/gpio-tegra.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/i2s.h>
+#include <mach/audio.h>
+#include <mach/usb_phy.h>
+#include <mach/nand.h>
+#include <mach/hardware.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include "board.h"
+#include "board-bonaire.h"
+#include "clock.h"
+#include "common.h"
+#include "devices.h"
+#include "fuse.h"
+#include "gpio-names.h"
+
+#define ENABLE_OTG 0
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+       {
+               .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
+               .mapbase        = TEGRA_UARTA_BASE,
+               .irq            = INT_UARTA,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+               .type           = PORT_TEGRA,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = 13000000,
+       }, {
+               .flags          = 0,
+       }
+};
+
+static struct platform_device debug_uart = {
+       .name = "serial8250",
+       .id = PLAT8250_DEV_PLATFORM,
+       .dev = {
+               .platform_data = debug_uart_platform_data,
+       },
+};
+
+#ifdef CONFIG_BCM4329_RFKILL
+
+static struct resource bonaire_bcm4329_rfkill_resources[] = {
+       {
+               .name   = "bcm4329_nreset_gpio",
+               .start  = TEGRA_GPIO_PU0,
+               .end    = TEGRA_GPIO_PU0,
+               .flags  = IORESOURCE_IO,
+       },
+       {
+               .name   = "bcm4329_nshutdown_gpio",
+               .start  = TEGRA_GPIO_PK2,
+               .end    = TEGRA_GPIO_PK2,
+               .flags  = IORESOURCE_IO,
+       },
+};
+
+static struct platform_device bonaire_bcm4329_rfkill_device = {
+       .name = "bcm4329_rfkill",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(bonaire_bcm4329_rfkill_resources),
+       .resource       = bonaire_bcm4329_rfkill_resources,
+};
+
+static noinline void __init bonaire_bt_rfkill(void)
+{
+       /*Add Clock Resource*/
+       clk_add_alias("bcm4329_32k_clk", bonaire_bcm4329_rfkill_device.name, \
+                               "blink", NULL);
+
+       platform_device_register(&bonaire_bcm4329_rfkill_device);
+
+       return;
+}
+#else
+static inline void bonaire_bt_rfkill(void) { }
+#endif
+
+static __initdata struct tegra_clk_init_table bonaire_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "uarta",      "clk_m",        13000000,       true},
+       { "uartb",      "clk_m",        13000000,       true},
+       { "uartc",      "clk_m",        13000000,       true},
+       { "uartd",      "clk_m",        13000000,       true},
+       { "uarte",      "clk_m",        13000000,       true},
+       { "pll_m",      NULL,           0,              true},
+       { "blink",      "clk_32k",      32768,          false},
+       { "pll_p_out4", "pll_p",        24000000,       true },
+       { "pwm",        "clk_32k",      32768,          false},
+       { "blink",      "clk_32k",      32768,          false},
+       { "pll_a",      NULL,           56448000,       true},
+       { "pll_a_out0", NULL,           11289600,       true},
+       { "i2s1",       "pll_a_out0",   11289600,       true},
+       { "i2s2",       "pll_a_out0",   11289600,       true},
+       { "d_audio",    "pll_a_out0",   11289600,       false},
+       { "audio_2x",   "audio",        22579200,       true},
+       { NULL,         NULL,           0,              0},
+};
+
+static struct i2c_board_info __initdata bonaire_i2c_bus1_board_info[] = {
+       {
+               I2C_BOARD_INFO("wm8903", 0x1a),
+       },
+};
+
+static struct tegra_i2c_platform_data bonaire_i2c1_platform_data = {
+       .adapter_nr     = 0,
+       .bus_count      = 1,
+       .bus_clk_rate   = 100000,
+};
+
+#if 0  /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
+static const struct tegra_pingroup_config i2c2_ddc = {
+       .pingroup       = TEGRA_PINGROUP_DDC,
+       .func           = TEGRA_MUX_I2C2,
+};
+
+static const struct tegra_pingroup_config i2c2_gen2 = {
+       .pingroup       = TEGRA_PINGROUP_PTA,
+       .func           = TEGRA_MUX_I2C2,
+};
+#endif
+
+static struct tegra_i2c_platform_data bonaire_i2c2_platform_data = {
+       .adapter_nr     = 1,
+       .bus_count      = 2,
+       .bus_clk_rate   = { 100000, 100000 },
+#if 0  /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
+       .bus_mux        = { &i2c2_ddc, &i2c2_gen2 },
+       .bus_mux_len    = { 1, 1 },
+#endif
+};
+
+static struct tegra_i2c_platform_data bonaire_i2c3_platform_data = {
+       .adapter_nr     = 3,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+};
+
+static struct tegra_i2c_platform_data bonaire_i2c4_platform_data = {
+       .adapter_nr     = 4,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+};
+
+static struct tegra_i2c_platform_data bonaire_i2c5_platform_data = {
+       .adapter_nr     = 5,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+};
+
+static void bonaire_i2c_init(void)
+{
+       tegra_i2c_device1.dev.platform_data = &bonaire_i2c1_platform_data;
+       tegra_i2c_device2.dev.platform_data = &bonaire_i2c2_platform_data;
+       tegra_i2c_device3.dev.platform_data = &bonaire_i2c3_platform_data;
+       tegra_i2c_device4.dev.platform_data = &bonaire_i2c4_platform_data;
+       tegra_i2c_device5.dev.platform_data = &bonaire_i2c5_platform_data;
+
+       i2c_register_board_info(0, bonaire_i2c_bus1_board_info, 1);
+
+       platform_device_register(&tegra_i2c_device5);
+       platform_device_register(&tegra_i2c_device4);
+       platform_device_register(&tegra_i2c_device3);
+       platform_device_register(&tegra_i2c_device2);
+       platform_device_register(&tegra_i2c_device1);
+}
+
+#define GPIO_KEY(_id, _gpio, _iswake)          \
+       {                                       \
+               .code = _id,                    \
+               .gpio = TEGRA_GPIO_##_gpio,     \
+               .active_low = 1,                \
+               .desc = #_id,                   \
+               .type = EV_KEY,                 \
+               .wakeup = _iswake,              \
+               .debounce_interval = 10,        \
+       }
+
+/* !!!FIXME!!! THESE ARE VENTANA DEFINITIONS */
+static struct gpio_keys_button bonaire_keys[] = {
+       [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
+       [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
+       [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
+       [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
+       [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
+       [5] = GPIO_KEY(KEY_POWER, PV2, 1),
+};
+
+static struct gpio_keys_platform_data bonaire_keys_platform_data = {
+       .buttons        = bonaire_keys,
+       .nbuttons       = ARRAY_SIZE(bonaire_keys),
+};
+
+static struct platform_device bonaire_keys_device = {
+       .name   = "gpio-keys",
+       .id     = 0,
+       .dev    = {
+               .platform_data  = &bonaire_keys_platform_data,
+       },
+};
+
+static struct resource tegra_rtc_resources[] = {
+       [0] = {
+               .start = TEGRA_RTC_BASE,
+               .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = INT_RTC,
+               .end = INT_RTC,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_rtc_device = {
+       .name = "tegra_rtc",
+       .id   = -1,
+       .resource = tegra_rtc_resources,
+       .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+#if defined(CONFIG_MTD_NAND_TEGRA)
+static struct resource nand_resources[] = {
+       [0] = {
+               .start = INT_NANDFLASH,
+               .end   = INT_NANDFLASH,
+               .flags = IORESOURCE_IRQ
+       },
+       [1] = {
+               .start = TEGRA_NAND_BASE,
+               .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
+               .flags = IORESOURCE_MEM
+       }
+};
+
+static struct tegra_nand_chip_parms nand_chip_parms[] = {
+       /* Samsung K5E2G1GACM */
+       [0] = {
+               .vendor_id   = 0xEC,
+               .device_id   = 0xAA,
+               .capacity    = 256,
+               .timing      = {
+                       .trp            = 21,
+                       .trh            = 15,
+                       .twp            = 21,
+                       .twh            = 15,
+                       .tcs            = 31,
+                       .twhr           = 60,
+                       .tcr_tar_trr    = 20,
+                       .twb            = 100,
+                       .trp_resp       = 30,
+                       .tadl           = 100,
+               },
+       },
+       /* Hynix H5PS1GB3EFR */
+       [1] = {
+               .vendor_id   = 0xAD,
+               .device_id   = 0xDC,
+               .capacity    = 512,
+               .timing      = {
+                       .trp            = 12,
+                       .trh            = 10,
+                       .twp            = 12,
+                       .twh            = 10,
+                       .tcs            = 20,
+                       .twhr           = 80,
+                       .tcr_tar_trr    = 20,
+                       .twb            = 100,
+                       .trp_resp       = 20,
+                       .tadl           = 70,
+               },
+       },
+};
+
+struct tegra_nand_platform nand_data = {
+       .max_chips      = 8,
+       .chip_parms     = nand_chip_parms,
+       .nr_chip_parms  = ARRAY_SIZE(nand_chip_parms),
+};
+
+struct platform_device tegra_nand_device = {
+       .name          = "tegra_nand",
+       .id            = -1,
+       .resource      = nand_resources,
+       .num_resources = ARRAY_SIZE(nand_resources),
+       .dev            = {
+               .platform_data = &nand_data,
+       },
+};
+#endif
+
+#if defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && defined(CONFIG_SMC91X)
+static struct resource tegra_sim_smc91x_resources[] = {
+       [0] = {
+               .start          = TEGRA_SIM_ETH_BASE,
+               .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
+               .flags          = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start          = IRQ_ETH,
+               .end            = IRQ_ETH,
+               .flags          = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_sim_smc91x_device = {
+       .name           = "smc91x",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(tegra_sim_smc91x_resources),
+       .resource       = tegra_sim_smc91x_resources,
+};
+#endif
+
+static struct platform_device *bonaire_devices[] __initdata = {
+#if ENABLE_OTG
+       &tegra_otg_device,
+#endif
+       &debug_uart,
+       &tegra_uartb_device,
+       &tegra_uartc_device,
+       &tegra_uartd_device,
+       &tegra_uarte_device,
+       &tegra_pmu_device,
+       &tegra_rtc_device,
+       &tegra_udc_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU)
+       &tegra_smmu_device,
+#endif
+       &bonaire_keys_device,
+       &tegra_wdt_device,
+#if defined(CONFIG_SND_HDA_TEGRA)
+       &tegra_hda_device,
+#endif
+       &tegra_avp_device,
+#if defined(CONFIG_MTD_NAND_TEGRA)
+       &tegra_nand_device,
+#endif
+#if defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && defined(CONFIG_SMC91X)
+       &tegra_sim_smc91x_device,
+#endif
+};
+
+static void bonaire_keys_init(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(bonaire_keys); i++)
+               tegra_gpio_enable(bonaire_keys[i].gpio);
+}
+
+static int __init bonaire_touch_init(void)
+{
+       return 0;
+}
+
+#if defined(USB_HOST_ONLY)
+static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
+       [0] = {
+                       .phy_config = &utmi_phy_config[0],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 0,
+       },
+       [1] = {
+                       .phy_config = &ulpi_phy_config,
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 1,
+       },
+       [2] = {
+                       .phy_config = &utmi_phy_config[1],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 0,
+       },
+};
+#endif
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_DEVICE,
+       .u_data.dev = {
+               .vbus_pmu_irq = 0,
+               .vbus_gpio = -1,
+               .charging_supported = false,
+               .remote_wakeup_supported = false,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .vbus_reg = "vdd_vbus_micro_usb",
+               .hot_plug = true,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 15,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+       .port_otg = false,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode         = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = true,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 15,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+       .port_otg = false,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode         = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .vbus_reg = "vdd_vbus_typea_usb",
+               .hot_plug = true,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static void bonaire_usb_init(void)
+{
+#if defined(USB_HOST_ONLY)
+       tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
+       platform_device_register(&tegra_ehci1_device);
+#else
+       /* setup the udc platform data */
+       tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+
+#endif
+}
+
+static void __init tegra_bonaire_init(void)
+{
+       tegra_clk_init_from_table(bonaire_clk_init_table);
+       tegra_enable_pinmux();
+       bonaire_pinmux_init();
+
+       platform_add_devices(bonaire_devices, ARRAY_SIZE(bonaire_devices));
+
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+       bonaire_power_off_init();
+#endif
+
+       bonaire_sdhci_init();
+       bonaire_i2c_init();
+       bonaire_regulator_init();
+       bonaire_suspend_init();
+       bonaire_touch_init();
+       bonaire_keys_init();
+       bonaire_usb_init();
+       bonaire_panel_init();
+       bonaire_bt_rfkill();
+}
+
+static void __init tegra_bonaire_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+       tegra_reserve(0, SZ_4M, 0);
+#else
+#if defined(CONFIG_TEGRA_SIMULATION_SPLIT_MEM)
+       if (tegra_split_mem_active())
+               tegra_reserve(0, 0, 0);
+       else
+#endif
+               tegra_reserve(SZ_128M, SZ_4M, 0);
+#endif
+}
+
+
+MACHINE_START(BONAIRE, BONAIRE_BOARD_NAME)
+       .atag_offset    = 0x80000100,
+       .soc            = &tegra_soc_desc,
+       .map_io         = tegra_map_common_io,
+       .reserve        = tegra_bonaire_reserve,
+       .init_early     = tegra12x_init_early,
+       .init_irq       = tegra_init_irq,
+       .handle_irq     = gic_handle_irq,
+       .init_machine   = tegra_bonaire_init,
+       .timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-bonaire.h b/arch/arm/mach-tegra/board-bonaire.h
new file mode 100644 (file)
index 0000000..7727bdf
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/mach-tegra/board-bonaire.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Nvidia Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_BONAIRE_H
+#define _MACH_TEGRA_BOARD_BONAIRE_H
+
+/* External peripheral act as gpio */
+/* TPS6591x GPIOs */
+#define TPS6591X_GPIO_BASE      TEGRA_NR_GPIOS
+#define TPS6591X_GPIO_GP0       (TPS6591X_GPIO_BASE + 0)
+#define TPS6591X_GPIO_GP1       (TPS6591X_GPIO_BASE + 1)
+#define TPS6591X_GPIO_GP2       (TPS6591X_GPIO_BASE + 2)
+#define TPS6591X_GPIO_GP3       (TPS6591X_GPIO_BASE + 3)
+#define TPS6591X_GPIO_GP4       (TPS6591X_GPIO_BASE + 4)
+#define TPS6591X_GPIO_GP5       (TPS6591X_GPIO_BASE + 5)
+#define TPS6591X_GPIO_GP6       (TPS6591X_GPIO_BASE + 6)
+#define TPS6591X_GPIO_GP7       (TPS6591X_GPIO_BASE + 7)
+#define TPS6591X_GPIO_GP8       (TPS6591X_GPIO_BASE + 8)
+#define TPS6591X_GPIO_END       (TPS6591X_GPIO_GP8 + 1)
+
+/* PMU_TCA6416 GPIOs */
+#define PMU_TCA6416_GPIO_BASE   (TPS6591X_GPIO_END)
+#define PMU_TCA6416_GPIO_PORT00 (PMU_TCA6416_GPIO_BASE + 0)
+#define PMU_TCA6416_GPIO_PORT01 (PMU_TCA6416_GPIO_BASE + 1)
+#define PMU_TCA6416_GPIO_PORT02 (PMU_TCA6416_GPIO_BASE + 2)
+#define PMU_TCA6416_GPIO_PORT03 (PMU_TCA6416_GPIO_BASE + 3)
+#define PMU_TCA6416_GPIO_PORT04 (PMU_TCA6416_GPIO_BASE + 4)
+#define PMU_TCA6416_GPIO_PORT05 (PMU_TCA6416_GPIO_BASE + 5)
+#define PMU_TCA6416_GPIO_PORT06 (PMU_TCA6416_GPIO_BASE + 6)
+#define PMU_TCA6416_GPIO_PORT07 (PMU_TCA6416_GPIO_BASE + 7)
+#define PMU_TCA6416_GPIO_PORT10 (PMU_TCA6416_GPIO_BASE + 8)
+#define PMU_TCA6416_GPIO_PORT11 (PMU_TCA6416_GPIO_BASE + 9)
+#define PMU_TCA6416_GPIO_PORT12 (PMU_TCA6416_GPIO_BASE + 10)
+#define PMU_TCA6416_GPIO_PORT13 (PMU_TCA6416_GPIO_BASE + 11)
+#define PMU_TCA6416_GPIO_PORT14 (PMU_TCA6416_GPIO_BASE + 12)
+#define PMU_TCA6416_GPIO_PORT15 (PMU_TCA6416_GPIO_BASE + 13)
+#define PMU_TCA6416_GPIO_PORT16 (PMU_TCA6416_GPIO_BASE + 14)
+#define PMU_TCA6416_GPIO_PORT17 (PMU_TCA6416_GPIO_BASE + 15)
+#define PMU_TCA6416_GPIO_END    (PMU_TCA6416_GPIO_BASE + 16)
+
+int bonaire_regulator_init(void);
+int bonaire_sdhci_init(void);
+int bonaire_pinmux_init(void);
+int bonaire_panel_init(void);
+int bonaire_sensors_init(void);
+int bonaire_suspend_init(void);
+
+#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
+
+#define BONAIRE_BOARD_NAME "bonaire_sim"
+
+int bonaire_power_off_init(void);
+
+#else
+
+#define BONAIRE_BOARD_NAME "bonaire"
+
+#endif
+
+#endif
index c0afbcc..7e6e634 100644 (file)
@@ -89,6 +89,7 @@ void tegra_assert_system_reset(char mode, const char *cmd);
 void __init tegra20_init_early(void);
 void __init tegra30_init_early(void);
 void __init tegra11x_init_early(void);
+void __init tegra12x_init_early(void);
 void __init tegra14x_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_dt_init_irq(void);
diff --git a/arch/arm/mach-tegra/tegra12_host1x_devices.h b/arch/arm/mach-tegra/tegra12_host1x_devices.h
new file mode 100644 (file)
index 0000000..e75c93c
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * drivers/video/tegra/host/tegra12_host1x_devices.h
+ *
+ * Tegra12 Graphics Host Devices
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TEGRA12_HOST1X_DEVICES_H
+#define TEGRA12_HOST1X_DEVICES_H
+
+int tegra12_register_host1x_devices(void);
+
+#endif
index e3a6e9a..88ec210 100644 (file)
@@ -817,7 +817,7 @@ void *nvmap_mmap(struct nvmap_handle_ref *ref)
        adj_size += h->size;
        adj_size = PAGE_ALIGN(adj_size);
 
-       v = alloc_vm_area(adj_size, NULL);
+       v = alloc_vm_area(adj_size);
        if (!v) {
                nvmap_handle_put(h);
                return NULL;
@@ -915,7 +915,10 @@ struct nvmap_handle_ref *nvmap_alloc(struct nvmap_client *client, size_t size,
                return r;
 
        err = nvmap_alloc_handle_id(client, nvmap_ref_to_id(r),
-                                   heap_mask, align, flags);
+                                   heap_mask, align,
+                                   0, /* kind n/a */
+                                   flags & ~(NVMAP_HANDLE_KIND_SPECIFIED |
+                                             NVMAP_HANDLE_COMPR_SPECIFIED));
 
        if (err) {
                nvmap_free_handle_id(client, nvmap_ref_to_id(r));
@@ -950,7 +953,10 @@ struct nvmap_handle_ref *nvmap_alloc_iovm(struct nvmap_client *client,
        h = r->handle;
        h->pgalloc.iovm_addr = iovm_start;
        err = nvmap_alloc_handle_id(client, nvmap_ref_to_id(r),
-                       default_heap, align, flags);
+                                   default_heap, align,
+                                   0, /* kind n/a */
+                                   flags & ~(NVMAP_HANDLE_KIND_SPECIFIED |
+                                             NVMAP_HANDLE_COMPR_SPECIFIED));
        if (err)
                goto fail;
 
index d732087..40d2b60 100644 (file)
@@ -27,7 +27,6 @@
 #include <linux/kernel.h>
 #include <linux/miscdevice.h>
 #include <linux/mm.h>
-#include <linux/module.h>
 #include <linux/oom.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>
@@ -134,6 +133,8 @@ int is_nvmap_vma(struct vm_area_struct *vma)
 
 struct device *nvmap_client_to_device(struct nvmap_client *client)
 {
+       if (!client)
+               return 0;
        if (client->super)
                return client->dev->dev_super.this_device;
        else
@@ -1132,7 +1133,7 @@ static int nvmap_probe(struct platform_device *pdev)
                goto fail;
        }
 #endif
-       dev->vm_rgn = alloc_vm_area(NVMAP_NUM_PTES * PAGE_SIZE, NULL);
+       dev->vm_rgn = alloc_vm_area(NVMAP_NUM_PTES * PAGE_SIZE);
        if (!dev->vm_rgn) {
                e = -ENOMEM;
                dev_err(&pdev->dev, "couldn't allocate remapping region\n");
index 16acd79..f3933d6 100644 (file)
@@ -41,6 +41,7 @@
 #include <asm/pgtable.h>
 
 #include <mach/iovmm.h>
+#include <mach/hardware.h>
 #include <trace/events/nvmap.h>
 
 #include "nvmap_priv.h"
@@ -787,7 +788,9 @@ static const unsigned int heap_policy_large[] = {
 
 int nvmap_alloc_handle_id(struct nvmap_client *client,
                          unsigned long id, unsigned int heap_mask,
-                         size_t align, unsigned int flags)
+                         size_t align,
+                         u8 kind,
+                         unsigned int flags)
 {
        struct nvmap_handle *h = NULL;
        const unsigned int *alloc_policy;
@@ -810,6 +813,8 @@ int nvmap_alloc_handle_id(struct nvmap_client *client,
        h->secure = !!(flags & NVMAP_HANDLE_SECURE);
        h->flags = (flags & NVMAP_HANDLE_CACHE_FLAG);
        h->align = max_t(size_t, align, L1_CACHE_BYTES);
+       h->kind = kind;
+       h->map_resources = 0;
 
 #ifndef CONFIG_TEGRA_IOVMM
        /* convert iovmm requests to generic carveout. */
@@ -1308,6 +1313,12 @@ int nvmap_get_handle_param(struct nvmap_client *client,
                } else
                        *result = NVMAP_HEAP_IOVMM;
                break;
+       case NVMAP_HANDLE_PARAM_KIND:
+               *result = h->kind;
+               break;
+       case NVMAP_HANDLE_PARAM_COMPR:
+               /* ignored, to be removed */
+               break;
        default:
                err = -EINVAL;
                break;
index abd1815..2e0de6e 100644 (file)
@@ -26,7 +26,6 @@
 #include <linux/mm.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
-#include <linux/stat.h>
 #include <linux/err.h>
 
 #include <linux/nvmap.h>
index bd35cc6..5dbc5c5 100644 (file)
@@ -319,7 +319,7 @@ int nvmap_ioctl_alloc(struct file *filp, void __user *arg)
 #endif
 
        return nvmap_alloc_handle_id(client, handle, op.heap_mask,
-                                    op.align, op.flags);
+                                    op.align, op.kind, op.flags);
 }
 
 int nvmap_ioctl_create(struct file *filp, unsigned int cmd, void __user *arg)
@@ -473,11 +473,13 @@ out:
        return err;
 }
 
+
 int nvmap_ioctl_get_param(struct file *filp, void __user* arg)
 {
        struct nvmap_handle_param op;
        struct nvmap_client *client = filp->private_data;
        struct nvmap_handle *h;
+       u32 result;
        int err = 0;
        ulong handle;
 
@@ -489,50 +491,8 @@ int nvmap_ioctl_get_param(struct file *filp, void __user* arg)
        if (!h)
                return -EINVAL;
 
-       switch (op.param) {
-       case NVMAP_HANDLE_PARAM_SIZE:
-               op.result = h->orig_size;
-               break;
-       case NVMAP_HANDLE_PARAM_ALIGNMENT:
-               mutex_lock(&h->lock);
-               if (!h->alloc)
-                       op.result = 0;
-               else if (h->heap_pgalloc)
-                       op.result = PAGE_SIZE;
-               else if (h->carveout->base)
-                       op.result = (h->carveout->base & -h->carveout->base);
-               else
-                       op.result = SZ_4M;
-               mutex_unlock(&h->lock);
-               break;
-       case NVMAP_HANDLE_PARAM_BASE:
-               if (WARN_ON(!h->alloc || !atomic_add_return(0, &h->pin)))
-                       op.result = -1ul;
-               else if (!h->heap_pgalloc) {
-                       mutex_lock(&h->lock);
-                       op.result = h->carveout->base;
-                       mutex_unlock(&h->lock);
-               } else if (h->pgalloc.contig)
-                       op.result = page_to_phys(h->pgalloc.pages[0]);
-               else if (h->pgalloc.area)
-                       op.result = h->pgalloc.area->iovm_start;
-               else
-                       op.result = -1ul;
-               break;
-       case NVMAP_HANDLE_PARAM_HEAP:
-               if (!h->alloc)
-                       op.result = 0;
-               else if (!h->heap_pgalloc) {
-                       mutex_lock(&h->lock);
-                       op.result = nvmap_carveout_usage(client, h->carveout);
-                       mutex_unlock(&h->lock);
-               } else
-                       op.result = NVMAP_HEAP_IOVMM;
-               break;
-       default:
-               err = -EINVAL;
-               break;
-       }
+       err = nvmap_get_handle_param_u32(client, h, op.param, &result);
+       op.result = (long unsigned int)result;
 
        if (!err && copy_to_user(arg, &op, sizeof(op)))
                err = -EFAULT;
index b2057e5..7dd8ca4 100644 (file)
@@ -43,6 +43,8 @@ enum {
        NVMAP_HANDLE_PARAM_ALIGNMENT,
        NVMAP_HANDLE_PARAM_BASE,
        NVMAP_HANDLE_PARAM_HEAP,
+       NVMAP_HANDLE_PARAM_KIND,
+       NVMAP_HANDLE_PARAM_COMPR, /* ignored, to be removed */
 };
 
 enum {
index b7f01e4..821ea9d 100644 (file)
@@ -90,6 +90,9 @@ struct nvmap_handle {
        size_t size;            /* padded (as-allocated) size */
        size_t orig_size;       /* original (as-requested) size */
        size_t align;
+       u8 kind;                /* memory kind (0=pitch, !0 -> blocklinear) */
+       void *map_resources;    /* mapping resources associated with the
+                                  buffer */
        struct nvmap_client *owner;
        struct nvmap_handle_ref *owner_ref; /* use this ref to avoid spending
                        time on validation in some cases.
@@ -289,7 +292,8 @@ struct nvmap_handle_ref *nvmap_create_handle_from_fd(
 
 int nvmap_alloc_handle_id(struct nvmap_client *client,
                          unsigned long id, unsigned int heap_mask,
-                         size_t align, unsigned int flags);
+                         size_t align, u8 kind,
+                         unsigned int flags);
 
 void nvmap_free_handle_id(struct nvmap_client *c, unsigned long id);
 
@@ -343,4 +347,7 @@ static inline void nvmap_flush_tlb_kernel_page(unsigned long kaddr)
 #endif
 }
 
+int nvmap_get_handle_param_u32(struct nvmap_client *client,
+                              struct nvmap_handle *h, u32 param, u32 *result);
+
 #endif /* __VIDEO_TEGRA_NVMAP_NVMAP_H */
index c67baa9..68712af 100644 (file)
@@ -50,6 +50,9 @@
 #define NVMAP_HANDLE_SECURE          (0x1ul << 2)
 #define NVMAP_HANDLE_ZEROED_PAGES    (0x1ul << 3)
 
+#define NVMAP_HANDLE_KIND_SPECIFIED  (0x1ul << 3)
+#define NVMAP_HANDLE_COMPR_SPECIFIED (0x1ul << 4)
+
 struct nvmap_handle;
 
 #if defined(__KERNEL__)