ARM: tegra11: dvfs: Increase max AMX/ADX clock rate
Alex Frid [Sun, 16 Jun 2013 06:03:06 +0000 (23:03 -0700)]
Increased maximum AMX/ADX clock rate from 19.91MHz to 24.73MHz.

Bug 1161126

Change-Id: I637eb483a570a91511ae472053bac5287ac9f92f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239140
(cherry picked from commit d1861462d318d4c6483543f26a1f1bc6e2dc3043)
Reviewed-on: http://git-master/r/241233
(cherry picked from commit 0d4302e2f31caeea4dbce2d3c0379d5eedf57d5c)
Reviewed-on: http://git-master/r/271881
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 48c33c5..b592869 100644 (file)
@@ -6874,8 +6874,8 @@ struct clk tegra_list_clks[] = {
        D_AUDIO_CLK("dam0",     "tegra30-dam.0",        NULL,   108,    0x3d8,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
        D_AUDIO_CLK("dam1",     "tegra30-dam.1",        NULL,   109,    0x3dc,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
        D_AUDIO_CLK("dam2",     "tegra30-dam.2",        NULL,   110,    0x3e0,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("adx",       "adx",                  NULL,   154,    0x638,  19910000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("amx",       "amx",                  NULL,   153,    0x63c,  19910000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("adx",       "adx",                  NULL,   154,    0x638,  24730000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("amx",       "amx",                  NULL,   153,    0x63c,  24730000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda",       "tegra30-hda",          "hda",          125,    0x428,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),