ARM: tegra12: clock: Rename "gpu" to "gpu_ref"
Kaz Fukuoka [Thu, 5 Sep 2013 23:25:24 +0000 (16:25 -0700)]
GPU PLL reference clock was mistakenly named as "gpu".

Change-Id: I5083cdfd98795002d46a68806e2c9d41282eb9a4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/271103
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/powergate-t12x.c
arch/arm/mach-tegra/tegra12_clocks.c

index d057220..2084259 100644 (file)
@@ -433,7 +433,7 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "sbc4.sclk",  NULL,           40000000,       false},
        { "sbc5.sclk",  NULL,           40000000,       false},
        { "sbc6.sclk",  NULL,           40000000,       false},
-       { "gpu",        NULL,           0,              true},
+       { "gpu_ref",    NULL,           0,              true},
 #ifdef CONFIG_TEGRA_PLLM_SCALED
        { "vi",         "pll_p",        0,              false},
        { "isp",        "pll_p",        0,              false},
index 16250ee..5d59136 100644 (file)
@@ -139,7 +139,7 @@ static struct powergate_partition_info tegra12x_powergate_partition_info[] = {
        [TEGRA_POWERGATE_GPU] = {
                .name = "gpu",
                .clk_info = {
-                       [0] = { .clk_name = "gpu", .clk_type = CLK_AND_RST },
+                       [0] = { .clk_name = "gpu_ref", .clk_type = CLK_AND_RST },
                },
        },
        [TEGRA_POWERGATE_VDEC] = {
index 3258819..5a31920 100644 (file)
@@ -6973,7 +6973,7 @@ static struct clk_ops tegra_clk_gpu_ops = {
    dvfs to control voltage of gpu rail along with frequency change of actual
    gpu clock. So frequency here and in dvfs are based on the acutal gpu clock. */
 static struct clk tegra_clk_gpu = {
-       .name      = "gpu",
+       .name      = "gpu_ref",
        .ops       = &tegra_clk_gpu_ops,
        .parent    = &tegra_pll_ref,
        .u.periph  = {
@@ -7601,7 +7601,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
        CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
        CLK_DUPLICATE("actmon", "tegra_host1x", "actmon"),
-       CLK_DUPLICATE("gpu", "tegra_gk20a", "PLLG_ref"),
+       CLK_DUPLICATE("gpu_ref", "tegra_gk20a", "PLLG_ref"),
        CLK_DUPLICATE("gbus", "tegra_gk20a", "PLLG_out"),
        CLK_DUPLICATE("pll_p_out5", "tegra_gk20a", "pwr"),
        CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp", "isp"),