ARM: tegra11x: Fix CRAIL power up sequence
Bo Yan [Thu, 18 Oct 2012 00:24:20 +0000 (17:24 -0700)]
When switching cluster from slow to fast, it's desirable to power
up CRAIL first to introduce some parallism with software context
save.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/145430
(cherry picked from commit f81caa0a9ef390d326b344ca5c1dd2f6550df1d0)

Change-Id: I4cef9ff32bbf0118fad34aa202e20a2be0c7925a
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146488
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R6ed945d422ee49ef87e3b589c6f9fee7b53f1bb3

arch/arm/mach-tegra/pm.c

index 36a132c..7683cdb 100644 (file)
@@ -604,9 +604,16 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
                         * transition. Before the transition, enable
                         * the vdd_cpu rail.
                         */
-                       if (is_lp_cluster())
+                       if (is_lp_cluster()) {
+#if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
+                               reg = readl(FLOW_CTRL_CPU_PWR_CSR);
+                               reg |= FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE;
+                               writel(reg, FLOW_CTRL_CPU_PWR_CSR);
+#else
                                writel(UN_PWRGATE_CPU,
                                       pmc + PMC_PWRGATE_TOGGLE);
+#endif
+                       }
                }
                tegra_cluster_switch_prolog(flags);
        } else {