ARM: tegra: power: setup TTB0 for cacheable memory
Jin Qian [Tue, 16 Aug 2011 02:32:23 +0000 (19:32 -0700)]
Bug 862494

Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3
Reviewed-on: http://git-master/r/47246
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58

arch/arm/mach-tegra/pm.c

index 0d86f37..8fda333 100644 (file)
@@ -242,7 +242,8 @@ static __init int create_suspend_pgtable(void)
        identity_mapping_add(tegra_pgd, IO_IRAM_VIRT,
                IO_IRAM_VIRT + SECTION_SIZE, 0);
 
-       tegra_pgd_phys = virt_to_phys(tegra_pgd);
+       /* inner/outer write-back/write-allocate, sharable */
+       tegra_pgd_phys = (virt_to_phys(tegra_pgd) & PAGE_MASK) | 0x4A;
 
        return 0;
 }