mmc: host: tegra: fixup NVQUIRKS ordering.
Shridhar Rasal [Mon, 16 Sep 2013 10:16:39 +0000 (15:16 +0530)]
Change-Id: I6879367274784ad973d29d4efcf3ca74857e9736
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/275630
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Eric Miao <emiao@nvidia.com>
Tested-by: Eric Miao <emiao@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

drivers/mmc/host/sdhci-tegra.c

index 5530d38..40ab9c2 100644 (file)
@@ -169,14 +169,14 @@ static unsigned int uhs_max_freq_MHz[] = {
 /* update PAD_E_INPUT_OR_E_PWRD bit */
 #define NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD      BIT(18)
 /* Shadow write xfer mode reg and write it alongwith CMD register */
-#define NVQUIRK_SHADOW_XFER_MODE_REG           BIT(18)
+#define NVQUIRK_SHADOW_XFER_MODE_REG           BIT(19)
 /* In SDR50 mode, run the sdmmc controller at freq greater than
  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
  * is below 1.2V, CRC errors would occur during data transfers
  */
-#define NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK  BIT(19)
+#define NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK  BIT(20)
 /* Set Pipe stages value o zero */
-#define NVQUIRK_SET_PIPE_STAGES_MASK_0         BIT(20)
+#define NVQUIRK_SET_PIPE_STAGES_MASK_0         BIT(21)
 
 struct sdhci_tegra_soc_data {
        const struct sdhci_pltfm_data *pdata;