ARM: tegra11: clock: Restore SCLK and HCLK rate limits
Alex Frid [Tue, 11 Dec 2012 06:54:05 +0000 (22:54 -0800)]
Set back minimum 12 MHz rate for system and AHB clocks (SCLK and
HCLK) - partial revert of cf02b47b2dfdbe1e19a40df6bd28620a0c422ce9
Bug 1057646 requires HCLK:PCLK 2:1 ratio only starting from 60MHz.

Change-Id: Ic82cac35b9861dccbc66b29c9d507c1100c73d7c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169967
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index c4f22fa..871a9eb 100644 (file)
@@ -5792,7 +5792,7 @@ static struct clk tegra_clk_sclk = {
        .reg    = 0x28,
        .ops    = &tegra_super_ops,
        .max_rate = 336000000,
-       .min_rate = 24000000,
+       .min_rate = 12000000,
 };
 
 static struct clk tegra_clk_virtual_cpu_g = {
@@ -5851,7 +5851,7 @@ static struct clk tegra_clk_hclk = {
        .reg_shift      = 4,
        .ops            = &tegra_bus_ops,
        .max_rate       = 336000000,
-       .min_rate       = 24000000,
+       .min_rate       = 12000000,
 };
 
 static struct clk tegra_clk_pclk = {