arm: tegra: Disable EMC clock in SoC idle state
Prashant Gaikwad [Thu, 25 Apr 2013 12:34:56 +0000 (17:34 +0530)]
Bug 1294838

Change-Id: I8ba04077b20588b0e9f092ef164712f053b70b8f
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/237510
(cherry picked from commit 22a87133ad417f2cd69e4d83b5fcb84e0ac64ae1)
Reviewed-on: http://git-master/r/252264
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

arch/arm/mach-tegra/sleep-t30.S

index cff5567..4036591 100644 (file)
@@ -397,9 +397,15 @@ ENTRY(tegra3_lp1_reset)
        ldr     r8, [r12, #RESET_DATA(MASK_MC_CLK)]
        tst     r8, r11         @ if memory clock stopped
        mov32   r2, TEGRA_PMC_BASE
-       bne     emc_exit_selfrefresh
+       beq     resume_lp1
 
        mov32   r0, TEGRA_CLK_RESET_BASE
+       mov     r1, #(1 << 25)
+       str     r1, [r0, #CLK_RESET_CLK_ENB_H_SET]
+       b       emc_exit_selfrefresh
+
+resume_lp1:
+       mov32   r0, TEGRA_CLK_RESET_BASE
 #if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL)
        /* secure code handles 32KHz to CLKM/OSC clock switch */
        mov     r1, #(1<<28)
@@ -924,6 +930,8 @@ tegra3_lp0_tear_down_core:
 
 tegra3_stop_mc_clk:
        bl      tegra3_sdram_self_refresh
+       mov     r1, #(1 << 25)
+       str     r1, [r5, #CLK_RESET_CLK_ENB_H_CLR]
        b       tegra3_enter_sleep
 
 /*