clock: tegra21: Use OSC as PLLE reference
Alex Frid [Wed, 27 Aug 2014 01:54:03 +0000 (18:54 -0700)]
Switched PLLE reference clock from PLLREFE to OSC (with dividers
settings: M = 2, N = 125, PDIV = 14).

Bug 1546078

Change-Id: I74af702c285511449048942c9d78c9d0f5c1b32a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488544
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

drivers/platform/tegra/tegra21_clocks.c

index f59ccc9..5e601ff 100644 (file)
 #define PLLP_DEFAULT_FIXED_RATE                408000000
 
 /* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
-#define USE_PLLE_INPUT_PLLRE    1
+#define USE_PLLE_INPUT_PLLRE    0
 
 static void pllc4_set_fixed_rates(unsigned long cf);
 static void tegra21_dfll_cpu_late_init(struct clk *c);