arm: t124: ardbeg: Add SPI support
Shardar Shariff Md [Thu, 27 Jun 2013 05:53:26 +0000 (10:53 +0530)]
Bug 1271900

Change-Id: I3d7269c4aa1ffffb4a59deb8554c845db8adf79f
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/242743
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arch/arm/configs/tegra12_android_defconfig
arch/arm/mach-tegra/board-ardbeg.c
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/tegra12_clocks.c

index 5700ecb..cd44c9b 100644 (file)
@@ -278,6 +278,7 @@ CONFIG_I2C_MUX_PCA954x=y
 # CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
+CONFIG_SPI_TEGRA114=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_AS3722=y
index 3497f39..abed36e 100644 (file)
@@ -632,18 +632,26 @@ static void ardbeg_modem_init(void)
 
 #ifndef CONFIG_USE_OF
 static struct platform_device *ardbeg_spi_devices[] __initdata = {
+       &tegra11_spi_device1,
        &tegra11_spi_device4,
 };
 
-static struct tegra_spi_platform_data ardbeg_spi_pdata = {
-       .dma_req_sel            = 0,
+static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
+       .dma_req_sel            = 15,
+       .spi_max_frequency      = 25000000,
+       .clock_always_on        = false,
+};
+
+static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
+       .dma_req_sel            = 18,
        .spi_max_frequency      = 25000000,
        .clock_always_on        = false,
 };
 
 static void __init ardbeg_spi_init(void)
 {
-       tegra11_spi_device4.dev.platform_data = &ardbeg_spi_pdata;
+       tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
+       tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
        platform_add_devices(ardbeg_spi_devices,
                        ARRAY_SIZE(ardbeg_spi_devices));
 }
index ead88a3..f01618f 100644 (file)
@@ -842,7 +842,7 @@ struct platform_device tegra11_spi_device1 = {
        .resource       = spi_resource1,
        .num_resources  = ARRAY_SIZE(spi_resource1),
        .dev            = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 
@@ -852,7 +852,7 @@ struct platform_device tegra11_spi_device2 = {
        .resource       = spi_resource2,
        .num_resources  = ARRAY_SIZE(spi_resource2),
        .dev            = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 
@@ -862,7 +862,7 @@ struct platform_device tegra11_spi_device3 = {
        .resource       = spi_resource3,
        .num_resources  = ARRAY_SIZE(spi_resource3),
        .dev            = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 
@@ -872,7 +872,7 @@ struct platform_device tegra11_spi_device4 = {
        .resource       = spi_resource4,
        .num_resources  = ARRAY_SIZE(spi_resource4),
        .dev            = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 
@@ -883,7 +883,7 @@ struct platform_device tegra11_spi_device5 = {
        .resource       = spi_resource5,
        .num_resources  = ARRAY_SIZE(spi_resource5),
        .dev  = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 
@@ -893,7 +893,7 @@ struct platform_device tegra11_spi_device6 = {
        .resource       = spi_resource6,
        .num_resources  = ARRAY_SIZE(spi_resource6),
        .dev  = {
-               .coherent_dma_mask      = 0xffffffff,
+               .coherent_dma_mask      = DMA_BIT_MASK(64),
        },
 };
 #endif
@@ -2154,7 +2154,7 @@ struct swgid_fixup tegra_swgid_fixup_t124[] = {
          SWGID(PPCS2), },
        { .name = "tegra11-se", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
          SWGID(PPCS2), },
-       { .name = "tegra11-spi",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
+       { .name = "spi-tegra114",       .swgids = SWGID(PPCS) | SWGID(PPCS1) |
          SWGID(PPCS2), },
        { .name = "tegra14-i2c",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
          SWGID(PPCS2), },
index b112f70..764be04 100644 (file)
@@ -6815,12 +6815,18 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
-       PERIPH_CLK("sbc1",      "tegra11-spi.0",                NULL,   41,     0x134,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc2",      "tegra11-spi.1",                NULL,   44,     0x118,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc3",      "tegra11-spi.2",                NULL,   46,     0x11c,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc4",      "tegra11-spi.3",                NULL,   68,     0x1b4,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc5",      "tegra11-spi.4",                NULL,   104,    0x3c8,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc6",      "tegra11-spi.5",                NULL,   105,    0x3cc,  48000000, mux_pllp_pllc_pllm_clkm,      MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 48000000,
+                       mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),