arch: arm: tegra: loki: Update EMC table to 0x18
Sang-Hun Lee [Tue, 3 Dec 2013 01:38:16 +0000 (20:38 -0500)]
Bug 1326949
Bug 1361282
Bug 1393328

Change-Id: I318433fa5fd1201f14d054c3abba9d18a0e073a7
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/337571
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

arch/arm/mach-tegra/board-loki-memory.c

index 976f19f..7070485 100644 (file)
 #include "tegra12_emc.h"
 #include "devices.h"
 
-static struct tegra12_emc_table loki_a02_emc_table[] = {
+static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
        {
-               0x15,       /* V5.0.2 */
-               "01_12750_V01_V5.0.2_V0.3", /* DVFS table version */
-               12750,      /* SDRAM frequency */
-               780,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x4000003e, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000000, /* EMC_RC */
-                       0x00000003, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000000, /* EMC_RAS */
-                       0x00000000, /* EMC_RP */
-                       0x00000003, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000000, /* EMC_RD_RCD */
-                       0x00000000, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x00000004, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x0000000c, /* EMC_QSAFE */
-                       0x0000000c, /* EMC_RDV */
-                       0x0000000e, /* EMC_RDV_MASK */
-                       0x00000060, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000007, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x00000005, /* EMC_TXSR */
-                       0x00000005, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000000, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x00000064, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000007, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00000000, /* EMC_ZCAL_INTERVAL */
-                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000f3f3, /* EMC_CFG_PIPE */
-                       0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x40040001, /* MC_EMEM_ARB_CFG */
-                       0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-                       0x77e30303, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000007, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               57820,      /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_20400_V01_V5.0.2_V0.3", /* DVFS table version */
-               20400,      /* SDRAM frequency */
-               780,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x40000026, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000000, /* EMC_RC */
-                       0x00000005, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000000, /* EMC_RAS */
-                       0x00000000, /* EMC_RP */
-                       0x00000003, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000000, /* EMC_RD_RCD */
-                       0x00000000, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x00000004, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x0000000c, /* EMC_QSAFE */
-                       0x0000000c, /* EMC_RDV */
-                       0x0000000e, /* EMC_RDV_MASK */
-                       0x0000009a, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000007, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x00000006, /* EMC_TXSR */
-                       0x00000006, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000000, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x000000a0, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x0000000b, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00000000, /* EMC_ZCAL_INTERVAL */
-                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000f3f3, /* EMC_CFG_PIPE */
-                       0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x40020001, /* MC_EMEM_ARB_CFG */
-                       0x80000012, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-                       0x76230303, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               35610,      /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_40800_V01_V5.0.2_V0.3", /* DVFS table version */
-               40800,      /* SDRAM frequency */
-               780,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x40000012, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000001, /* EMC_RC */
-                       0x0000000a, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000001, /* EMC_RAS */
-                       0x00000000, /* EMC_RP */
-                       0x00000003, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000000, /* EMC_RD_RCD */
-                       0x00000000, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x00000004, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x0000000c, /* EMC_QSAFE */
-                       0x0000000c, /* EMC_RDV */
-                       0x0000000e, /* EMC_RDV_MASK */
-                       0x00000134, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000008, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x0000000c, /* EMC_TXSR */
-                       0x0000000c, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000000, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x0000013f, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000015, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00000000, /* EMC_ZCAL_INTERVAL */
-                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000f3f3, /* EMC_CFG_PIPE */
-                       0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0xa0000001, /* MC_EMEM_ARB_CFG */
-                       0x80000017, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-                       0x74a30303, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000014, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               20850,      /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_68000_V01_V5.0.2_V0.3", /* DVFS table version */
-               68000,      /* SDRAM frequency */
-               780,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x4000000a, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000003, /* EMC_RC */
-                       0x00000011, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000002, /* EMC_RAS */
-                       0x00000000, /* EMC_RP */
-                       0x00000003, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000000, /* EMC_RD_RCD */
-                       0x00000000, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x00000004, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x0000000c, /* EMC_QSAFE */
-                       0x0000000c, /* EMC_RDV */
-                       0x0000000e, /* EMC_RDV_MASK */
-                       0x00000202, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x0000000f, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x00000013, /* EMC_TXSR */
-                       0x00000013, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000001, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x00000213, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000022, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00000000, /* EMC_ZCAL_INTERVAL */
-                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000f3f3, /* EMC_CFG_PIPE */
-                       0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x00000001, /* MC_EMEM_ARB_CFG */
-                       0x8000001e, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-                       0x74230403, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000021, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff00b0, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00e90049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff00a3, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00ee00ef, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               10720,      /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_102000_V01_V5.0.2_V0.3", /* DVFS table version */
-               102000,     /* SDRAM frequency */
-               780,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x40000006, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000004, /* EMC_RC */
-                       0x0000001a, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000003, /* EMC_RAS */
-                       0x00000001, /* EMC_RP */
-                       0x00000003, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000001, /* EMC_RD_RCD */
-                       0x00000001, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x00000006, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x00000004, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x0000000c, /* EMC_QSAFE */
-                       0x0000000c, /* EMC_RDV */
-                       0x0000000e, /* EMC_RDV_MASK */
-                       0x00000304, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000000c1, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000018, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x0000001c, /* EMC_TXSR */
-                       0x0000001c, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000003, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x0000031c, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000033, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00000000, /* EMC_ZCAL_INTERVAL */
-                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000f3f3, /* EMC_CFG_PIPE */
-                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x08000001, /* MC_EMEM_ARB_CFG */
-                       0x80000026, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
-                       0x73c30504, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000031, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff0075, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x009b0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x000800ad, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff00c6, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff006d, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff00d6, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x009f00a0, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff00da, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               6890,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_204000_V01_V5.0.2_V0.3", /* DVFS table version */
-               204000,     /* SDRAM frequency */
-               800,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllp_out0", /* clock source id */
-               0x40000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000009, /* EMC_RC */
-                       0x00000035, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000006, /* EMC_RAS */
-                       0x00000002, /* EMC_RP */
-                       0x00000004, /* EMC_R2W */
-                       0x0000000a, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x0000000b, /* EMC_W2P */
-                       0x00000002, /* EMC_RD_RCD */
-                       0x00000002, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000003, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000004, /* EMC_WDV */
-                       0x00000004, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000000, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000003, /* EMC_EINPUT */
-                       0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000002, /* EMC_QRST */
-                       0x0000000d, /* EMC_QSAFE */
-                       0x0000000e, /* EMC_RDV */
-                       0x00000010, /* EMC_RDV_MASK */
-                       0x00000607, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x00000002, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000032, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x00000038, /* EMC_TXSR */
-                       0x00000038, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000007, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x00000638, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00004000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00004000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0030a118, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00001212, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000066, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
-                       0x0000d3b3, /* EMC_CFG_PIPE */
-                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x01000003, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0404, /* MC_EMEM_ARB_DA_COVERS */
-                       0x73840a05, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000062, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x004e0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080057, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff0063, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff0036, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff006b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510050, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff00c6, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff006d, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73240000, /* EMC_CFG */
-               0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80001221, /* Mode Register 0 */
-               0x80100003, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               3420,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_312000_V01_V5.0.2_V0.3", /* DVFS table version */
-               312000,     /* SDRAM frequency */
-               820,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllm_out0", /* clock source id */
-               0x00000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x0000000d, /* EMC_RC */
-                       0x00000050, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000009, /* EMC_RAS */
-                       0x00000003, /* EMC_RP */
-                       0x00000004, /* EMC_R2W */
-                       0x00000008, /* EMC_W2R */
-                       0x00000002, /* EMC_R2P */
-                       0x00000009, /* EMC_W2P */
-                       0x00000003, /* EMC_RD_RCD */
-                       0x00000003, /* EMC_WR_RCD */
-                       0x00000002, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000003, /* EMC_WDV */
-                       0x00000003, /* EMC_WDV_MASK */
-                       0x00000005, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000002, /* EMC_EINPUT */
-                       0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000002, /* EMC_QRST */
-                       0x0000000e, /* EMC_QSAFE */
-                       0x0000000e, /* EMC_RDV */
-                       0x00000010, /* EMC_RDV_MASK */
-                       0x00000942, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000001, /* EMC_PDEX2WR */
-                       0x00000008, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x0000004d, /* EMC_AR2PDEN */
-                       0x0000000e, /* EMC_RW2PDEN */
-                       0x00000055, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x0000000a, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x00000982, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ4 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ5 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ6 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ7 */
-                       0x10000280, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x01231339, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451420, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x0000009c, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x0171000e, /* EMC_MRS_WAIT_CNT */
-                       0x0171000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x0000d3b3, /* EMC_CFG_PIPE */
-                       0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000009, /* EMC_QPOP */
-                       0x0b000004, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
-                       0x76e50f08, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000005, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000096, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00330049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080039, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff002c, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff0046, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510034, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff0082, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73340000, /* EMC_CFG */
-               0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80000321, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200000, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               2180,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_396000_V01_V5.0.2_V0.3", /* DVFS table version */
-               396000,     /* SDRAM frequency */
-               870,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllc_out0", /* clock source id */
-               0x20000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000011, /* EMC_RC */
-                       0x00000065, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x0000000c, /* EMC_RAS */
-                       0x00000004, /* EMC_RP */
-                       0x00000005, /* EMC_R2W */
-                       0x00000008, /* EMC_W2R */
-                       0x00000002, /* EMC_R2P */
-                       0x0000000a, /* EMC_W2P */
-                       0x00000004, /* EMC_RD_RCD */
-                       0x00000004, /* EMC_WR_RCD */
-                       0x00000002, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000004, /* EMC_WDV */
-                       0x00000004, /* EMC_WDV_MASK */
-                       0x00000007, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000003, /* EMC_EINPUT */
-                       0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00050000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000004, /* EMC_QRST */
-                       0x0000000f, /* EMC_QSAFE */
-                       0x00000010, /* EMC_RDV */
-                       0x00000012, /* EMC_RDV_MASK */
-                       0x00000bd1, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000001, /* EMC_PDEX2WR */
-                       0x00000008, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000063, /* EMC_AR2PDEN */
-                       0x0000000f, /* EMC_RW2PDEN */
-                       0x0000006b, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x0000000d, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000005, /* EMC_TCLKSTABLE */
-                       0x00000005, /* EMC_TCLKSTOP */
-                       0x00000c11, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0x002c00a0, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ4 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ5 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ6 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0123133d, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451420, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x000000c6, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x015b000e, /* EMC_MRS_WAIT_CNT */
-                       0x015b000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x0000d2b3, /* EMC_CFG_PIPE */
-                       0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x0000000b, /* EMC_QPOP */
-                       0x0f000005, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000009, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
-                       0x7586120a, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x0000000a, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x000000be, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00280049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x0008002d, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff0033, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff0022, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff0037, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff0066, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff0038, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73340000, /* EMC_CFG */
-               0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
-               0x002c0068, /* EMC_CFG_DIG_DLL */
-               0x80000521, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200000, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               1750,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_528000_V01_V5.0.2_V0.3", /* DVFS table version */
-               528000,     /* SDRAM frequency */
-               900,        /* min voltage */
-               900,        /* gpu min voltage */
-               "pllm_ud",  /* clock source id */
-               0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000018, /* EMC_RC */
-                       0x00000088, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000010, /* EMC_RAS */
-                       0x00000006, /* EMC_RP */
-                       0x00000006, /* EMC_R2W */
-                       0x00000009, /* EMC_W2R */
-                       0x00000002, /* EMC_R2P */
-                       0x0000000d, /* EMC_W2P */
-                       0x00000006, /* EMC_RD_RCD */
-                       0x00000006, /* EMC_WR_RCD */
-                       0x00000002, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000004, /* EMC_WDV */
-                       0x00000004, /* EMC_WDV_MASK */
-                       0x00000008, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000003, /* EMC_EINPUT */
-                       0x00000007, /* EMC_EINPUT_DURATION */
-                       0x00060000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000004, /* EMC_QRST */
-                       0x0000000e, /* EMC_QSAFE */
-                       0x00000013, /* EMC_RDV */
-                       0x00000015, /* EMC_RDV_MASK */
-                       0x00000fd6, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x0000000b, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x00000084, /* EMC_AR2PDEN */
-                       0x00000012, /* EMC_RW2PDEN */
-                       0x0000008f, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000013, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000006, /* EMC_TCLKSTABLE */
-                       0x00000006, /* EMC_TCLKSTOP */
-                       0x00001017, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe01200b1, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS8 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS9 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS10 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS11 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS12 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS13 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS14 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0123133d, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000c0c, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451420, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0606003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000000, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x013a000e, /* EMC_MRS_WAIT_CNT */
-                       0x013a000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x000052a0, /* EMC_CFG_PIPE */
-                       0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x0000000c, /* EMC_QPOP */
-                       0x0f000007, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
-                       0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x06050202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
-                       0x7428180d, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x0000000d, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x000000fd, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00c10038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00c10038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00c1003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00c10090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00c10041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00c10090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00c10041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00c10080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00c10004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00c10004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080021, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000c1, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00c10004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00c10026, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00c1001a, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00c10024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00c10029, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000c1, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00c100c1, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00c100c1, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00c100c1, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00c100c1, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00c10065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00c1002a, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73300000, /* EMC_CFG */
-               0x00000895, /* EMC_CFG_2 */
-               0x00040128, /* EMC_SEL_DPD_CTRL */
-               0xe0120069, /* EMC_CFG_DIG_DLL */
-               0x80000941, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200008, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_624000_V01_V5.0.2_V0.3", /* DVFS table version */
-               624000,     /* SDRAM frequency */
-               910,        /* min voltage */
-               900,        /* gpu min voltage */
-               "pllm_ud",  /* clock source id */
-               0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x0000001c, /* EMC_RC */
-                       0x000000a1, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000014, /* EMC_RAS */
-                       0x00000007, /* EMC_RP */
-                       0x00000007, /* EMC_R2W */
-                       0x0000000b, /* EMC_W2R */
-                       0x00000003, /* EMC_R2P */
-                       0x00000010, /* EMC_W2P */
-                       0x00000007, /* EMC_RD_RCD */
-                       0x00000007, /* EMC_WR_RCD */
-                       0x00000002, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000005, /* EMC_WDV */
-                       0x00000005, /* EMC_WDV_MASK */
-                       0x0000000a, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000003, /* EMC_EINPUT */
-                       0x0000000b, /* EMC_EINPUT_DURATION */
-                       0x00080000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000002, /* EMC_QRST */
-                       0x00000013, /* EMC_QSAFE */
-                       0x00000016, /* EMC_RDV */
-                       0x00000018, /* EMC_RDV_MASK */
-                       0x000012c3, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000002, /* EMC_PDEX2WR */
-                       0x0000000d, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x0000009c, /* EMC_AR2PDEN */
-                       0x00000015, /* EMC_RW2PDEN */
-                       0x000000a9, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000004, /* EMC_TCKE */
-                       0x00000005, /* EMC_TCKESR */
-                       0x00000004, /* EMC_TPD */
-                       0x00000016, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000007, /* EMC_TCLKSTABLE */
-                       0x00000007, /* EMC_TCLKSTOP */
-                       0x00001304, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00d01b1, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS8 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS9 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS10 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS11 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS12 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS13 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS14 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ0 */
-                       0x007f800e, /* EMC_DLL_XFORM_DQ1 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ2 */
-                       0x007f800e, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0121113d, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x51451420, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
-                       0x0606003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000000, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x0122000e, /* EMC_MRS_WAIT_CNT */
-                       0x0122000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x000040a0, /* EMC_CFG_PIPE */
-                       0x80002617, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x0000000e, /* EMC_QPOP */
-                       0x06000009, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
-                       0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x07050202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
-                       0x736a1d10, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x0000000f, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x0000012b, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00a4003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00a40080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x0008001c, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000a4, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00a40020, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00a40018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00a40024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00a40023, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000a4, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00a40065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00a40024, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73300000, /* EMC_CFG */
-               0x0000089d, /* EMC_CFG_2 */
-               0x00040128, /* EMC_SEL_DPD_CTRL */
-               0xe00d0169, /* EMC_CFG_DIG_DLL */
-               0x80000b61, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200010, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               1230,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_792000_V01_V5.0.2_V0.3", /* DVFS table version */
-               792000,     /* SDRAM frequency */
-               1000,       /* min voltage */
-               1100,       /* gpu min voltage */
-               "pllc_out0", /* clock source id */
-               0x20000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x00000024, /* EMC_RC */
-                       0x000000cc, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x00000019, /* EMC_RAS */
-                       0x0000000a, /* EMC_RP */
-                       0x00000008, /* EMC_R2W */
-                       0x0000000d, /* EMC_W2R */
-                       0x00000004, /* EMC_R2P */
-                       0x00000013, /* EMC_W2P */
-                       0x0000000a, /* EMC_RD_RCD */
-                       0x0000000a, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000006, /* EMC_WDV */
-                       0x00000006, /* EMC_WDV_MASK */
-                       0x0000000b, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x0000000c, /* EMC_EINPUT_DURATION */
-                       0x000a0000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x00000013, /* EMC_QSAFE */
-                       0x00000018, /* EMC_RDV */
-                       0x0000001a, /* EMC_RDV_MASK */
-                       0x000017e2, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000003, /* EMC_PDEX2WR */
-                       0x00000011, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x000000c6, /* EMC_AR2PDEN */
-                       0x00000018, /* EMC_RW2PDEN */
-                       0x000000d6, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000005, /* EMC_TCKE */
-                       0x00000006, /* EMC_TCKESR */
-                       0x00000005, /* EMC_TPD */
-                       0x0000001d, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x00000008, /* EMC_TCLKSTABLE */
-                       0x00000008, /* EMC_TCLKSTOP */
-                       0x00001822, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00701b1, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS8 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS9 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS10 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS11 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS12 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS13 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS14 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0120113d, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000c0c, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x59659600, /* EMC_XM2DQSPADCTRL3 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
-                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x59659600, /* EMC_XM2DQSPADCTRL6 */
-                       0x0606003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000000, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x00f8000e, /* EMC_MRS_WAIT_CNT */
-                       0x00f8000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x000040a0, /* EMC_CFG_PIPE */
-                       0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000010, /* EMC_QPOP */
-                       0x0e00000b, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000013, /* MC_EMEM_ARB_TIMING_RC */
-                       0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x08060202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
-                       0x734c2414, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000013, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x0000017c, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x0081003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00810080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x00000081, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00810004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00810019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00810018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00810024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x0081001c, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x00000081, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00810065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x0081001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73300000, /* EMC_CFG */
-               0x0000089d, /* EMC_CFG_2 */
-               0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0070169, /* EMC_CFG_DIG_DLL */
-               0x80000d71, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200018, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               1200,       /* expected dvfs latency (ns) */
-       },
-       {
-               0x15,       /* V5.0.2 */
-               "01_924000_V01_V5.0.2_V0.3", /* DVFS table version */
-               924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
-               1100,       /* gpu min voltage */
-               "pllm_ud",  /* clock source id */
-               0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
-               31,         /* number of up_down_regs */
-               {
-                       0x0000002b, /* EMC_RC */
-                       0x000000ef, /* EMC_RFC */
-                       0x00000000, /* EMC_RFC_SLR */
-                       0x0000001e, /* EMC_RAS */
-                       0x0000000b, /* EMC_RP */
-                       0x00000009, /* EMC_R2W */
-                       0x0000000f, /* EMC_W2R */
-                       0x00000005, /* EMC_R2P */
-                       0x00000016, /* EMC_W2P */
-                       0x0000000b, /* EMC_RD_RCD */
-                       0x0000000b, /* EMC_WR_RCD */
-                       0x00000004, /* EMC_RRD */
-                       0x00000002, /* EMC_REXT */
-                       0x00000000, /* EMC_WEXT */
-                       0x00000007, /* EMC_WDV */
-                       0x00000007, /* EMC_WDV_MASK */
-                       0x0000000e, /* EMC_QUSE */
-                       0x00000002, /* EMC_QUSE_WIDTH */
-                       0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x0000000e, /* EMC_EINPUT_DURATION */
-                       0x000c0000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_PUTERM_ADJ */
-                       0x00000000, /* EMC_CDB_CNTL_1 */
-                       0x00000000, /* EMC_CDB_CNTL_2 */
-                       0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x00000015, /* EMC_QSAFE */
-                       0x0000001b, /* EMC_RDV */
-                       0x0000001d, /* EMC_RDV_MASK */
-                       0x00001be7, /* EMC_REFRESH */
-                       0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */
-                       0x00000004, /* EMC_PDEX2WR */
-                       0x00000015, /* EMC_PDEX2RD */
-                       0x00000001, /* EMC_PCHG2PDEN */
-                       0x00000000, /* EMC_ACT2PDEN */
-                       0x000000e6, /* EMC_AR2PDEN */
-                       0x0000001b, /* EMC_RW2PDEN */
-                       0x000000fa, /* EMC_TXSR */
-                       0x00000200, /* EMC_TXSRDLL */
-                       0x00000006, /* EMC_TCKE */
-                       0x00000007, /* EMC_TCKESR */
-                       0x00000006, /* EMC_TPD */
-                       0x00000022, /* EMC_TFAW */
-                       0x00000000, /* EMC_TRPAB */
-                       0x0000000a, /* EMC_TCLKSTABLE */
-                       0x0000000a, /* EMC_TCLKSTOP */
-                       0x00001c28, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
-                       0x00000000, /* EMC_ODT_WRITE */
-                       0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00401b1, /* EMC_CFG_DIG_DLL */
-                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS0 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS1 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS2 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS3 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS4 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS5 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS6 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS7 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS8 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS9 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS10 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS11 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS12 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS13 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS14 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS15 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ0 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ1 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ2 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
-                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
-                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0120113d, /* EMC_XM2DQSPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL2 */
-                       0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
-                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
-                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x5d75d720, /* EMC_XM2DQSPADCTRL3 */
-                       0x00492492, /* EMC_XM2DQSPADCTRL4 */
-                       0x00492492, /* EMC_XM2DQSPADCTRL5 */
-                       0x5d75d700, /* EMC_XM2DQSPADCTRL6 */
-                       0x0606003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x00000000, /* EMC_TXDSRVTTGEN */
-                       0x00000000, /* EMC_FBIO_SPARE */
-                       0x00020000, /* EMC_ZCAL_INTERVAL */
-                       0x00000128, /* EMC_ZCAL_WAIT_CNT */
-                       0x00ce000e, /* EMC_MRS_WAIT_CNT */
-                       0x00ce000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x00004080, /* EMC_CFG_PIPE */
-                       0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000012, /* EMC_QPOP */
-                       0x0e00000d, /* MC_EMEM_ARB_CFG */
-                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000016, /* MC_EMEM_ARB_TIMING_RC */
-                       0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-                       0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
-                       0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x09060202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
-                       0x734e2a17, /* MC_EMEM_ARB_MISC0 */
-                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-               },
-               {
-                       0x00000017, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x000001bb, /* MC_PTSA_GRANT_DECREMENT */
-                       0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x006e003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x006e0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x0000006e, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x006e0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x006e0019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x006e0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x006e0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x006e001b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x0000006e, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x006e0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x006e001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-               },
-               0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */
-               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-               0x00000802, /* EMC_CTT_TERM_CTRL */
-               0x73300000, /* EMC_CFG */
-               0x0000089d, /* EMC_CFG_2 */
-               0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0040169, /* EMC_CFG_DIG_DLL */
-               0x80000f15, /* Mode Register 0 */
-               0x80100002, /* Mode Register 1 */
-               0x80200020, /* Mode Register 2 */
-               0x00000000, /* Mode Register 4 */
-               1180,       /* expected dvfs latency (ns) */
-       },
-};
-
-static struct tegra12_emc_table loki_b00_emc_table[] = {
-       {
-               0x16,       /* NoRegCalcVersion */
-               "05_12750_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_12750_01_V5.0.6_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -2761,7 +58,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -2880,9 +176,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -2947,6 +240,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -2954,14 +251,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_20400_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_20400_01_V5.0.6_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -2987,7 +284,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3106,9 +402,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3173,6 +466,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -3180,14 +477,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_40800_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_40800_01_V5.0.6_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -3213,7 +510,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3332,9 +628,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3399,6 +692,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -3406,14 +703,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_68000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_68000_01_V5.0.6_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -3439,7 +736,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3558,9 +854,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3625,6 +918,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -3632,14 +929,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_102000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_102000_01_V5.0.6_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -3665,7 +962,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3784,9 +1080,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3851,6 +1144,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -3858,14 +1155,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_204000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_204000_01_V5.0.6_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -3891,7 +1188,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4010,9 +1306,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4077,6 +1370,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -4084,14 +1381,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_300000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_300000_01_V5.0.6_V0.8", /* DVFS table version */
                300000,     /* SDRAM frequency */
-               800,        /* min voltage */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000000c, /* EMC_RC */
@@ -4117,7 +1414,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4236,9 +1532,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4303,6 +1596,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -4310,14 +1607,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                2680,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_396000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_396000_01_V5.0.6_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
+               860,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_out0", /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -4343,7 +1640,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4462,9 +1758,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4529,6 +1822,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x0000088d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -4536,14 +1833,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_528000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_528000_01_V5.0.6_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000017, /* EMC_RC */
@@ -4569,7 +1866,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4688,9 +1984,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
@@ -4755,6 +2048,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x00000895, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe0120069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -4762,14 +2059,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_600000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_600000_01_V5.0.6_V0.8", /* DVFS table version */
                600000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllc_ud",  /* clock source id */
                0xe0000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000001a, /* EMC_RC */
@@ -4795,7 +2092,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000b, /* EMC_EINPUT_DURATION */
                        0x00070000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4914,9 +2210,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -4981,6 +2274,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe00e0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
@@ -4988,14 +2285,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_792000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_792000_01_V5.0.6_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000023, /* EMC_RC */
@@ -5021,7 +2318,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000d, /* EMC_EINPUT_DURATION */
                        0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5140,9 +2436,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -5207,6 +2500,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0070069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
@@ -5214,14 +2511,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_924000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_924000_01_V5.0.6_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000029, /* EMC_RC */
@@ -5247,7 +2544,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000f, /* EMC_EINPUT_DURATION */
                        0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5366,9 +2662,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
@@ -5433,6 +2726,10 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0040069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
@@ -5443,14 +2740,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
 
 static struct tegra12_emc_table thor_195_b00_emc_table[] = {
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_12750_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_12750_01_V5.0.6_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -5476,7 +2773,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5595,9 +2891,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -5662,6 +2955,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -5669,14 +2966,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_20400_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_20400_01_V5.0.6_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -5702,7 +2999,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5821,9 +3117,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -5888,6 +3181,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -5895,14 +3192,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_40800_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_40800_01_V5.0.6_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -5928,7 +3225,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6047,9 +3343,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6114,6 +3407,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -6121,14 +3418,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_68000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_68000_01_V5.0.6_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -6154,7 +3451,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6273,9 +3569,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6340,6 +3633,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -6347,14 +3644,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_102000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_102000_01_V5.0.6_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -6380,7 +3677,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6499,9 +3795,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6566,6 +3859,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -6573,14 +3870,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_204000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_204000_01_V5.0.6_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -6606,7 +3903,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6725,9 +4021,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -6792,6 +4085,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -6799,14 +4096,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_300000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_300000_01_V5.0.6_V0.8", /* DVFS table version */
                300000,     /* SDRAM frequency */
-               800,        /* min voltage */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000000c, /* EMC_RC */
@@ -6832,7 +4129,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6951,9 +4247,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -7018,6 +4311,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -7025,14 +4322,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                2680,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_396000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_396000_01_V5.0.6_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
+               860,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_out0", /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -7058,7 +4355,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7177,9 +4473,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -7244,6 +4537,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000088d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -7251,14 +4548,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_528000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_528000_01_V5.0.6_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000017, /* EMC_RC */
@@ -7284,7 +4581,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7403,9 +4699,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
@@ -7470,6 +4763,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x00000895, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe0120069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -7477,14 +4774,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_600000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_600000_01_V5.0.6_V0.8", /* DVFS table version */
                600000,     /* SDRAM frequency */
-               910,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000001a, /* EMC_RC */
@@ -7510,7 +4807,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000b, /* EMC_EINPUT_DURATION */
                        0x00070000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7629,9 +4925,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -7696,22 +4989,25 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe00e0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
                1440,       /* expected dvfs latency (ns) */
-
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_792000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_792000_01_V5.0.6_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000023, /* EMC_RC */
@@ -7737,7 +5033,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000d, /* EMC_EINPUT_DURATION */
                        0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7856,9 +5151,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -7923,6 +5215,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0070069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
@@ -7930,14 +5226,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_924000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_924000_01_V5.0.6_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000029, /* EMC_RC */
@@ -7963,7 +5259,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000f, /* EMC_EINPUT_DURATION */
                        0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8082,9 +5377,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
@@ -8149,6 +5441,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0040069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
@@ -8156,14 +5452,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                1180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "03_1056000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_1056000_01_V5.0.6_V0.8", /* DVFS table version */
                1056000,    /* SDRAM frequency */
                1100,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000002f, /* EMC_RC */
@@ -8189,7 +5485,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000010, /* EMC_EINPUT_DURATION */
                        0x000b0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8308,9 +5603,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000152, /* EMC_ZCAL_WAIT_CNT */
                        0x00a30010, /* EMC_MRS_WAIT_CNT */
                        0x00a30010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                        0x0000000a, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00000000, /* EMC_CFG_PIPE */
@@ -8375,6 +5667,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008a5, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xd0010069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000125, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200028, /* Mode Register 2 */
@@ -8385,14 +5681,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
 
 static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_12750_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_12750_01_V5.0.9_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -8418,7 +5714,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8537,9 +5832,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000f2f3, /* EMC_CFG_PIPE */
@@ -8604,6 +5896,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -8611,14 +5907,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_20400_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_20400_01_V5.0.9_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -8644,7 +5940,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8763,9 +6058,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000f2f3, /* EMC_CFG_PIPE */
@@ -8830,6 +6122,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -8837,14 +6133,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_40800_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_40800_01_V5.0.9_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -8870,7 +6166,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8989,9 +6284,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000f2f3, /* EMC_CFG_PIPE */
@@ -9056,6 +6348,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -9063,14 +6359,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_68000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_68000_01_V5.0.9_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -9096,7 +6392,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -9215,9 +6510,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000f2f3, /* EMC_CFG_PIPE */
@@ -9282,6 +6574,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -9289,14 +6585,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_102000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_102000_01_V5.0.9_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -9322,7 +6618,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -9441,9 +6736,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000f2f3, /* EMC_CFG_PIPE */
@@ -9508,6 +6800,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -9515,14 +6811,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_204000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_204000_01_V5.0.9_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -9548,7 +6844,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -9667,9 +6962,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT */
                        0x00110011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d2b3, /* EMC_CFG_PIPE */
@@ -9734,6 +7026,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -9741,14 +7037,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_300000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_300000_01_V5.0.9_V0.8", /* DVFS table version */
                300000,     /* SDRAM frequency */
-               800,        /* min voltage */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000000c, /* EMC_RC */
@@ -9774,7 +7070,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -9832,11 +7127,11 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -9893,9 +7188,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01740011, /* EMC_MRS_WAIT_CNT */
                        0x01740011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -9960,6 +7252,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -9967,14 +7263,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                2680,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_396000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_396000_01_V5.0.9_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
+               860,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_out0", /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -10000,7 +7296,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -10058,11 +7353,11 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00078000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00078000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00078000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00078000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -10119,9 +7414,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x015b0011, /* EMC_MRS_WAIT_CNT */
                        0x015b0011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -10186,6 +7478,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x0000088d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
@@ -10193,14 +7489,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_528000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_528000_01_V5.0.9_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000017, /* EMC_RC */
@@ -10226,7 +7522,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -10260,22 +7555,22 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x1040b098, /* EMC_FBIO_CFG5 */
                        0xe01d00b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS8 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS9 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS10 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS11 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS12 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS13 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS14 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -10314,14 +7609,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000e, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -10345,9 +7640,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x013a0011, /* EMC_MRS_WAIT_CNT */
                        0x013a0011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
@@ -10412,6 +7704,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x00000895, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe01d0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
@@ -10419,14 +7715,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_600000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_600000_01_V5.0.9_V0.8", /* DVFS table version */
                600000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllc_ud",  /* clock source id */
                0xe0000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000001a, /* EMC_RC */
@@ -10452,7 +7748,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x0000000b, /* EMC_EINPUT_DURATION */
                        0x00070000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -10486,22 +7781,22 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x1040b098, /* EMC_FBIO_CFG5 */
                        0xe01900b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS8 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS9 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS10 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS11 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS12 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS13 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS14 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -10540,14 +7835,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -10571,9 +7866,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01280011, /* EMC_MRS_WAIT_CNT */
                        0x01280011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -10638,6 +7930,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe0190069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
@@ -10645,14 +7941,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_792000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_792000_01_V5.0.9_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000023, /* EMC_RC */
@@ -10678,7 +7974,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x0000000d, /* EMC_EINPUT_DURATION */
                        0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -10712,22 +8007,22 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x1040b098, /* EMC_FBIO_CFG5 */
                        0xe01100b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS8 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS9 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS10 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS11 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS12 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS13 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS14 */
-                       0x00000008, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -10766,14 +8061,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -10797,9 +8092,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00f80011, /* EMC_MRS_WAIT_CNT */
                        0x00f80011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -10864,6 +8156,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0110069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
@@ -10871,14 +8167,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_924000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_924000_01_V5.0.9_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000029, /* EMC_RC */
@@ -10904,7 +8200,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x0000000f, /* EMC_EINPUT_DURATION */
                        0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -10938,22 +8233,22 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x1040b898, /* EMC_FBIO_CFG5 */
                        0xe00d00b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS8 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS9 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS10 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS11 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS12 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS13 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS14 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000006, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -10992,14 +8287,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000c, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -11023,9 +8318,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
                        0x00ce0011, /* EMC_MRS_WAIT_CNT */
                        0x00ce0011, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
@@ -11090,6 +8382,10 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe00d0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
@@ -11097,14 +8393,14 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                1180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_1056000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.9 */
+               "05_1056000_01_V5.0.9_V0.8", /* DVFS table version */
                1056000,    /* SDRAM frequency */
                1100,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000002f, /* EMC_RC */
@@ -11130,7 +8426,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000010, /* EMC_EINPUT_DURATION */
                        0x000b0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -11249,9 +8544,6 @@ static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
                        0x00000152, /* EMC_ZCAL_WAIT_CNT */
                        0x00a30011, /* EMC_MRS_WAIT_CNT */
                        0x00a30011, /* EMC_MRS_WAIT_CNT2 */
-                       0x06060606, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000606, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x0000000a, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00000000, /* EMC_CFG_PIPE */
@@