ARM: tegra: Get cluster ID by reading MPIDR
Bo Yan [Sat, 15 Dec 2012 22:53:50 +0000 (14:53 -0800)]
This is to avoid MMIO access, thus save a few processor cycles.

Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/171656
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/pm.h

index 18011e2..cc2c27e 100644 (file)
@@ -192,8 +192,8 @@ __invalidate_cpu_state:
        /* fall through */
 #else
        /*      This is only needed for cluster 0 with integrated L2 cache */
-       mov32   r0, TEGRA_FLOW_CTRL_BASE+0x2c   @ CLUSTER_CONTROL
-       ldr     r0, [r0]
+       mrc     p15, 0, r0, c0, c0, 5
+       ubfx    r0, r0, #8, #4
        tst     r0, #1
        bne     __enable_i_cache_branch_pred
        mrc     p15, 0x1, r0, c9, c0, 2
index 8be42e0..3a2b719 100644 (file)
@@ -94,9 +94,6 @@ bool tegra_set_cpu_in_pd(int cpu);
 
 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags);
 
-#define FLOW_CTRL_CLUSTER_CONTROL \
-       (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
-
 #define FLOW_CTRL_CPU_PWR_CSR \
        (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38)
 #define FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE      1
@@ -149,8 +146,12 @@ static inline bool is_g_cluster_present(void)
 static inline unsigned int is_lp_cluster(void)
 {
        unsigned int reg;
-       reg = readl(FLOW_CTRL_CLUSTER_CONTROL);
-       return (reg & 1); /* 0 == G, 1 == LP*/
+       asm("mrc        p15, 0, %0, c0, c0, 5\n"
+           "ubfx       %0, %0, #8, #4"
+           : "=r" (reg)
+           :
+           : "cc");
+       return reg ; /* 0 == G, 1 == LP*/
 }
 int tegra_cluster_control(unsigned int us, unsigned int flags);
 void tegra_cluster_switch_prolog(unsigned int flags);