Added cl_dvfs clock requirement for PWR_I2C through
platform data.
Bug
1234556
Change-Id: I59bf9fcf5364b44050df610c12e6aef519b25047
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/201709
(cherry picked from commit
f78ad10003cbea807b354393f5523c738253ecbc)
Reviewed-on: http://git-master/r/206943
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
.bus_clk_rate = 400000,
.scl_gpio = TEGRA_GPIO_I2C5_SCL,
.sda_gpio = TEGRA_GPIO_I2C5_SDA,
+ .needs_cl_dvfs_clock = true,
};
#endif
.bus_clk_rate = 400000,
.scl_gpio = TEGRA_GPIO_I2C5_SCL,
.sda_gpio = TEGRA_GPIO_I2C5_SDA,
+ .needs_cl_dvfs_clock = true,
};
static struct i2c_board_info __initdata rt5640_board_info = {
.bus_clk_rate = 400000,
.scl_gpio = TEGRA_GPIO_I2C5_SCL,
.sda_gpio = TEGRA_GPIO_I2C5_SDA,
+ .needs_cl_dvfs_clock = true,
};
static struct aic3262_gpio_setup aic3262_gpio[] = {
.bus_clk_rate = 400000,
.scl_gpio = TEGRA_GPIO_I2C5_SCL,
.sda_gpio = TEGRA_GPIO_I2C5_SDA,
+ .needs_cl_dvfs_clock = true,
};
#if defined(CONFIG_ARCH_TEGRA_11x_SOC)