ARM: tegra11: Disable d-cache before power gating
Bo Yan [Wed, 25 Apr 2012 01:18:24 +0000 (18:18 -0700)]
For Cortex A15, the power down sequence requires D cache be
disabled before flushing cache and power gating the CPU.

bug 971396

Change-Id: I15c169c82780022877a0a49aa6403a9e5fd9d83f
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/98581
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R9af0f0af47ebb7260215b314cb958098a029183c

arch/arm/mach-tegra/hotplug.c

index f91c84c..7d8bf51 100644 (file)
@@ -42,8 +42,24 @@ void tegra_cpu_die(unsigned int cpu)
        cpu = cpu_logical_map(cpu);
 
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+       unsigned int r;
+#endif
+
        /* Disable GIC CPU interface for this CPU. */
        tegra_gic_cpu_disable(false);
+
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+       /* disable cache */
+       asm volatile(
+       "       mrc p15, 0, %0, c1, c0, 0\n"
+       "       bic %0, %0, #0x4         \n"
+       "       mcr p15, 0, %0, c1, c0, 0\n"
+       : "=r" (r)
+       : "r" (r)
+       : "cc"
+       );
+#endif
 #endif
 
        /* Flush the L1 data cache. */