ARM: Build fix after Tegra14 K3.4 merge
Kaz Fukuoka [Fri, 13 Jul 2012 01:20:17 +0000 (18:20 -0700)]
Change-Id: I174273877fd6500dffd10cce0dd4737f85765cdb
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/116282
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

13 files changed:
arch/arm/kernel/sleep.S
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board.h
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/include/mach/pinmux-t14.h
arch/arm/mach-tegra/include/mach/pinmux.h
arch/arm/mach-tegra/include/mach/powergate.h
arch/arm/mach-tegra/pinmux-t14-tables.c
arch/arm/mach-tegra/pinmux.c
arch/arm/mach-tegra/timer.c
drivers/video/tegra/host/Makefile
include/linux/nvmap.h

index 987dcf3..99ce1d8 100644 (file)
@@ -64,6 +64,15 @@ ENTRY(cpu_resume_mmu)
        mov     r0, r0
        mov     pc, r3                  @ jump to virtual address
 ENDPROC(cpu_resume_mmu)
+       .ltorg
+       .align  5
+cpu_resume_turn_mmu_on:
+       mcr     p15, 0, r1, c1, c0, 0   @ turn on MMU, I-cache, etc
+       mrc     p15, 0, r1, c0, c0, 0   @ read id reg
+       mov     r1, r1
+       mov     r1, r1
+       mov     pc, r3                  @ jump to virtual address
+ENDPROC(cpu_resume_turn_mmu_on)
        .popsection
 cpu_resume_after_mmu:
        bl      cpu_init                @ restore the und/abt/irq banked regs
index 2be732b..a9584f4 100644 (file)
@@ -70,7 +70,7 @@ obj-$(CONFIG_TEGRA_FIQ_DEBUGGER)        += tegra_fiq_debugger.o
 obj-$(CONFIG_TEGRA_ARB_SEMAPHORE)       += arb_sema.o
 obj-y                                   += dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_11x_SOC)        += tegra11_dvfs.o
-obj-$(CONFIG_ARCH_TEGRA_14x_SOC)        += tegra14_dvfs.o
+obj-$(CONFIG_ARCH_TEGRA_14x_SOC)        += tegra11_dvfs.o
 ifeq ($(CONFIG_TEGRA_SILICON_PLATFORM),y)
 obj-$(CONFIG_TEGRA_LATENCY_ALLOWANCE)   += latency_allowance.o
 obj-$(CONFIG_TEGRA_EDP_LIMITS)          += edp.o
index 55d417c..a3cea24 100644 (file)
@@ -89,6 +89,7 @@ void tegra_assert_system_reset(char mode, const char *cmd);
 void __init tegra20_init_early(void);
 void __init tegra30_init_early(void);
 void __init tegra11x_init_early(void);
+void __init tegra14x_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_dt_init_irq(void);
 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
index 8c93a6f..34678e9 100644 (file)
@@ -276,6 +276,67 @@ static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
        { NULL,         NULL,           0,              0},
 };
 #endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "clk_m",      NULL,           0,              true },
+       { "emc",        NULL,           0,              true },
+       { "cpu",        NULL,           0,              true },
+       { "kfuse",      NULL,           0,              true },
+       { "fuse",       NULL,           0,              true },
+       { "sclk",       NULL,           0,              true },
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
+       { "pll_p",      NULL,           0,              true },
+       { "pll_p_out1", "pll_p",        0,              false },
+       { "pll_p_out3", "pll_p",        0,              true },
+       { "pll_m_out1", "pll_m",        275000000,      false },
+       { "pll_p_out2",  "pll_p",       102000000,      false },
+       { "sclk",        "pll_p_out2",  102000000,      true },
+       { "pll_p_out4",  "pll_p",       204000000,      true },
+       { "host1x",     "pll_p",        102000000,      false },
+       { "cl_dvfs_ref", "pll_p",       54000000,       false },
+       { "cl_dvfs_soc", "pll_p",       54000000,       false },
+#else
+       { "pll_p",      NULL,           0,              true },
+       { "pll_p_out1", "pll_p",        0,              false },
+       { "pll_p_out3", "pll_p",        0,              true },
+       { "pll_m_out1", "pll_m",        275000000,      true },
+       { "pll_p_out2", "pll_p",        108000000,      false },
+       { "sclk",       "pll_p_out2",   108000000,      true },
+       { "pll_p_out4", "pll_p",        216000000,      true },
+       { "host1x",     "pll_p",        108000000,      false },
+       { "cl_dvfs_ref", "clk_m",       13000000,       false },
+       { "cl_dvfs_soc", "clk_m",       13000000,       false },
+       { "hclk",       "sclk",         108000000,      true },
+       { "pclk",       "hclk",         54000000,       true },
+       { "wake.sclk",  NULL,           250000000,      true },
+       { "mselect",    "pll_p",        108000000,      true },
+#endif
+#ifdef CONFIG_TEGRA_SLOW_CSITE
+       { "csite",      "clk_m",        1000000,        true },
+#else
+       { "csite",      NULL,           0,              true },
+#endif
+       { "pll_u",      NULL,           480000000,      false },
+       { "sdmmc1",     "pll_p",        48000000,       false},
+       { "sdmmc3",     "pll_p",        48000000,       false},
+       { "sdmmc4",     "pll_p",        48000000,       false},
+       { "sbc1.sclk",  NULL,           40000000,       false},
+       { "sbc2.sclk",  NULL,           40000000,       false},
+       { "sbc3.sclk",  NULL,           40000000,       false},
+       { "sbc4.sclk",  NULL,           40000000,       false},
+       { "sbc5.sclk",  NULL,           40000000,       false},
+       { "sbc6.sclk",  NULL,           40000000,       false},
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+       { "c2bus",      "pll_c2",       300000000,      false },
+       { "c3bus",      "pll_c3",       300000000,      false },
+#else
+       { "cbus",       "pll_c",        416000000,      false },
+       { "pll_c_out1", "pll_c",        208000000,      false },
+#endif
+       { NULL,         NULL,           0,              0},
+};
+#endif
 
 #ifdef CONFIG_CACHE_L2X0
 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
@@ -663,6 +724,29 @@ void __init tegra11x_init_early(void)
        init_dma_coherent_pool_size(SZ_1M);
 }
 #endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+void __init tegra14x_init_early(void)
+{
+#ifndef CONFIG_SMP
+       /* For SMP system, initializing the reset handler here is too
+          late. For non-SMP systems, the function that calls the reset
+          handler initializer is not called, so do it here for non-SMP. */
+       tegra_cpu_reset_handler_init();
+#endif
+       tegra_init_fuse();
+       tegra11x_init_clocks(); /* using Tegra11x for now */
+       tegra11x_init_dvfs(); /* using Tegra11x for now */
+       tegra_common_init_clock();
+       tegra_clk_init_from_table(tegra14x_clk_init_table);
+       tegra_init_cache(true);
+       tegra_pmc_init();
+       tegra_powergate_init();
+       tegra_init_power();
+       tegra_init_ahb_gizmo_settings();
+       tegra_init_debug_uart_rate();
+       tegra_gpio_resume_init();
+}
+#endif
 static int __init tegra_lp0_vec_arg(char *options)
 {
        char *p = options;
index 568a1a5..cff41bb 100644 (file)
@@ -167,6 +167,8 @@ struct platform_device tegra_pinmux_device = {
        .name           = "tegra20-pinmux-ctl",
 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
        .name           = "tegra11x-pinmux-ctl",
+#elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
+       .name           = "tegra14x-pinmux",
 #endif
        .id             = -1,
        .resource       = pinmux_resource,
index 35086b2..566105e 100644 (file)
@@ -19,6 +19,8 @@
 
 #define TEGRA_PINMUX_HAS_IO_DIRECTION  1
 
+void tegra14x_default_pinmux(void);
+
 enum tegra_pingroup {
        TEGRA_PINGROUP_SDMMC1_CLK,
        TEGRA_PINGROUP_SDMMC1_CMD,
index b229546..40b5c6a 100644 (file)
@@ -484,6 +484,10 @@ void tegra11x_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max,
        const int **gpiomap, int *gpiomap_max);
 
+void tegra14x_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+       const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max,
+       const int **gpiomap, int *gpiomap_max);
+
 int tegra_pinmux_get_func(int pg);
 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
 int tegra_pinmux_set_io(int pg, enum tegra_pin_io input);
index 6cd7f69..88a3d96 100644 (file)
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_POWERGATE_H_
 #define _MACH_TEGRA_POWERGATE_H_
 
+#include <linux/init.h>
+
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 #define TEGRA_POWERGATE_CPU0   0
 #else
index 86fc97f..a3a2b7b 100644 (file)
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/syscore_ops.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-t14.h>
 #include "gpio-names.h"
 #include "iomap.h"
 
@@ -38,39 +41,67 @@ static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 #define PMC_IO_DPD_REQ_0       0x1B8
 #define PMC_IO_DPD2_REQ_0      0x1C0
 
-#define DRIVE_PINGROUP(pg_name, r)             \
-       [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
-               .name = #pg_name,               \
-               .reg = r                        \
+#define PINGROUP_REG_A 0x868
+#define MUXCTL_REG_A   0x3000
+
+#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask,     \
+       slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask)     \
+       [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
+               .name = #pg_name,                               \
+               .reg_bank = 0,                                  \
+               .reg = ((r) - PINGROUP_REG_A),                  \
+               .drvup_offset = drv_up_offset,                  \
+               .drvup_mask = drv_up_mask,                      \
+               .drvdown_offset = drv_down_offset,              \
+               .drvdown_mask = drv_down_mask,                  \
+               .slewrise_offset = slew_rise_offset,            \
+               .slewrise_mask = slew_rise_mask,                \
+               .slewfall_offset = slew_fall_offset,            \
+               .slewfall_mask = slew_fall_mask,                \
+       }
+
+#define DEFAULT_DRIVE_PINGROUP(pg_name, r)             \
+       [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {          \
+               .name = #pg_name,                       \
+               .reg_bank = 0,                          \
+               .reg = ((r) - PINGROUP_REG_A),          \
+               .drvup_offset = 20,                     \
+               .drvup_mask = 0x1f,                     \
+               .drvdown_offset = 12,                   \
+               .drvdown_mask = 0x1f,                   \
+               .slewrise_offset = 28,                  \
+               .slewrise_mask = 0x3,                   \
+               .slewfall_offset = 30,                  \
+               .slewfall_mask = 0x3,                   \
        }
 
 const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-       DRIVE_PINGROUP(AO1,             0x868),
-       DRIVE_PINGROUP(AO2,             0x86c),
-       DRIVE_PINGROUP(CDEV1,           0x884),
-       DRIVE_PINGROUP(CDEV2,           0x888),
-       DRIVE_PINGROUP(CSUS,            0x88c),
-       DRIVE_PINGROUP(DAP1,            0x890),
-       DRIVE_PINGROUP(DAP2,            0x894),
-       DRIVE_PINGROUP(DBG,             0x8a0),
-       DRIVE_PINGROUP(SDIO3,           0x8b0),
-       DRIVE_PINGROUP(UART2,           0x8c0),
-       DRIVE_PINGROUP(UART3,           0x8c4),
-       DRIVE_PINGROUP(PAD,             0x8e8),
-       DRIVE_PINGROUP(SDIO1,           0x8ec),
-       DRIVE_PINGROUP(DDC,             0x8fc),
-       DRIVE_PINGROUP(GMA,             0x900),
-       DRIVE_PINGROUP(GME,             0x910),
-       DRIVE_PINGROUP(OWR,             0x920),
-       DRIVE_PINGROUP(CEC,             0x938),
-       DRIVE_PINGROUP(DAP5,            0x998),
-       DRIVE_PINGROUP(DMIC0,           0x9a0),
-       DRIVE_PINGROUP(DMIC1,           0x9a4),
-       DRIVE_PINGROUP(AO3,             0x9a8),
-       DRIVE_PINGROUP(SPI2,            0x9ac),
-       DRIVE_PINGROUP(AO0,             0x9b0),
-       DRIVE_PINGROUP(DCA,             0x9b8),
-       DRIVE_PINGROUP(SPI3,            0x9bc),
+       DEFAULT_DRIVE_PINGROUP(AO1,             0x868),
+       DEFAULT_DRIVE_PINGROUP(AO2,             0x86c),
+       DEFAULT_DRIVE_PINGROUP(CDEV1,           0x884),
+       DEFAULT_DRIVE_PINGROUP(CDEV2,           0x888),
+       DEFAULT_DRIVE_PINGROUP(CSUS,            0x88c),
+       DEFAULT_DRIVE_PINGROUP(DAP1,            0x890),
+       DEFAULT_DRIVE_PINGROUP(DAP2,            0x894),
+       DEFAULT_DRIVE_PINGROUP(DBG,             0x8a0),
+       DEFAULT_DRIVE_PINGROUP(SDIO3,           0x8b0),
+       DEFAULT_DRIVE_PINGROUP(UART2,           0x8c0),
+       DEFAULT_DRIVE_PINGROUP(UART3,           0x8c4),
+       DEFAULT_DRIVE_PINGROUP(PAD,             0x8e8),
+       DEFAULT_DRIVE_PINGROUP(SDIO1,           0x8ec),
+       DEFAULT_DRIVE_PINGROUP(DDC,             0x8fc),
+       DEFAULT_DRIVE_PINGROUP(GMA,             0x900),
+       DEFAULT_DRIVE_PINGROUP(GME,             0x910),
+       DEFAULT_DRIVE_PINGROUP(OWR,             0x920),
+       DEFAULT_DRIVE_PINGROUP(CEC,             0x938),
+       DEFAULT_DRIVE_PINGROUP(DAP5,            0x998),
+       DEFAULT_DRIVE_PINGROUP(DMIC0,           0x9a0),
+       DEFAULT_DRIVE_PINGROUP(DMIC1,           0x9a4),
+       DEFAULT_DRIVE_PINGROUP(AO3,             0x9a8),
+       DEFAULT_DRIVE_PINGROUP(SPI2,            0x9ac),
+       DEFAULT_DRIVE_PINGROUP(AO0,             0x9b0),
+       DEFAULT_DRIVE_PINGROUP(DCA,             0x9b8),
+       DEFAULT_DRIVE_PINGROUP(SPI3,            0x9bc),
 
 };
 
@@ -84,12 +115,16 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                        TEGRA_MUX_ ## f2,                       \
                        TEGRA_MUX_ ## f3,                       \
                },                                              \
+               .gpionr = TEGRA_GPIO_ ## gpio_nr,               \
                .func_safe = TEGRA_MUX_ ## fs,                  \
-               .tri_reg = reg,                                 \
+               .tri_bank = 1,                                  \
+               .tri_reg = ((reg) - MUXCTL_REG_A),              \
                .tri_bit = 4,                                   \
-               .mux_reg = reg,                                 \
+               .mux_bank = 1,                                  \
+               .mux_reg = ((reg) - MUXCTL_REG_A),              \
                .mux_bit = 0,                                   \
-               .pupd_reg = reg,                                \
+               .pupd_bank = 1,                                 \
+               .pupd_reg = ((reg) - MUXCTL_REG_A),             \
                .pupd_bit = 2,                                  \
                .io_default = TEGRA_PIN_ ## iod,                \
                .od_bit = 6,                                    \
@@ -98,7 +133,6 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        }
 
 /* !!!FIXME!!! FILL IN fSafe COLUMN IN TABLE ....... */
-
 #define PINGROUPS      \
        /*       NAME             GPIO          VDD         f0          f1          f2          f3           fSafe       io     reg */\
        PINGROUP(SDMMC1_CLK,      PA0,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3048),\
@@ -245,36 +279,43 @@ const int gpio_to_pingroup[TEGRA_MAX_GPIO] = {
 
 };
 
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_##_hsm,                        \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,            \
+               .drive = TEGRA_DRIVE_##_drive,                  \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,        \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,       \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
+static __initdata struct tegra_drive_pingroup_config t14x_def_drive_pinmux[] = {
+};
+
 #ifdef CONFIG_PM_SLEEP
 
 static u32 pinmux_reg[TEGRA_MAX_PINGROUP +
                      ARRAY_SIZE(tegra_soc_drive_pingroups)];
 
-static inline unsigned long pg_readl(unsigned long offset)
-{
-       return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
-}
-
-static inline void pg_writel(unsigned long value, unsigned long offset)
-{
-       writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
-}
-
-static int tegra_pinmux_suspend(void)
+static int tegra14x_pinmux_suspend(void)
 {
        unsigned int i;
        u32 *ctx = pinmux_reg;
 
        for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
-               *ctx++ = pg_readl(tegra_soc_pingroups[i].mux_reg);
+               *ctx++ = pg_readl(tegra_soc_pingroups[i].mux_bank,
+                               tegra_soc_pingroups[i].mux_reg);
 
        for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
-               *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg);
+               *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg_bank,
+                               tegra_soc_drive_pingroups[i].reg);
 
        return 0;
 }
 
-static void tegra_pinmux_resume(void)
+static void tegra14x_pinmux_resume(void)
 {
        unsigned int i;
        u32 *ctx = pinmux_reg;
@@ -284,29 +325,46 @@ static void tegra_pinmux_resume(void)
        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
                reg_value = *tmp++;
                reg_value |= TRISTATE;
-               pg_writel(reg_value, tegra_soc_pingroups[i].mux_reg);
+               pg_writel(reg_value, tegra_soc_pingroups[i].mux_bank,
+                       tegra_soc_pingroups[i].mux_reg);
        }
 
        writel(0x400fffff, pmc + PMC_IO_DPD_REQ_0);
        writel(0x40001fff, pmc + PMC_IO_DPD2_REQ_0);
 
        for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
-               pg_writel(*ctx++, tegra_soc_pingroups[i].mux_reg);
+               pg_writel(*ctx++, tegra_soc_pingroups[i].mux_bank,
+                       tegra_soc_pingroups[i].mux_reg);
 
        for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
-               pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg);
+               pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg_bank,
+                       tegra_soc_drive_pingroups[i].reg);
 }
 
-static struct syscore_ops tegra_pinmux_syscore_ops = {
-       .suspend = tegra_pinmux_suspend,
-       .resume = tegra_pinmux_resume,
+static struct syscore_ops tegra14x_pinmux_syscore_ops = {
+       .suspend = tegra14x_pinmux_suspend,
+       .resume = tegra14x_pinmux_resume,
 };
 #endif
 
-void __init tegra_init_pinmux(void)
+void __devinit tegra14x_pinmux_init(const struct tegra_pingroup_desc **pg,
+               int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+               int *pgdrive_max, const int **gpiomap, int *gpiomap_max)
 {
+       *pg = tegra_soc_pingroups;
+       *pg_max = TEGRA_MAX_PINGROUP;
+       *pgdrive = tegra_soc_drive_pingroups;
+       *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+       *gpiomap = gpio_to_pingroup;
+       *gpiomap_max = TEGRA_MAX_GPIO;
+
 #ifdef CONFIG_PM_SLEEP
-       register_syscore_ops(&tegra_pinmux_syscore_ops);
+       register_syscore_ops(&tegra14x_pinmux_syscore_ops);
 #endif
+}
 
+void tegra14x_default_pinmux(void)
+{
+       tegra_drive_pinmux_config_table(t14x_def_drive_pinmux,
+                                       ARRAY_SIZE(t14x_def_drive_pinmux));
 }
index 78bb0a8..eaae009 100644 (file)
@@ -982,6 +982,9 @@ static struct of_device_id tegra_pinmux_of_match[] = {
 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
        { .compatible = "nvidia,tegra11x-pinmux-ctl", tegra11x_pinmux_init },
 #endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+       { .compatible = "nvidia,tegra14x-pinmux", tegra14x_pinmux_init },
+#endif
        { },
 };
 
@@ -1085,6 +1088,10 @@ static struct platform_device_id __devinitdata tegra_pinmux_id[] = {
        { .name = "tegra11x-pinmux-ctl",
          .driver_data = (kernel_ulong_t)tegra11x_pinmux_init, },
 #endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+       { .name = "tegra14x-pinmux",
+         .driver_data = (kernel_ulong_t)tegra14x_pinmux_init, },
+#endif
        {},
 };
 
index 0665498..540d1ed 100644 (file)
@@ -275,6 +275,8 @@ static void __init tegra_init_late_timer(void)
 #define tegra_twd_get_state    do {} while(0)
 #define tegra_twd_suspend      do {} while(0)
 #define tegra_twd_resume       do {} while(0)
+void __init tegra_cpu_timer_init(void) {}
+static void __init tegra_init_late_timer(void) {}
 #endif
 
 #ifdef CONFIG_ARM_ARCH_TIMER
index 2a8b414..5e456e4 100644 (file)
@@ -29,7 +29,6 @@ obj-$(CONFIG_TEGRA_GRHOST) += t114/
 obj-$(CONFIG_TEGRA_GRHOST) += t148/
 obj-$(CONFIG_TEGRA_GRHOST) += msenc/
 obj-$(CONFIG_TEGRA_GRHOST) += tsec/
-obj-$(CONFIG_TEGRA_GRHOST) += dsi/
 obj-$(CONFIG_TEGRA_GRHOST) += nvhost.o
 
 obj-$(CONFIG_TEGRA_GRHOST_USE_NVMAP) += nvmap.o
index 12949e7..1c9aa18 100644 (file)
@@ -148,6 +148,9 @@ int nvmap_pin_array(struct nvmap_client *client,
                struct nvmap_handle_ref **unique_arr_refs);
 
 
+struct nvmap_handle_ref *nvmap_duplicate_handle_id(struct nvmap_client *client,
+                                                  unsigned long id);
+
 struct nvmap_platform_carveout {
        const char *name;
        unsigned int usage_mask;