tegra21: emc: Only poll single rank for PD
Alex Waterman [Fri, 28 Apr 2017 00:31:22 +0000 (01:31 +0100)]
Only poll the single active rank for power-down status when checking if
the DRAM has left auto power-down state and there's only a single rank
of DRAM.

Bug 1906919

Change-Id: I5bc8c926e03268785425b337780e5720414342de
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1471775
Tested-by: David Dastous St Hilaire <ddastoussthi@nvidia.com>
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: David Dastous St Hilaire <ddastoussthi@nvidia.com>
(cherry picked from commit fdb38b913a0eda8dbb545528192e542fcdd37199)
Reviewed-on: http://git-master/r/1471830
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>

drivers/platform/tegra/mc/tegra21_emc_cc_r21021.c

index 460e68a..94f2950 100644 (file)
@@ -507,6 +507,7 @@ u32 __do_periodic_emc_compensation_r21021(
        };
        u32 items = ARRAY_SIZE(list);
        u32 emc_cfg_update;
+       u32 pd_mask = EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK;
 
        if (current_timing->periodic_training) {
                channel_mode = !!(current_timing->burst_regs[EMC_FBIO_CFG7_INDEX] &
@@ -530,11 +531,12 @@ u32 __do_periodic_emc_compensation_r21021(
                /* Does emc_timing_update() for above changes. */
                dll_disable(channel_mode);
 
-               wait_for_update(EMC_EMC_STATUS,
-                               EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK, 0, 0);
+               if (dram_dev_num == ONE_RANK)
+                       pd_mask = 0x10;
+
+               wait_for_update(EMC_EMC_STATUS, pd_mask, 0, 0);
                if (channel_mode)
-                       wait_for_update(EMC_EMC_STATUS,
-                               EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK, 0, 1);
+                       wait_for_update(EMC_EMC_STATUS, pd_mask, 0, 1);
 
                wait_for_update(EMC_EMC_STATUS,
                                EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK, 0, 0);
@@ -838,13 +840,16 @@ void emc_set_clock_r21021(struct tegra21_emc_table *next_timing,
        emc_set_shadow_bypass(ASSEMBLY);
 
        if (next_timing->periodic_training) {
+               u32 pd_mask = EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK;
+
                __reset_dram_clktree_values(next_timing);
 
-               wait_for_update(EMC_EMC_STATUS,
-                               EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK, 0, 0);
+               if (dram_dev_num == ONE_RANK)
+                       pd_mask = 0x10;
+
+               wait_for_update(EMC_EMC_STATUS, pd_mask, 0, 0);
                if (channel_mode)
-                       wait_for_update(EMC_EMC_STATUS,
-                               EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK, 0, 1);
+                       wait_for_update(EMC_EMC_STATUS, pd_mask, 0, 1);
 
                wait_for_update(EMC_EMC_STATUS,
                                EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK, 0, 0);