video: tegra: dc: Update eDP code
Chao Xu [Fri, 24 May 2013 22:35:22 +0000 (15:35 -0700)]
Verified on FPGA (bug 1258447).

Change-Id: Ie95880b99f453d57d659579e6f3b9e6aed393190
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242513

drivers/video/tegra/dc/dp.c
drivers/video/tegra/dc/dp.h
drivers/video/tegra/dc/sor.c
drivers/video/tegra/dc/sor.h
drivers/video/tegra/dc/sor_regs.h

index dec8da9..5aa6f90 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dp.c
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  */
 
 
-#include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/fb.h>
 #include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/nvhost.h>
 #include <linux/wait.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
 
-#include <mach/clk.h>
 #include <mach/dc.h>
 #include <mach/fb.h>
+#include <mach/hardware.h>
 
 #include "dp.h"
 #include "sor.h"
 
 
 
-static inline unsigned long tegra_dpaux_readl(struct tegra_dc_dp_data *dp,
-       unsigned long reg)
+static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
 {
        return readl(dp->aux_base + reg * 4);
 }
 
 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
-       unsigned long reg, unsigned long val)
+       u32 reg, u32 val)
 {
        writel(val, dp->aux_base + reg * 4);
 }
 
 
-static unsigned long tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
+static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
        u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
 {
-       unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
-       u32 reg_val = 0;
+       unsigned long   timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
+       u32             reg_val    = 0;
 
        do {
                usleep_range(poll_interval_us, poll_interval_us << 1);
@@ -70,7 +67,7 @@ static unsigned long tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
 }
 
 
-static int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
+static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
 {
        /* According to DP spec, each aux transaction needs to finish
           within 40ms. */
@@ -86,46 +83,13 @@ static int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
 }
 
 
-static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
-{
-       unsigned long reg_val;
-
-       /* clear interrupt */
-       tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
-       /* do not enable interrupt for now. Enable them when Isr in place */
-       tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
-
-       /* Power up aux/hybrid pads */
-       /* TODO: this may not needed for t124 */
-       reg_val = DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP;
-       tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, reg_val);
-
-       /* Put HYBRID PAD in AUX mode */
-       reg_val = tegra_dpaux_readl(dp, DPAUX_HYBRID_PADCTL);
-       reg_val &= ~DPAUX_HYBRID_PADCTL_MODE_I2C;
-       reg_val |= DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE;
-       reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE;
-       reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE;
-       tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, reg_val);
-
-}
-
-static void tegra_dc_dpaux_disable(struct tegra_dc_dp_data *dp)
-{
-       tegra_dpaux_writel(dp, NV_DPCD_SET_POWER,
-               NV_DPCD_SET_POWER_VAL_D3_PWRDWN);
-
-       /* TODO: power down DPAUX_HYBRID_SPARE too? */
-}
-
-
 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
        u32 addr, u8 *data, u32 *size, u32 *aux_stat)
 {
-       int             i;
-       unsigned long   reg_val;
-       u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
-       u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
+       int     i;
+       u32     reg_val;
+       u32     timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+       u32     defer_retries   = DP_AUX_DEFER_MAX_TRIES;
 
        if (*size >= DP_AUX_MAX_BYTES)
                return -EINVAL; /* only write one chunk of data */
@@ -142,24 +106,24 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                return -EINVAL;
        }
 
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
-       *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
-       if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
-               dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
-               return -EFAULT;
+       if (tegra_platform_is_silicon()) {
+               *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+               if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+                       dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
+                       return -EFAULT;
+               }
        }
-#endif
 
        tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
        for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
                tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
-                       (unsigned long)*data);
+                       (u32)*data);
                data += 4;
        }
 
        reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
        reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
-       reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
+       reg_val |= cmd;
        reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
        reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
 
@@ -178,6 +142,10 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 
                *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 
+               /* Ignore I2C errors on fpga */
+               if (tegra_platform_is_fpga())
+                       *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
+
                if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
                        (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
                        (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
@@ -186,9 +154,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                                dev_dbg(&dp->dc->ndev->dev,
                                        "dp: aux write retry (0x%x) -- %d\n",
                                        *aux_stat, timeout_retries);
+                               /* clear the error bits */
+                               tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+                                       *aux_stat);
                                continue;
                        } else {
-                               dev_err(&dp->dc->ndev->dev, "dp: aux write got error (0x%x)\n",
+                               dev_err(&dp->dc->ndev->dev,
+                                       "dp: aux write got error (0x%x)\n",
                                        *aux_stat);
                                return -EFAULT;
                        }
@@ -200,10 +172,14 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                                dev_dbg(&dp->dc->ndev->dev,
                                        "dp: aux write defer (0x%x) -- %d\n",
                                        *aux_stat, defer_retries);
+                               /* clear the error bits */
+                               tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+                                       *aux_stat);
                                continue;
                        } else {
                                dev_err(&dp->dc->ndev->dev,
-                                       "dp: aux write defer exceeds max retries (0x%x)\n",
+                                       "dp: aux write defer exceeds max retries "
+                                       "(0x%x)\n",
                                        *aux_stat);
                                return -EFAULT;
                        }
@@ -252,9 +228,9 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
        u32 addr, u8 *data, u32 *size, u32 *aux_stat)
 {
-       unsigned long   reg_val;
-       u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
-       u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
+       u32     reg_val;
+       u32     timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+       u32     defer_retries   = DP_AUX_DEFER_MAX_TRIES;
 
        if (*size >= DP_AUX_MAX_BYTES)
                return -EINVAL; /* only read one chunk */
@@ -272,19 +248,19 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                return -EINVAL;
        }
 
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
-       *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
-       if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
-               dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
-               return -EFAULT;
+       if (tegra_platform_is_silicon()) {
+               *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+               if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+                       dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
+                       return -EFAULT;
+               }
        }
-#endif
 
        tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
 
        reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
        reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
-       reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
+       reg_val |= cmd;
        reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
        reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
 
@@ -294,7 +270,6 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                        usleep_range(DP_DPCP_RETRY_SLEEP_NS,
                                DP_DPCP_RETRY_SLEEP_NS << 1);
 
-
                reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
                tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
 
@@ -304,6 +279,10 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
 
                *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 
+               /* Ignore I2C errors on fpga */
+               if (tegra_platform_is_fpga())
+                       *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
+
                if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
                        (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
                        (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
@@ -312,9 +291,13 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                                dev_dbg(&dp->dc->ndev->dev,
                                        "dp: aux read retry (0x%x) -- %d\n",
                                        *aux_stat, timeout_retries);
+                               /* clear the error bits */
+                               tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+                                       *aux_stat);
                                continue; /* retry */
                        } else {
-                               dev_err(&dp->dc->ndev->dev, "dp: aux read got error (0x%x)\n",
+                               dev_err(&dp->dc->ndev->dev,
+                                       "dp: aux read got error (0x%x)\n",
                                        *aux_stat);
                                return -EFAULT;
                        }
@@ -326,11 +309,14 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                                dev_dbg(&dp->dc->ndev->dev,
                                        "dp: aux read defer (0x%x) -- %d\n",
                                        *aux_stat, defer_retries);
+                               /* clear the error bits */
+                               tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+                                       *aux_stat);
                                continue;
                        } else {
                                dev_err(&dp->dc->ndev->dev,
-                                       "dp: aux read defer exceeds max retries (0x%x)\n",
-                                       *aux_stat);
+                                       "dp: aux read defer exceeds max retries "
+                                       "(0x%x)\n", *aux_stat);
                                return -EFAULT;
                        }
                }
@@ -345,7 +331,7 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
                                        DPAUX_DP_AUXDATA_READ_W(i));
 
                        *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
-                       memcpy(temp_data, data, *size);
+                       memcpy(data, temp_data, *size);
 
                        return 0;
                } else {
@@ -386,7 +372,7 @@ static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
        return ret;
 }
 
-static inline int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
+static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
        u8 *data_ptr)
 {
        u32 size = 0;
@@ -395,7 +381,7 @@ static inline int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
 
        ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
                cmd, data_ptr, &size, &status);
-       if (!ret)
+       if (ret)
                dev_err(&dp->dc->ndev->dev,
                        "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
                        cmd, status);
@@ -403,7 +389,7 @@ static inline int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
        return ret;
 }
 
-static inline int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
+static int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
        u8 data)
 {
        u32 size = 0;
@@ -412,7 +398,7 @@ static inline int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
 
        ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
                cmd, &data, &size, &status);
-       if (!ret)
+       if (ret)
                dev_err(&dp->dc->ndev->dev,
                        "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
                        cmd, status);
@@ -427,41 +413,128 @@ static inline u64 tegra_div64(u64 dividend, u32 divisor)
 }
 
 
-static int tegra_dc_init_max_link_cfg(struct tegra_dc_dp_data *dp,
-       struct tegra_dc_dp_link_config *cfg)
+#ifdef CONFIG_DEBUG_FS
+static int dbg_dp_show(struct seq_file *s, void *unused)
 {
-       u8     dpcd_data;
-       int    ret;
+       struct tegra_dc_dp_data *dp = s->private;
 
-       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
-                       &dpcd_data));
-       cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
+#define DUMP_REG(a) seq_printf(s, "%-32s  %03x %08x\n",        \
+               #a, a, tegra_dpaux_readl(dp, a))
 
-       cfg->support_enhanced_framing =
-               (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
-               true : false;
+       tegra_dc_io_start(dp->dc);
+       clk_prepare_enable(dp->clk);
 
-       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
-                       &dpcd_data));
-       cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
-               true : false;
+       DUMP_REG(DPAUX_INTR_EN_AUX);
+       DUMP_REG(DPAUX_INTR_AUX);
+       DUMP_REG(DPAUX_DP_AUXADDR);
+       DUMP_REG(DPAUX_DP_AUXCTL);
+       DUMP_REG(DPAUX_DP_AUXSTAT);
+       DUMP_REG(DPAUX_HPD_CONFIG);
+       DUMP_REG(DPAUX_HPD_IRQ_CONFIG);
+       DUMP_REG(DPAUX_DP_AUX_CONFIG);
+       DUMP_REG(DPAUX_HYBRID_PADCTL);
+       DUMP_REG(DPAUX_HYBRID_SPARE);
 
-       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
-                       &cfg->max_link_bw));
+       clk_disable_unprepare(dp->clk);
+       tegra_dc_io_end(dp->dc);
 
-       cfg->bytes_per_pixel = dp->dc->pdata->fb->bits_per_pixel / 8;
+       return 0;
+}
 
-       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
-                       &dpcd_data));
-       cfg->alt_scramber_reset_cap =
-               (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
-               true : false;
-       cfg->only_enhanced_framing =
-               (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
-               true : false;
+static int dbg_dp_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, dbg_dp_show, inode->i_private);
+}
 
-       return 0;
+static const struct file_operations dbg_fops = {
+       .open           = dbg_dp_open,
+       .read           = seq_read,
+       .llseek         = seq_lseek,
+       .release        = single_release,
+};
+
+static struct dentry *dpdir;
+
+static void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
+{
+       struct dentry *retval;
+
+       dpdir = debugfs_create_dir("tegra_dp", NULL);
+       if (!dpdir)
+               return;
+       retval = debugfs_create_file("regs", S_IRUGO, dpdir, dp, &dbg_fops);
+       if (!retval)
+               goto free_out;
+       return;
+free_out:
+       debugfs_remove_recursive(dpdir);
+       dpdir = NULL;
+       return;
 }
+#else
+static inline void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
+{ }
+#endif
+
+static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
+{
+       /* clear interrupt */
+       tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
+       /* do not enable interrupt for now. Enable them when Isr in place */
+       tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
+
+       tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
+               DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
+               DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
+               0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
+               DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
+}
+
+static void tegra_dc_dpaux_disable(struct tegra_dc_dp_data *dp)
+{
+       tegra_dpaux_writel(dp, NV_DPCD_SET_POWER,
+               NV_DPCD_SET_POWER_VAL_D3_PWRDWN);
+
+       /* TODO: power down DPAUX_HYBRID_SPARE too? */
+}
+
+static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
+       const struct tegra_dc_dp_link_config *cfg)
+{
+       BUG_ON(!cfg || !cfg->is_valid);
+
+       dev_info(&dp->dc->ndev->dev, "DP config: cfg_name       cfg_value\n");
+       dev_info(&dp->dc->ndev->dev, "           Lane Count          %d\n",
+               cfg->max_lane_count);
+       dev_info(&dp->dc->ndev->dev, "           SupportEnhancedFraming %s\n",
+               cfg->support_enhanced_framing ? "Y" : "N");
+       dev_info(&dp->dc->ndev->dev, "           Bandwidth           %d\n",
+               cfg->max_link_bw);
+       dev_info(&dp->dc->ndev->dev, "           BPP                 %d\n",
+               cfg->bytes_per_pixel);
+       dev_info(&dp->dc->ndev->dev, "           EnhancedFraming     %s\n\n",
+               cfg->enhanced_framing ? "Y" : "N");
+       dev_info(&dp->dc->ndev->dev, "           Scramble_enabled    %s\n",
+               cfg->scramble_ena ? "Y" : "N");
+       dev_info(&dp->dc->ndev->dev, "           LinkBW              %d\n",
+               cfg->link_bw);
+       dev_info(&dp->dc->ndev->dev, "           lane_count          %d\n",
+               cfg->lane_count);
+       dev_info(&dp->dc->ndev->dev, "           activespolarity     %d\n",
+               cfg->activepolarity);
+       dev_info(&dp->dc->ndev->dev, "           active_count        %d\n",
+               cfg->active_count);
+       dev_info(&dp->dc->ndev->dev, "           tu_size             %d\n",
+               cfg->tu_size);
+       dev_info(&dp->dc->ndev->dev, "           active_frac         %d\n",
+               cfg->active_frac);
+       dev_info(&dp->dc->ndev->dev, "           watermark           %d\n",
+               cfg->watermark);
+       dev_info(&dp->dc->ndev->dev, "           hblank_sym          %d\n",
+               cfg->hblank_sym);
+       dev_info(&dp->dc->ndev->dev, "           vblank_sym          %d\n",
+               cfg->vblank_sym);
+};
 
 static bool tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp,
        struct tegra_dc_dp_link_config *cfg)
@@ -530,7 +603,7 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
                (u64)link_rate * mode->h_active, mode->pclk);
 
        ratio_f = (u64)mode->pclk * cfg->bytes_per_pixel * f;
-       ratio_f /= 8;
+       /* ratio_f /= 8; */
        ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
 
        for (i = 64; i >= 32; --i) {
@@ -611,11 +684,11 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
                cfg->activepolarity, cfg->active_count, cfg->tu_size,
                cfg->active_frac);
 
-       watermark_f = ratio_f * cfg->tu_size * tegra_div64(f - ratio_f, f);
-       cfg->watermark = 2*((cfg->bytes_per_pixel) * f / 8) + watermark_f +
-               (u32)tegra_div64(lowest_neg_error_f, (u32)f) - 1;
+       watermark_f = tegra_div64(ratio_f * cfg->tu_size * (f - ratio_f), f);
+       cfg->watermark = (u32)tegra_div64(watermark_f + lowest_neg_error_f,
+               f) + 2 * cfg->bytes_per_pixel - 1;
        num_symbols_per_line = (mode->h_active * cfg->bytes_per_pixel) /
-               (8 * cfg->lane_count);
+               cfg->lane_count;
        if (cfg->watermark > 30) {
                dev_dbg(&dp->dc->ndev->dev,
                        "dp: sor setting: unable to get a good tusize, "
@@ -635,7 +708,7 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
        /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
        /*                      - 3 * enhanced_framing - Y */
        /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
-       cfg->hblank_sym = tegra_div64((u64)(mode->h_back_porch +
+       cfg->hblank_sym = (int)tegra_div64((u64)(mode->h_back_porch +
                        mode->h_front_porch + mode->h_sync_width - 7)
                * link_rate, mode->pclk)
                - 3 * cfg->enhanced_framing - (12 / cfg->lane_count);
@@ -645,19 +718,68 @@ static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 
 
        /* Refer to dev_disp.ref for more information. */
-       /* # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
-       /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
+       /* # symbols/vblank = ((SetRasterBlankStart.X - */
+       /*                      SetRasterBlankEen.X - 25) * link_clk / pclk) */
        /*                      - Y - 1; */
        /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
-       cfg->vblank_sym = tegra_div64((u64)(mode->v_back_porch +
-                       mode->v_front_porch + mode->v_sync_width - 25)
+       cfg->vblank_sym = (int)tegra_div64((u64)(mode->h_active - 25)
                * link_rate, mode->pclk) - (36 / cfg->lane_count) - 4;
 
        if (cfg->vblank_sym < 0)
                cfg->vblank_sym = 0;
+
+       cfg->is_valid = true;
+       tegra_dc_dp_dump_link_cfg(dp, cfg);
+
        return true;
 }
 
+static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
+       struct tegra_dc_dp_link_config *cfg)
+{
+       u8     dpcd_data;
+       int    ret;
+
+       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
+                       &dpcd_data));
+
+       cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
+
+       cfg->support_enhanced_framing =
+               (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
+               true : false;
+
+       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
+                       &dpcd_data));
+       cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
+               true : false;
+
+       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
+                       &cfg->max_link_bw));
+
+       cfg->bytes_per_pixel = dp->dc->pdata->fb->bits_per_pixel / 8;
+
+       CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
+                       &dpcd_data));
+       cfg->alt_scramber_reset_cap =
+               (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
+               true : false;
+       cfg->only_enhanced_framing =
+               (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
+               true : false;
+
+       if (tegra_platform_is_fpga()) /* hardcoded to 1.62G on fpga */
+               cfg->max_link_bw = SOR_LINK_SPEED_G1_62;
+       cfg->lane_count       = cfg->max_lane_count;
+       cfg->link_bw          = cfg->max_link_bw;
+       cfg->enhanced_framing = cfg->support_enhanced_framing;
+
+       tegra_dc_dp_calc_config(dp, dp->mode, cfg);
+       tegra_dc_dp_dump_link_cfg(dp, cfg);
+
+       return 0;
+}
+
 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
 {
        int ret;
@@ -699,7 +821,6 @@ static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
        tegra_dc_sor_set_lane_count(dp->sor, cfg->lane_count);
 
        /* Also power down lanes that will not be used */
-       return tegra_dc_sor_power_dplanes(dp->sor, cfg->lane_count);
 }
 
 static int tegra_dc_dp_set_lane_config(struct tegra_dc_dp_data *dp,
@@ -1047,7 +1168,7 @@ static int tegra_dc_dp_link_training(struct tegra_dc_dp_data *dp,
 }
 
 static bool tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
-       struct tegra_dc_dp_link_config *cfg)
+       const struct tegra_dc_dp_link_config *cfg)
 {
        u32 lane;
        u8  mask;
@@ -1073,34 +1194,40 @@ static bool tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
 
 
 static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
-       struct tegra_dc_dp_link_config *cfg)
+       const struct tegra_dc_dp_link_config *cfg)
 {
        struct tegra_dc_sor_data *sor = dp->sor;
-       int ret;
+       u8 link_bw;
+       u8 lane_count;
 
+       BUG_ON(!cfg || !cfg->is_valid);
        tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
        tegra_dc_sor_set_lane_count(sor, cfg->lane_count);
 
        /* Send TP1 */
-       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_1, cfg,
-               false);
+       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_1, cfg);
 
        usleep_range(500, 1000);
        /* enable ASSR */
        tegra_dc_dp_set_assr(dp, true);
-       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_2, cfg,
-               true);
+       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_2, cfg);
 
        usleep_range(500, 1000);
-       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_Disabled,
-               cfg, false);
+       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_Disabled, cfg);
+
+       if (!tegra_dc_dp_link_trained(dp, cfg)) {
+               tegra_dc_sor_read_link_config(dp->sor, &link_bw,
+                       &lane_count);
+               dev_info(&dp->dc->ndev->dev,
+                       "Fast link trainging failed, link bw %d, lane # %d\n",
+                       link_bw, lane_count);
+               return -EFAULT;
+       } else
+               dev_dbg(&dp->dc->ndev->dev,
+                       "Fast link trainging succeeded, link bw %d, lane %d\n",
+                       cfg->link_bw, cfg->lane_count);
 
-       ret = tegra_dc_dp_link_trained(dp, cfg);
-       if (!ret) {
-               tegra_dc_sor_read_link_config(dp->sor, &cfg->link_bw,
-                       &cfg->lane_count);
-       }
-       return ret;
+       return 0;
 }
 
 static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
@@ -1125,7 +1252,7 @@ static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
                do {
                        ret = tegra_dc_dp_dpcd_write(dp,
                                NV_DPCD_SET_POWER, dpcd_data);
-               } while ((--retry > 0) && (ret != 0));
+               } while ((--retry > 0) && ret);
                if (ret) {
                        dev_err(&dp->dc->ndev->dev,
                                "dp: Failed to set DP panel power\n");
@@ -1147,13 +1274,13 @@ static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
                dev_err(&dp->dc->ndev->dev, "dp: Failed to set lane count\n");
                return ret;
        }
-       tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_Disabled,
-               cfg, true);
+       tegra_dc_dp_dump_link_cfg(dp, cfg);
+       tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_None, cfg);
 
-       /* Now do the link training */
-       ret = tegra_dc_dp_link_training(dp, cfg);
+       /* Now do the fast link training for eDP */
+       ret = tegra_dc_dp_fast_link_training(dp, cfg);
        if (ret) {
-               dev_dbg(&dp->dc->ndev->dev, "dp: link training failed\n");
+               dev_err(&dp->dc->ndev->dev, "dp: fast link training failed\n");
                return ret;
        }
 
@@ -1184,7 +1311,7 @@ static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
        }
 
        cfg->is_valid = false;
-       memcpy(cfg, &temp_cfg, sizeof(temp_cfg));
+       memcpy(&temp_cfg, cfg, sizeof(temp_cfg));
 
        temp_cfg.link_bw    = temp_cfg.max_link_bw;
        temp_cfg.lane_count = temp_cfg.max_lane_count;
@@ -1192,8 +1319,7 @@ static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
        while (tegra_dc_dp_calc_config(dp, mode, &temp_cfg) &&
                tegra_dp_link_config(dp, &temp_cfg)) {
                /* current link cfg is doable */
-               memcpy(&temp_cfg, cfg, sizeof(temp_cfg));
-               cfg->is_valid = true;
+               memcpy(cfg, &temp_cfg, sizeof(temp_cfg));
 
                /* try to lower the config */
                if (!tegra_dc_dp_lower_config(dp, &temp_cfg))
@@ -1211,10 +1337,10 @@ static void tegra_dc_dp_lt_worker(struct work_struct *work)
        tegra_dc_disable(dp->dc);
 
        if (!dp->link_cfg.is_valid ||
-               !tegra_dp_link_config(dp, &dp->link_cfg)) {
+               tegra_dp_link_config(dp, &dp->link_cfg)) {
                /* If current config is not valid or cannot be trained,
                   needs to re-explore the possilbe config */
-               if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg))
+               if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg))
                        dev_err(&dp->dc->ndev->dev,
                                "dp: failed to init link configuration\n");
                else if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg,
@@ -1273,7 +1399,7 @@ static int tegra_dc_dp_init(struct tegra_dc *dc)
        if (!dp)
                return -ENOMEM;
 
-       res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "dpaux");
+       res = platform_get_resource_byname(dc->ndev, IORESOURCE_MEM, "dpaux");
        if (!res) {
                dev_err(&dc->ndev->dev, "dp: no mem resources for dpaux\n");
                err = -EFAULT;
@@ -1295,7 +1421,7 @@ static int tegra_dc_dp_init(struct tegra_dc *dc)
                goto err_release_resource_reg;
        }
 
-       clk = clk_get(&dc->ndev->dev, "edp");
+       clk = clk_get_sys("dpaux", NULL);
        if (IS_ERR_OR_NULL(clk)) {
                dev_err(&dc->ndev->dev, "dp: dc clock %s.edp unavailable\n",
                        dev_name(&dc->ndev->dev));
@@ -1332,6 +1458,7 @@ static int tegra_dc_dp_init(struct tegra_dc *dc)
        INIT_WORK(&dp->lt_work, tegra_dc_dp_lt_worker);
 
        tegra_dc_set_outdata(dc, dp);
+       tegra_dc_dp_debug_create(dp);
 
        return 0;
 
@@ -1354,16 +1481,23 @@ static void tegra_dc_dp_enable(struct tegra_dc *dc)
        u32    retry;
        int    ret;
 
+       if (!tegra_is_clk_enabled(dp->clk))
+               clk_prepare_enable(dp->clk);
+
        tegra_dc_dpaux_enable(dp);
-       clk_enable(dp->clk);
 
        /* Power on panel */
        tegra_dc_sor_set_panel_power(dp->sor, true);
 
-       /* TODO: power on lanes as well? */
+       if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) {
+               dev_err(&dc->ndev->dev,
+                       "dp: failed to init link configuration\n");
+               goto error_enable;
+       }
 
-       /* Enable backlight -- TODO: need to go through I2C */
+       tegra_dc_sor_enable_dp(dp->sor);
 
+       /* Enable backlight -- TODO: need to go through I2C */
        msleep(DP_LCDVCC_TO_HPD_DELAY_MS);
 
        /* Write power on to DPCD */
@@ -1381,39 +1515,30 @@ static void tegra_dc_dp_enable(struct tegra_dc *dc)
        }
 
        /* Confirm DP is plugging status */
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
-       if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
+       if (tegra_platform_is_silicon() &&
+               !(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
                        DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
                dev_err(&dp->dc->ndev->dev, "dp: could not detect HPD\n");
                return;
        }
-#endif
 
        /* Check DP version */
        if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
                dev_err(&dp->dc->ndev->dev,
                        "dp: failed to read the revision number from sink\n");
 
-       if (!dp->link_cfg.is_valid ||
-               tegra_dc_dp_fast_link_training(dp, &dp->link_cfg)) {
-               /* if valid link config is not ready yet, or current
-                  config cannot be link-trained, try to find the
-                  new minimal config */
-               if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg)) {
-                       dev_err(&dp->dc->ndev->dev,
-                               "dp: failed to init link configuration\n");
-                       return;
-               }
-               if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, dp->mode) ||
-                       tegra_dc_dp_link_training(dp, &dp->link_cfg)) {
-                       dev_err(&dp->dc->ndev->dev,
-                               "dp: Current mode is not possible\n");
-                       return;
-               }
+       if (tegra_dp_link_config(dp, &dp->link_cfg)) {
+               dev_err(&dp->dc->ndev->dev, "dp: Could not setup link\n");
+               return;
        }
 
-       /* enable SOR by programming the watermark/v/hblank_sym etc */
-       tegra_dc_sor_enable_dp(dp->sor);
+       tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, dp->mode);
+
+       mdelay(100);
+       tegra_dc_sor_attach(dp->sor);
+
+error_enable:
+       return;
 }
 
 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
@@ -1444,24 +1569,55 @@ static void tegra_dc_dp_disable(struct tegra_dc *dc)
        /* Make sure the timing meet the eDP specs */
 }
 
+extern struct clk *tegra_get_clock_by_name(const char *name);
+
+static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk)
+{
+       struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
+       struct clk              *sor_clk = dp->sor->sor_clk;
+       struct clk              *parent_clk;
+
+       tegra_dc_sor_setup_clk(dp->sor, clk, false);
+
+       parent_clk = tegra_get_clock_by_name("pll_dp");
+
+       if (clk_get_parent(sor_clk) != parent_clk)
+               clk_set_parent(sor_clk, parent_clk);
+       clk_set_rate(parent_clk, 270000000);
+
+       if (!tegra_is_clk_enabled(parent_clk))
+               clk_prepare_enable(parent_clk);
+
+       return tegra_dc_pclk_round_rate(dc, dp->sor->dc->mode.pclk);
+}
 
 
 static void tegra_dc_dp_suspend(struct tegra_dc *dc)
 {
-       /* TBD */
+       struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
+
+       tegra_dc_dp_disable(dc);
+       dp->suspended = true;
 }
 
 
 static void tegra_dc_dp_resume(struct tegra_dc *dc)
 {
-       /* TBD */
+       struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
+
+       if (!dp->suspended)
+               return;
+       tegra_dc_dp_enable(dc);
 }
 
 struct tegra_dc_out_ops tegra_dc_dp_ops = {
-       .init    = tegra_dc_dp_init,
-       .destroy = tegra_dc_dp_destroy,
-       .enable  = tegra_dc_dp_enable,
-       .disable = tegra_dc_dp_disable,
-       .suspend = tegra_dc_dp_suspend,
-       .resume  = tegra_dc_dp_resume,
+       .init      = tegra_dc_dp_init,
+       .destroy   = tegra_dc_dp_destroy,
+       .enable    = tegra_dc_dp_enable,
+       .disable   = tegra_dc_dp_disable,
+       .suspend   = tegra_dc_dp_suspend,
+       .resume    = tegra_dc_dp_resume,
+       .setup_clk = tegra_dc_dp_setup_clk,
 };
+
+
index e5a72fc..2c46364 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dp.h
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -70,21 +70,24 @@ struct tegra_dc_dp_data {
 
        struct resource                 *aux_base_res;
        void __iomem                    *aux_base;
-       struct clk                      *clk;   /* DC clock */
+       struct clk                      *clk;   /* dpaux clock */
 
        struct work_struct               lt_work;
        u8                               revision;
 
        struct tegra_dc_mode            *mode;
        struct tegra_dc_dp_link_config   link_cfg;
+
+       bool                             suspended;
 };
 
 
 /* DPCD definitions */
 #define NV_DPCD_REV                                    (0x00000000)
-#define NV_DPCD_REV_MAJOR_1                            (0x00000001)
-#define NV_DPCD_REV_MINOR_0                            (0x00000000)
-#define NV_DPCD_REV_MINOR_1                            (0x00000001)
+#define NV_DPCD_REV_MAJOR_SHIFT                                (4)
+#define NV_DPCD_REV_MAJOR_MASK                         (0xf << 4)
+#define NV_DPCD_REV_MINOR_SHIFT                                (0)
+#define NV_DPCD_REV_MINOR_MASK                         (0xf)
 #define NV_DPCD_MAX_LINK_BANDWIDTH                     (0x00000001)
 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS       (0x00000006)
 #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS       (0x0000000a)
@@ -99,25 +102,25 @@ struct tegra_dc_dp_data {
 #define NV_DPCD_MAX_DOWNSPREAD                         (0x00000003)
 #define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE                        (0x00000000)
 #define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT             (0x00000001)
-#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F   (0x00000000)
-#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T   (0x00000001)
+#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F   (0x00000000 << 6)
+#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T   (0x00000001 << 6)
 #define NV_DPCD_EDP_CONFIG_CAP                         (0x0000000D)
 #define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO            (0x00000000)
 #define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES           (0x00000001)
-#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO       (0x00000000)
-#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES      (0x00000001)
+#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO       (0x00000000 << 1)
+#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES      (0x00000001 << 1)
 #define NV_DPCD_LINK_BANDWIDTH_SET                     (0x00000100)
 #define NV_DPCD_LANE_COUNT_SET                         (0x00000101)
-#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F       (0x00000000)
-#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T       (0x00000001)
+#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F       (0x00000000 << 7)
+#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T       (0x00000001 << 7)
 #define NV_DPCD_TRAINING_PATTERN_SET                   (0x00000102)
 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK          0x3
 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE          (0x00000000)
 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1           (0x00000001)
 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2           (0x00000002)
 #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3           (0x00000003)
-#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F     (0x00000000)
-#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T     (0x00000001)
+#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F     (0x00000000 << 5)
+#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T     (0x00000001 << 5)
 #define NV_DPCD_TRAINING_LANE0_SET                     (0x00000103)
 #define NV_DPCD_TRAINING_LANE1_SET                     (0x00000104)
 #define NV_DPCD_TRAINING_LANE2_SET                     (0x00000105)
@@ -127,13 +130,13 @@ struct tegra_dc_dp_data {
 #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT            3
 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T    (0x00000001 << 5)
 #define NV_DPCD_DOWNSPREAD_CTRL                                (0x00000107)
-#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE                (0x00000000)
-#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5      (0x00000001)
+#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE                (0x00000000 << 4)
+#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5      (0x00000001 << 4)
 #define NV_DPCD_EDP_CONFIG_SET                         (0x0000010A)
 #define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE       (0x00000000)
 #define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE                (0x00000001)
-#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE  (0x00000000)
-#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE   (0x00000001)
+#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE  (0x00000000 << 1)
+#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE   (0x00000001 << 1)
 #define NV_DPCD_TRAINING_LANE0_1_SET2                  (0x0000010F)
 #define NV_DPCD_TRAINING_LANE2_3_SET2                  (0x00000110)
 #define NV_DPCD_LANEX_SET2_PC2_SHIFT                   0
index e7fc70d..1ee4da3 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor.c
  *
- * Copyright (c) 2011-2102, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -20,6 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/fb.h>
 #include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
 
 #include <mach/clk.h>
 #include <mach/dc.h>
 #include "sor_regs.h"
 #include "dc_priv.h"
 
+static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
+{
+       u32 reg_val = readl(sor->base + reg * 4);
+       return reg_val;
+}
+
+static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
+       u32 reg, u32 val)
+{
+       writel(val, sor->base + reg * 4);
+}
+
+static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
+       u32 reg, u32 mask, u32 val)
+{
+       u32 reg_val = tegra_sor_readl(sor, reg);
+       reg_val &= ~mask;
+       reg_val |= val;
+       tegra_sor_writel(sor, reg, reg_val);
+}
+
+static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
+       u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
+{
+       unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
+       u32 reg_val = 0;
+
+       do {
+               usleep_range(poll_interval_us, poll_interval_us << 1);
+               reg_val = tegra_sor_readl(sor, reg);
+       } while (((reg_val & mask) != exp_val) &&
+               time_after(timeout_jf, jiffies));
+
+       if ((reg_val & mask) == exp_val)
+               return 0;       /* success */
+       dev_err(&sor->dc->ndev->dev,
+               "sor_poll_register 0x%x: timeout\n", reg);
+       return jiffies - timeout_jf + 1;
+}
+
+
+#ifdef CONFIG_DEBUG_FS
+static int dbg_sor_show(struct seq_file *s, void *unused)
+{
+       struct tegra_dc_sor_data *sor = s->private;
+
+#define DUMP_REG(a) seq_printf(s, "%-32s  %03x  %08x\n",               \
+               #a, a, tegra_sor_readl(sor, a));
+
+       tegra_dc_io_start(sor->dc);
+       clk_prepare_enable(sor->sor_clk);
+
+       DUMP_REG(NV_SOR_SUPER_STATE0);
+       DUMP_REG(NV_SOR_SUPER_STATE1);
+       DUMP_REG(NV_SOR_STATE0);
+       DUMP_REG(NV_SOR_STATE1);
+       DUMP_REG(NV_HEAD_STATE0(0));
+       DUMP_REG(NV_HEAD_STATE0(1));
+       DUMP_REG(NV_HEAD_STATE1(0));
+       DUMP_REG(NV_HEAD_STATE1(1));
+       DUMP_REG(NV_HEAD_STATE2(0));
+       DUMP_REG(NV_HEAD_STATE2(1));
+       DUMP_REG(NV_HEAD_STATE3(0));
+       DUMP_REG(NV_HEAD_STATE3(1));
+       DUMP_REG(NV_HEAD_STATE4(0));
+       DUMP_REG(NV_HEAD_STATE4(1));
+       DUMP_REG(NV_HEAD_STATE5(0));
+       DUMP_REG(NV_HEAD_STATE5(1));
+       DUMP_REG(NV_SOR_CRC_CNTRL);
+       DUMP_REG(NV_SOR_CLK_CNTRL);
+       DUMP_REG(NV_SOR_CAP);
+       DUMP_REG(NV_SOR_PWR);
+       DUMP_REG(NV_SOR_TEST);
+       DUMP_REG(NV_SOR_PLL0);
+       DUMP_REG(NV_SOR_PLL1);
+       DUMP_REG(NV_SOR_PLL2);
+       DUMP_REG(NV_SOR_PLL3);
+       DUMP_REG(NV_SOR_CSTM);
+       DUMP_REG(NV_SOR_LVDS);
+       DUMP_REG(NV_SOR_CRCA);
+       DUMP_REG(NV_SOR_CRCB);
+       DUMP_REG(NV_SOR_SEQ_CTL);
+       DUMP_REG(NV_SOR_LANE_SEQ_CTL);
+       DUMP_REG(NV_SOR_SEQ_INST(0));
+       DUMP_REG(NV_SOR_SEQ_INST(8));
+       DUMP_REG(NV_SOR_PWM_DIV);
+       DUMP_REG(NV_SOR_PWM_CTL);
+       DUMP_REG(NV_SOR_MSCHECK);
+       DUMP_REG(NV_SOR_XBAR_CTRL);
+       DUMP_REG(NV_SOR_DP_LINKCTL(0));
+       DUMP_REG(NV_SOR_DP_LINKCTL(1));
+       DUMP_REG(NV_SOR_DC(0));
+       DUMP_REG(NV_SOR_DC(1));
+       DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0));
+       DUMP_REG(NV_SOR_PR(0));
+       DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
+       DUMP_REG(NV_SOR_DP_CONFIG(0));
+       DUMP_REG(NV_SOR_DP_CONFIG(1));
+       DUMP_REG(NV_SOR_DP_MN(0));
+       DUMP_REG(NV_SOR_DP_MN(1));
+       DUMP_REG(NV_SOR_DP_PADCTL(0));
+       DUMP_REG(NV_SOR_DP_PADCTL(1));
+       DUMP_REG(NV_SOR_DP_DEBUG(0));
+       DUMP_REG(NV_SOR_DP_DEBUG(1));
+       DUMP_REG(NV_SOR_DP_SPARE(0));
+       DUMP_REG(NV_SOR_DP_SPARE(1));
+       DUMP_REG(NV_SOR_DP_TPG);
+
+       clk_disable_unprepare(sor->sor_clk);
+       tegra_dc_io_end(sor->dc);
+
+       return 0;
+}
+
+static int dbg_sor_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, dbg_sor_show, inode->i_private);
+}
+
+static const struct file_operations dbg_fops = {
+       .open           = dbg_sor_open,
+       .read           = seq_read,
+       .llseek         = seq_lseek,
+       .release        = single_release,
+};
+
+static struct dentry *sordir;
+
+static void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor)
+{
+       struct dentry *retval;
+
+       sordir = debugfs_create_dir("tegra_sor", NULL);
+       if (!sordir)
+               return;
+       retval = debugfs_create_file("regs", S_IRUGO, sordir, sor, &dbg_fops);
+       if (!retval)
+               goto free_out;
+       return;
+free_out:
+       debugfs_remove_recursive(sordir);
+       sordir = NULL;
+       return;
+}
+#else
+static inline void tegra_dc_sor_debug_create(struct tegra_dc_sor_data *sor)
+{ }
+#endif
+
 
 struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
        const struct tegra_dc_dp_link_config *cfg)
@@ -45,7 +196,7 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
                goto err_allocate;
        }
 
-       res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "sor");
+       res = platform_get_resource_byname(dc->ndev, IORESOURCE_MEM, "sor");
        if (!res) {
                dev_err(&dc->ndev->dev, "sor: no mem resource\n");
                err = -ENOENT;
@@ -67,7 +218,7 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
                goto err_release_resource_reg;
        }
 
-       clk = clk_get_sys("had2codec", "dpaux");
+       clk = clk_get_sys("sor0", NULL);
        if (IS_ERR_OR_NULL(clk)) {
                dev_err(&dc->ndev->dev, "sor: can't get clock\n");
                err = -ENOENT;
@@ -79,6 +230,9 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
        sor->base_res = base_res;
        sor->sor_clk  = clk;
        sor->link_cfg = cfg;
+       sor->portnum  = 0;
+
+       tegra_dc_sor_debug_create(sor);
 
        return sor;
 
@@ -93,52 +247,11 @@ err_allocate:
        return ERR_PTR(err);
 }
 
-static inline unsigned long tegra_sor_readl(struct tegra_dc_sor_data *sor,
-       unsigned long reg)
-{
-       return readl(sor->base + reg * 4);
-}
-
-static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
-       unsigned long reg, unsigned long val)
-{
-       writel(val, sor->base + reg * 4);
-}
-
-static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
-       unsigned long reg, u32 mask, u32 val)
-{
-       u32 reg_val = tegra_sor_readl(sor, reg);
-       reg_val &= ~mask;
-       reg_val |= val;
-       tegra_sor_writel(sor, reg, reg_val);
-}
-
-static unsigned long tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
-       u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
-{
-       unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
-       u32 reg_val = 0;
-
-       do {
-               usleep_range(poll_interval_us, poll_interval_us << 1);
-               reg_val = tegra_sor_readl(sor, reg);
-       } while (((reg_val & mask) != exp_val) &&
-               time_after(timeout_jf, jiffies));
-
-       if ((reg_val & mask) == exp_val)
-               return 0;       /* success */
-       dev_dbg(&sor->dc->ndev->dev,
-               "sor_poll_register 0x%x: timeout\n", reg);
-       return jiffies - timeout_jf + 1;
-}
-
-
 static int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor,
        int pu_pd)
 {
-       unsigned long reg_val;
-       unsigned long orig_val;
+       u32 reg_val;
+       u32 orig_val;
 
        if (tegra_dc_sor_poll_register(sor, NV_SOR_SEQ_CTL,
                        NV_SOR_SEQ_CTL_STATUS_MASK,
@@ -180,13 +293,11 @@ void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor)
        release_resource(sor->base_res);
        kfree(sor);
 }
-EXPORT_SYMBOL(tegra_dc_sor_destroy);
 
 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
-       u8 training_pattern, const struct tegra_dc_dp_link_config *cfg,
-       bool use_scramble)
+       u8 training_pattern, const struct tegra_dc_dp_link_config *cfg)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
        reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
 
@@ -197,27 +308,30 @@ void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
 
        reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
 
-       /* !!!TODO: fix the scrambler enabling */
-       if (use_scramble)
-               reg_val |= cfg->scramble_ena <<
-                       NV_SOR_DP_LINKCTL_SCRAMBLEREN_SHIFT;
-
        if (cfg->enhanced_framing)
                reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
-       reg_val |= (training_pattern <<
-               NV_SOR_DP_LINKCTL_TRAININGPTTRN_SHIFT);
 
-       tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum),
-               reg_val);
+       tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
+
+       switch (training_pattern) {
+       case trainingPattern_1:
+               tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
+               break;
+       case trainingPattern_2:
+               tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x42424242);
+               break;
+       default:
+               tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
+               break;
+       }
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_dp_linkctl);
 
 void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
        u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu)
 {
-       unsigned long d_cur;
-       unsigned long p_emp;
-       unsigned long p_ctl;
+       u32 d_cur;
+       u32 p_emp;
+       u32 p_ctl;
 
 
        d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum));
@@ -270,25 +384,24 @@ void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
        tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum),
                p_ctl);
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_dp_lanedata);
 
 
 int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
-       u32 lane_count)
+       u32 lane_count, bool pu, bool lvds)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
-       reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)) | 0xf;
+       reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
 
        switch (lane_count) {
        case 4:
-               reg_val &= (NV_SOR_DP_PADCTL_PD_TXD_3_YES |
-                       NV_SOR_DP_PADCTL_PD_TXD_2_YES);
+               reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
+                       NV_SOR_DP_PADCTL_PD_TXD_2_NO);
                /* fall through */
        case 2:
-               reg_val &= NV_SOR_DP_PADCTL_PD_TXD_1_YES;
+               reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
        case 1:
-               reg_val &= NV_SOR_DP_PADCTL_PD_TXD_0_YES;
+               reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
                break;
        default:
                dev_dbg(&sor->dc->ndev->dev,
@@ -297,15 +410,28 @@ int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
        }
 
        tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
+       tegra_dc_sor_set_lane_count(sor, lane_count);
 
        /* SOR lane sequencer */
-       reg_val = tegra_sor_readl(sor, NV_SOR_LANE_SEQ_CTL);
+       if (pu)
+               reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
+                       NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
+                       NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU;
+       else
+               reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
+                       NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP |
+                       NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD;
+
+       if (lvds)
+               reg_val &= ~NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK;
+       else
+               reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
 
-       reg_val |= NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER;
        tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val);
 
        if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
-                       NV_SOR_LANE_SEQ_CTL_SETTING_MASK, 0,
+                       NV_SOR_LANE_SEQ_CTL_SETTING_MASK,
+                       NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE,
                        100, TEGRA_SOR_TIMEOUT_MS)) {
                dev_dbg(&sor->dc->ndev->dev,
                        "dp: timeout while waiting for SOR lane sequencer "
@@ -314,13 +440,12 @@ int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
        }
        return 0;
 }
-EXPORT_SYMBOL(tegra_dc_sor_power_dplanes);
 
 
 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
        bool power_up)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
        /* !!TODO: need to enable panel power through GPIO operations */
        /* Check bug 790854 for HW progress */
@@ -334,7 +459,6 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
 
        tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_panel_power);
 
 
 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
@@ -357,59 +481,38 @@ static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
        const struct tegra_dc_dp_link_config *cfg)
 {
-       unsigned long reg_val;
+       u32 reg_val;
+
+       BUG_ON(!cfg || !cfg->is_valid);
 
        tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
 
-       /* TODO: SOR_NV_PDISP_SOR_REFCL */
-       /* tegra_dc_sor_set_dp_linkctl(sor, true,
-          trainingPattern_Disabled, true); */
-       reg_val = tegra_sor_readl(sor,
-               NV_SOR_DP_CONFIG(sor->portnum));
-       reg_val &= NV_SOR_DP_CONFIG_WATERMARK_MASK;
+       tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_None, cfg);
+       reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
+       reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
        reg_val |= cfg->watermark;
-       reg_val &= NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
+       reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
        reg_val |= (cfg->active_count <<
                NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
-       reg_val &= NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
+       reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
        reg_val |= (cfg->active_frac <<
                NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
        if (cfg->activepolarity)
                reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
        else
                reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
-       reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE;
+       reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
+               NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
+       reg_val = 0x84011713;   /* HACK */
 
-       tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum),
-               reg_val);
+       tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
 
        /* program h/vblank sym */
-       reg_val = tegra_sor_readl(sor,
-               NV_SOR_DP_LINKCTL(sor->portnum));
+       tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
+               NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, cfg->hblank_sym);
 
-       reg_val = cfg->hblank_sym & NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
-       tegra_sor_writel(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
-               reg_val);
-
-       reg_val = cfg->vblank_sym & NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
-       tegra_sor_writel(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
-               reg_val);
-}
-
-static void tegra_dc_sor_poweron(struct tegra_dc_sor_data *sor, u32 vdd_mode)
-{
-       /* enable PLL */
-       tegra_sor_writel(sor, NV_SOR_PLL2,
-               NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
-               NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
-               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE |
-               NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE |
-               NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE |
-               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
-       tegra_sor_writel(sor, NV_SOR_PLL0,
-               NV_SOR_PLL0_VCOPD_RESCIND |
-               NV_SOR_PLL0_PWR_ON);
-       tegra_sor_writel(sor, NV_SOR_PLL3, vdd_mode);
+       tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
+               NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, cfg->vblank_sym);
 }
 
 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
@@ -428,15 +531,15 @@ static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 
 static inline void tegra_dc_sor_enable_sequencer(struct tegra_dc_sor_data *sor)
 {
-       tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum),
+       tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
+               NV_SOR_DP_SPARE_SEQ_ENABLE_YES,
                NV_SOR_DP_SPARE_SEQ_ENABLE_YES);
 
        tegra_sor_writel(sor, NV_SOR_SEQ_CTL,
                (8 << NV_SOR_SEQ_CTL_PD_PC_SHIFT) |
                (8 << NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT));
 
-       tegra_sor_write_field(sor, NV_SOR_LANE_SEQ_CTL,
-               NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK, 0);
+       msleep(100);
 }
 
 static void tegra_dc_sor_sequencer_dp_start(struct tegra_dc_sor_data *sor)
@@ -444,15 +547,36 @@ static void tegra_dc_sor_sequencer_dp_start(struct tegra_dc_sor_data *sor)
        tegra_dc_sor_enable_sequencer(sor);
 
        tegra_sor_writel(sor, NV_SOR_SEQ_INST(0),
+               0 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT |
                NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
                NV_SOR_SEQ_INST_HALT_TRUE |
+               NV_SOR_SEQ_INST_PIN_A_LOW |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
                NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
-               NV_SOR_SEQ_INST_LANE_SEQ_RUN);
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL |
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
+               NV_SOR_SEQ_INST_LANE_SEQ_RUN |
+               NV_SOR_SEQ_INST_SEQUENCE_UP);
 
        tegra_sor_writel(sor, NV_SOR_SEQ_INST(8),
+               0 << NV_SOR_SEQ_INST_WAIT_TIME_SHIFT |
                NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC |
                NV_SOR_SEQ_INST_HALT_TRUE |
+               NV_SOR_SEQ_INST_PIN_A_LOW |
+               NV_SOR_SEQ_INST_PIN_B_LOW |
                NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE |
+               NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS |
+               NV_SOR_SEQ_INST_BLACK_DATA_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_DE_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_H_NORMAL |
+               NV_SOR_SEQ_INST_BLANK_V_NORMAL |
+               NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL |
+               NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL |
                NV_SOR_SEQ_INST_LANE_SEQ_RUN |
                NV_SOR_SEQ_INST_SEQUENCE_DOWN);
 }
@@ -619,7 +743,7 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
        const struct tegra_dc_mode      *dc_mode  = sor->dc->out->modes;
 
        const int       head_num = sor->dc->ndev->id;
-       u32             reg_val  = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
+       u32             reg_val  = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
        u32             vtotal, htotal;
        u32             vsync_end, hsync_end;
        u32             vblank_end, hblank_end;
@@ -628,7 +752,8 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
 
        reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
                NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
-       reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_BOTH;
+       reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
+               NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
 
        for (i = 0; pins && (i < sor->dc->out->n_out_pins); i++) {
                switch (pins[i].name) {
@@ -652,10 +777,15 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
                }
        }
 
-       reg_val |= (sor->dc->pdata->fb->bits_per_pixel > 16) ?
+       reg_val |= (sor->dc->pdata->fb->bits_per_pixel > 18) ?
                NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
                NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
 
+       tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
+
+       /* Skipping programming NV_HEAD_STATE0, assuming:
+          interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
+
        BUG_ON(!dc_mode);
        vtotal = dc_mode->v_sync_width + dc_mode->v_back_porch +
                dc_mode->v_active + dc_mode->v_front_porch;
@@ -675,34 +805,164 @@ static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
                - dc_mode->v_ref_to_sync;
        hblank_end = dc_mode->h_sync_width + dc_mode->h_back_porch
                - dc_mode->h_ref_to_sync;
+       /* Add 1 to vblank. See bug 1021453 */
        tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
-               vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
+               (vblank_end + 1) << NV_HEAD_STATE3_VBLANK_END_SHIFT |
                hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
 
        vblank_start = vblank_end + dc_mode->v_active;
        hblank_start = hblank_end + dc_mode->h_active;
        tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
-               vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
+               (vblank_start + 1) << NV_HEAD_STATE4_VBLANK_START_SHIFT |
                hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
 
-       /* TODO: setup rotclk */
+       /* TODO: adding interlace mode support */
+       tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
+
+       tegra_sor_write_field(sor, NV_SOR_CSTM,
+               NV_SOR_CSTM_ROTCLK_DEFAULT_MASK,
+               2 << NV_SOR_CSTM_ROTCLK_SHIFT);
 
        tegra_dc_sor_config_pwm(sor, 1024, 1024);
 }
 
+static void tegra_dc_sor_enable_clk(struct tegra_dc_sor_data *sor)
+{
+       if (!tegra_is_clk_enabled(sor->sor_clk))
+               clk_prepare_enable(sor->sor_clk);
+}
+
+static void tegra_dc_sor_disable_clk(struct tegra_dc_sor_data *sor)
+{
+       if (tegra_is_clk_enabled(sor->sor_clk))
+               clk_disable_unprepare(sor->sor_clk);
+}
+
+void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor, bool ena)
+{
+       struct tegra_dc         *dc   = sor->dc;
+       struct tegra_dc_mode    *mode = &dc->mode;
+       u32     reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
+
+       const u32 h_pulse = mode->h_sync_width + mode->h_back_porch +
+               mode->h_active + mode->h_front_porch - mode->h_ref_to_sync;
+
+       tegra_dc_sor_enable_clk(sor);
+
+       tegra_dc_writel(dc, reg_val | WRITE_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
+
+       if (tegra_platform_is_fpga()) {
+               tegra_dc_writel(dc, 0, DC_DISP_DISP_CLOCK_CONTROL);
+               tegra_dc_writel(dc, 0xe, DC_DISP_DC_MCCIF_FIFOCTRL);
+       }
+
+       tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
+
+       /* Enable DC */
+       tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
+       tegra_dc_writel(dc, reg_val, DC_CMD_STATE_ACCESS);
+}
+
+static void tegra_dc_sor_attach_lvds(struct tegra_dc_sor_data *sor)
+{
+       /* Set head owner */
+       tegra_sor_write_field(sor, NV_SOR_STATE1,
+               NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK,
+               NV_SOR_STATE1_ASY_SUBOWNER_BOTH);
+
+       tegra_dc_sor_update(sor);
+
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
+                       NV_SOR_TEST_ATTACHED_TRUE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for ATTACHED = TRUE\n");
+               return;
+       }
+
+       /* OR mode: normal */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+       /* then awake */
+       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
+               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
+               NV_SOR_SUPER_STATE1_ATTACHED_YES);
+       tegra_dc_sor_super_update(sor);
+
+}
+
 void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
 {
-       unsigned long reg_val;
+       const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
 
-       tegra_dc_sor_poweron(sor, NV_SOR_PLL3_PLLVDD_MODE_V3_3);
-       tegra_dc_sor_power_dplanes(sor, sor->link_cfg->lane_count);
-       tegra_dc_sor_set_dp_mode(sor, sor->link_cfg);
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
+       usleep_range(20, 100);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL3,
+               NV_SOR_PLL3_PLLVDD_MODE_MASK,
+               NV_SOR_PLL3_PLLVDD_MODE_V3_3);
+       tegra_sor_writel(sor, NV_SOR_PLL0,
+               0xf << NV_SOR_PLL0_ICHPMP_SHFIT |
+               0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
+               NV_SOR_PLL0_PLLREG_LEVEL_V45 |
+               NV_SOR_PLL0_RESISTORSEL_EXT |
+               NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX1_SEQ_MASK |
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+               NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
+       tegra_sor_writel(sor, NV_SOR_PLL1, NV_SOR_PLL1_TERM_COMPOUT_HIGH);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
+                       NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+                       NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
+                       100, TEGRA_SOR_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev, "DP failed to lock PLL\n");
+               return;
+       }
+
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
+               NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
+               NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
+
+       /* Power up lanes */
+       BUG_ON(!cfg || !cfg->is_valid);
+       tegra_dc_sor_power_dplanes(sor, cfg->lane_count, true, false);
+       tegra_dc_sor_set_dp_mode(sor, cfg);
 
        tegra_dc_sor_sequencer_dp_start(sor);
        tegra_dc_sor_set_power_state(sor, 1);
+}
+
+
+void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
+{
+       u32 reg_val;
+
+       tegra_dc_sor_enable_dc(sor, false);
        tegra_dc_sor_config_panel(sor, false);
-       tegra_dc_sor_update(sor);
 
+       tegra_dc_writel(sor->dc, 0x20, DC_CMD_DISPLAY_WINDOW_HEADER);
+       tegra_dc_writel(sor->dc, SOR_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
+
+       /* Attach head */
+       tegra_dc_sor_update(sor);
        reg_val = NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
                NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
                NV_SOR_SUPER_STATE1_ATTACHED_NO;
@@ -720,20 +980,63 @@ void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
                dev_err(&sor->dc->ndev->dev,
                        "dc timeout waiting for ATTACHED = TRUE\n");
        }
+
+       tegra_dc_writel(sor->dc, 0x9f00, DC_CMD_STATE_CONTROL);
+       tegra_dc_writel(sor->dc, 0x9f, DC_CMD_STATE_CONTROL);
+
+       tegra_dc_writel(sor->dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE |
+               PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
+               DC_CMD_DISPLAY_POWER_CONTROL);
+
+       tegra_dc_writel(sor->dc, CRC_ALWAYS_ENABLE |
+               CRC_INPUT_DATA_ACTIVE_DATA | CRC_ENABLE_ENABLE,
+               DC_COM_CRC_CONTROL);
+
+       tegra_dc_writel(sor->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
+       tegra_dc_writel(sor->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
+
+       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+                       NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
+                       NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
+                       100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
+               dev_err(&sor->dc->ndev->dev,
+                       "dc timeout waiting for OPMOD = AWAKE\n");
+       }
 }
-EXPORT_SYMBOL(tegra_dc_sor_enable_dp);
 
-void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor)
+void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
+       bool balanced, bool conforming)
 {
-       tegra_dc_sor_poweron(sor, NV_SOR_PLL3_PLLVDD_MODE_V1_8);
+       u32 reg_val;
+
+       tegra_dc_sor_enable_dc(sor, true);
+
+       /* pclk needs be setup before window is enabled */
        tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
                NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK,
-               NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK);
+               NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK);
+
+       /* TODO: Dassert the PMC unit to power on */
+       usleep_range(5, 30);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK);
+       usleep_range(20, 60);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL3,
+               NV_SOR_PLL3_PLLVDD_MODE_MASK,
+               NV_SOR_PLL3_PLLVDD_MODE_V1_8);
+       tegra_sor_write_field(sor, NV_SOR_PLL0,
+               NV_SOR_PLL0_PWR_MASK, NV_SOR_PLL0_PWR_ON);
+       tegra_sor_write_field(sor, NV_SOR_PLL0,
+               NV_SOR_PLL0_VCOPD_MASK, NV_SOR_PLL0_VCOPD_RESCIND);
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
+       usleep_range(200, 400);
 
-       /* TODO: check if balanced mode is needed
-                check ROTDAT setting */
-       tegra_sor_writel(sor, NV_SOR_LVDS,
-               NV_SOR_LVDS_LINKACTB_DISABLE |
+       reg_val = NV_SOR_LVDS_LINKACTB_DISABLE |
                NV_SOR_LVDS_PD_TXCB_DISABLE |
                NV_SOR_LVDS_PD_TXDB_3_DISABLE |
                NV_SOR_LVDS_PD_TXDB_2_DISABLE |
@@ -741,41 +1044,32 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor)
                NV_SOR_LVDS_PD_TXDB_0_DISABLE |
                NV_SOR_LVDS_PD_TXDA_2_ENABLE |
                NV_SOR_LVDS_PD_TXDA_1_ENABLE |
-               NV_SOR_LVDS_PD_TXDA_0_ENABLE);
+               NV_SOR_LVDS_PD_TXDA_0_ENABLE;
+       if (!conforming && (sor->dc->pdata->fb->bits_per_pixel == 18))
+               reg_val |= (NV_SOR_LVDS_PD_TXDA_3_DISABLE);
 
-       tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
-       tegra_dc_sor_config_panel(sor, true);
-       tegra_dc_sor_update(sor);
+       tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
 
-       /* Attaching */
-       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
-               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
-               NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
-               NV_SOR_SUPER_STATE1_ATTACHED_YES);
-       tegra_dc_sor_super_update(sor);
-
-       if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
-                       NV_SOR_TEST_ATTACHED_DEFAULT_MASK,
-                       NV_SOR_TEST_ATTACHED_TRUE,
-                       100, TEGRA_SOR_TIMEOUT_MS)) {
+       if ((tegra_dc_sor_set_power_state(sor, 1))) {
                dev_err(&sor->dc->ndev->dev,
-                       "dc timeout waiting for ATTACHED = TRUE\n");
+                       "Failed to power up SOR sequencer for LVDS\n");
                return;
        }
 
-       /* OR mode: normal */
-       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
-               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
-               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
-               NV_SOR_SUPER_STATE1_ATTACHED_YES);
-       tegra_dc_sor_super_update(sor);
+       tegra_sor_write_field(sor, NV_SOR_LVDS,
+               NV_SOR_LVDS_BALANCED_DEFAULT_MASK,
+               balanced ? NV_SOR_LVDS_BALANCED_ENABLE :
+               NV_SOR_LVDS_BALANCED_DISABLE);
+       tegra_sor_write_field(sor, NV_SOR_LVDS,
+               NV_SOR_LVDS_ROTDAT_DEFAULT_MASK,
+               conforming ? 6 << NV_SOR_LVDS_ROTDAT_SHIFT :
+               0 << NV_SOR_LVDS_ROTDAT_SHIFT);
 
-       /* then awake */
-       tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
-               NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
-               NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL |
-               NV_SOR_SUPER_STATE1_ATTACHED_YES);
-       tegra_dc_sor_super_update(sor);
+       tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
+
+       tegra_dc_sor_config_panel(sor, true);
+       tegra_dc_sor_update(sor);
+       tegra_dc_sor_attach_lvds(sor);
 
        /* TODO: check if display controller needs to start now*/
        tegra_dc_sor_sequencer_lvds_start(sor);
@@ -789,10 +1083,12 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor)
                return;
        }
 }
-EXPORT_SYMBOL(tegra_dc_sor_enable_lvds);
 
 void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
 {
+       struct tegra_dc *dc = sor->dc;
+       u32    reg_val;
+
        /* #1: safe mode */
        tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
                NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
@@ -850,29 +1146,61 @@ void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
                NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM);
        tegra_dc_sor_update(sor);
 
-       /* TODO: need to program:
-          DISP_WIN_OPTIONS(SOR_DISABLE)
-          DISPLAY_COMMAND(DISPLAY_CTRL_MODE_STOP)
-          DISPLAY_POWER_CONTROL(POWER_ENABLE_DISABLE)
-        */
+       /* stop display2sor_clock */
+       tegra_dc_sor_enable_dc(sor, false);
+
+       /* stop disp controller */
+       reg_val = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
+       reg_val &= ~(DISP_CTRL_MODE_C_DISPLAY | DISP_CTRL_MODE_NC_DISPLAY);
+       tegra_dc_writel(dc, reg_val, DC_CMD_DISPLAY_COMMAND);
+       reg_val = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
+       reg_val &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
+               PW4_ENABLE);
+       tegra_dc_writel(dc, reg_val, DC_CMD_DISPLAY_POWER_CONTROL);
+
+
+       /* TODO: use safe clock */
 
        /* Power down the SOR sequencer */
-       if ((tegra_dc_sor_set_power_state(sor, 0))) {
+       if (tegra_dc_sor_set_power_state(sor, 0)) {
                dev_err(&sor->dc->ndev->dev,
                        "Failed to power down SOR sequencer\n");
                return;
        }
 
        /* Power down DP lanes */
-       if (!is_lvds && tegra_dc_sor_power_dplanes(sor, 0)) {
+       if (!is_lvds && tegra_dc_sor_power_dplanes(sor, 4, false, false)) {
                dev_err(&sor->dc->ndev->dev,
                        "Failed to power down dp lanes\n");
                return;
        }
 
-       clk_disable(sor->sor_clk);
+       /* Power down PDPORT */
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
+               NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE);
+       usleep_range(20, 40);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL0,
+               NV_SOR_PLL0_PWR_MASK | NV_SOR_PLL0_VCOPD_MASK,
+               NV_SOR_PLL0_PWR_OFF | NV_SOR_PLL0_VCOPD_ASSERT);
+       usleep_range(20, 40);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX1_SEQ_MASK |
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+               NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
+               NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
+       usleep_range(20, 40);
+
+       tegra_sor_write_field(sor, NV_SOR_PLL2,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
+               NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE);
+
+       tegra_dc_sor_disable_clk(sor);
+       /* Reset SOR clk */
+       tegra_periph_reset_assert(sor->sor_clk);
 }
-EXPORT_SYMBOL(tegra_dc_sor_disable);
 
 int tegra_dc_sor_set_dp_packet(struct tegra_dc_sor_data *sor,
        u8 *packet)
@@ -885,21 +1213,22 @@ int tegra_dc_sor_set_dp_packet(struct tegra_dc_sor_data *sor,
 
 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, bool is_int)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
        reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum));
        if (is_int)
                reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL;
        else
                reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL;
+
+       reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK;
        tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_internal_panel);
 
 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
                                   u8 *lane_count)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
        reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
        *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
@@ -924,23 +1253,17 @@ void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
                dev_err(&sor->dc->ndev->dev, "Unknown lane count\n");
        }
 }
-EXPORT_SYMBOL(tegra_dc_sor_read_link_config);
 
 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
 {
-       unsigned long reg_val;
-
-       /* FIXME!!! make sure the clk (single/diff dpclk) is programmed */
-       reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
-       reg_val &= ~NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
-       reg_val |= link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
-       tegra_sor_writel(sor, NV_SOR_CLK_CNTRL, reg_val);
+       tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
+               NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
+               link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_link_bandwidth);
 
 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
 {
-       unsigned long reg_val;
+       u32 reg_val;
 
        reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
        reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK;
@@ -962,8 +1285,31 @@ void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
                        lane_count);
                return;
        }
-       reg_val |= (lane_count << NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT);
-       tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum),
-               reg_val);
+       tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
+}
+
+void tegra_dc_sor_setup_clk(struct tegra_dc_sor_data *sor, struct clk *clk,
+       bool is_lvds)
+{
+       struct clk      *parent_clk;
+       struct clk      *base_clk;
+
+       parent_clk = clk_get_sys(NULL, "pll_d2");
+       base_clk   = clk_get_parent(parent_clk);
+
+       if (clk_get_parent(clk) != parent_clk)
+               clk_set_parent(clk, parent_clk);
+
+       if (sor->dc->mode.pclk != clk_get_rate(parent_clk))
+               clk_set_rate(parent_clk, sor->dc->mode.pclk);
+
+       if (!tegra_is_clk_enabled(parent_clk))
+               clk_prepare_enable(parent_clk);
+
+       tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
+
+       tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
+               NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
+               is_lvds ? NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK :
+               NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 }
-EXPORT_SYMBOL(tegra_dc_sor_set_lane_count);
index bb85c07..e375e53 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * drivers/video/tegra/dc/sor.h
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -60,8 +60,8 @@ struct tegra_dc_dp_link_config {
        u32     active_frac;
        u32     watermark;
 
-       u32     hblank_sym;
-       u32     vblank_sym;
+       s32     hblank_sym;
+       s32     vblank_sym;
 };
 
 
@@ -92,7 +92,9 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
 
 void tegra_dc_sor_destroy(struct tegra_dc_sor_data *sor);
 void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor);
-void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
+       bool balanced, bool conforming);
 void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds);
 
 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor,
@@ -106,11 +108,14 @@ void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
        bool power_up);
 void tegra_dc_sor_set_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
        u32 pwm_dutycycle, u32 pwm_clksrc);
-int  tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, u32 lane_count);
+int  tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, u32 lane_count,
+       bool pu, bool lvds);
 void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor,
        u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu);
 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, bool ena,
-       u8 training_pattern, const struct tegra_dc_dp_link_config *cfg,
-       bool use_scramble);
+       u8 training_pattern, const struct tegra_dc_dp_link_config *cfg);
+void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor, bool ena);
+void tegra_dc_sor_setup_clk(struct tegra_dc_sor_data *sor, struct clk *clk,
+       bool is_lvds);
 
 #endif
index 1d95a28..7320a64 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor_regs.h
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -9,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  */
 #define __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
 
 
-#define NV_SOR_SUPER_STATE0                            (0x1)
-#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT               (0)
-#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK         (0x1)
-#define NV_SOR_SUPER_STATE1                            (0x2)
-#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT             (3)
-#define NV_SOR_SUPER_STATE1_ATTACHED_NO                        (0 << 3)
-#define NV_SOR_SUPER_STATE1_ATTACHED_YES               (1 << 3)
-#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT            (2)
-#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE            (0 << 2)
-#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL           (1 << 2)
-#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT           (0)
-#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK    (0x3)
-#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP           (0)
-#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE          (1)
-#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE           (2)
-#define NV_SOR_STATE0                                  (0x3)
-#define NV_SOR_STATE0_UPDATE_SHIFT                     (0)
-#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK              (0x1)
-#define NV_SOR_STATE1                                  (0x4)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT             (17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK       (0xf << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422         (1 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444         (2 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422         (3 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422         (4 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444         (5 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444         (6 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422         (7 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444         (8 << 17)
-#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444         (9 << 17)
-#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT              (15)
-#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK        (0x3 << 15)
-#define NV_SOR_STATE1_ASY_REPLICATE_OFF                        (0 << 15)
-#define NV_SOR_STATE1_ASY_REPLICATE_X2                 (1 << 15)
-#define NV_SOR_STATE1_ASY_REPLICATE_X4                 (2 << 15)
-#define NV_SOR_STATE1_ASY_DEPOL_SHIFT                  (14)
-#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK            (0x1 << 14)
-#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE           (0 << 14)
-#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE           (1 << 14)
-#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT               (13)
-#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK         (0x1 << 13)
-#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE        (0 << 13)
-#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE        (1 << 13)
-#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT               (12)
-#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK         (0x1 << 12)
-#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE        (0 << 12)
-#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE        (1 << 12)
-#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT               (8)
-#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK         (0xf << 8)
-#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM          (0 << 8)
-#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A                        (8 << 8)
-#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B                        (9 << 8)
-#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM              (15 << 8)
-#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT                        (6)
-#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK          (0x3 << 6)
-#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER         (0 << 6)
-#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER       (1 << 6)
-#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER     (2 << 6)
-#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT               (4)
-#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK         (0x3 << 4)
-#define NV_SOR_STATE1_ASY_SUBOWNER_NONE                        (0 << 4)
-#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0            (1 << 4)
-#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1            (2 << 4)
-#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH                        (3 << 4)
-#define NV_SOR_STATE1_ASY_OWNER_SHIFT                  (0)
-#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK            (0xf)
-#define NV_SOR_STATE1_ASY_OWNER_NONE                   (0)
-#define NV_SOR_STATE1_ASY_OWNER_HEAD0                  (1)
-#define NV_SOR_STATE1_ASY_OWNER_HEAD1                  (2)
-#define NV_HEAD_STATE1(i)                              (0x7 + i)
-#define NV_HEAD_STATE1_VTOTAL_SHIFT                    (16)
-#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK             (0x7fff  << 16)
-#define NV_HEAD_STATE1_HTOTAL_SHIFT                    (0)
-#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK             (0x7fff)
-#define NV_HEAD_STATE2(i)                              (0x9 + i)
-#define NV_HEAD_STATE2_VSYNC_END_SHIFT                 (16)
-#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK          (0x7fff << 16)
-#define NV_HEAD_STATE2_HSYNC_END_SHIFT                 (0)
-#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK          (0x7fff)
-#define NV_HEAD_STATE3(i)                              (0xb + i)
-#define NV_HEAD_STATE3_VBLANK_END_SHIFT                        (16)
-#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK          (0x7fff << 16)
-#define NV_HEAD_STATE3_HBLANK_END_SHIFT                        (0)
-#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK          (0x7fff)
-#define NV_HEAD_STATE4(i)                              (0xd + i)
-#define NV_HEAD_STATE4_VBLANK_START_SHIFT              (16)
-#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK        (0x7fff << 16)
-#define NV_HEAD_STATE4_HBLANK_START_SHIFT              (0)
-#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK        (0x7fff)
-#define NV_SOR_CLK_CNTRL                               (0x13)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT              (0)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK               (0x3)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK                (0)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK          (1)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK       (2)
-#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK         (3)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT           (2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK            (0x1f << 2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62           (6 << 2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7            (10 << 2)
-#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS            (7 << 2)
-#define NV_SOR_CAP                                     (0x14)
-#define NV_SOR_CAP_DP_A_SHIFT                          (24)
-#define NV_SOR_CAP_DP_A_DEFAULT_MASK                   (0x1 << 24)
-#define NV_SOR_CAP_DP_A_FALSE                          (0 << 24)
-#define NV_SOR_CAP_DP_A_TRUE                           (1 << 24)
-#define NV_SOR_CAP_DP_B_SHIFT                          (25)
-#define NV_SOR_CAP_DP_B_DEFAULT_MASK                   (0x1 << 24)
-#define NV_SOR_CAP_DP_B_FALSE                          (0 << 24)
-#define NV_SOR_CAP_DP_B_TRUE                           (1 << 24)
-#define NV_SOR_PWR                                     (0x15)
-#define NV_SOR_PWR_SETTING_NEW_SHIFT                   (31)
-#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK            (0x1 << 31)
-#define NV_SOR_PWR_SETTING_NEW_DONE                    (0 << 31)
-#define NV_SOR_PWR_SETTING_NEW_PENDING                 (1 << 31)
-#define NV_SOR_PWR_SETTING_NEW_TRIGGER                 (1 << 31)
-#define NV_SOR_PWR_MODE_SHIFT                          (28)
-#define NV_SOR_PWR_MODE_DEFAULT_MASK                   (0x1 << 28)
-#define NV_SOR_PWR_MODE_NORMAL                         (0 << 28)
-#define NV_SOR_PWR_MODE_SAFE                           (1 << 28)
-#define NV_SOR_PWR_HALT_DELAY_SHIFT                    (24)
-#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK             (0x1 << 24)
-#define NV_SOR_PWR_HALT_DELAY_DONE                     (0 << 24)
-#define NV_SOR_PWR_HALT_DELAY_ACTIVE                   (1 << 24)
-#define NV_SOR_PWR_SAFE_START_SHIFT                    (17)
-#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK             (0x1 << 17)
-#define NV_SOR_PWR_SAFE_START_NORMAL                   (0 << 17)
-#define NV_SOR_PWR_SAFE_START_ALT                      (1 << 17)
-#define NV_SOR_PWR_SAFE_STATE_SHIFT                    (16)
-#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK             (0x1 << 16)
-#define NV_SOR_PWR_SAFE_STATE_PD                       (0 << 16)
-#define NV_SOR_PWR_SAFE_STATE_PU                       (1 << 16)
-#define NV_SOR_PWR_NORMAL_START_SHIFT                  (1)
-#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK           (0x1 << 1)
-#define NV_SOR_PWR_NORMAL_START_NORMAL                 (0 << 16)
-#define NV_SOR_PWR_NORMAL_START_ALT                    (1 << 16)
-#define NV_SOR_PWR_NORMAL_STATE_SHIFT                  (0)
-#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK           (0x1)
-#define NV_SOR_PWR_NORMAL_STATE_PD                     (0)
-#define NV_SOR_PWR_NORMAL_STATE_PU                     (1)
-#define NV_SOR_TEST                                    (0x16)
-#define NV_SOR_TEST_TESTMUX_SHIFT                      (24)
-#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK               (0xff << 24)
-#define NV_SOR_TEST_TESTMUX_AVSS                       (0 << 24)
-#define NV_SOR_TEST_TESTMUX_CLOCKIN                    (2 << 24)
-#define NV_SOR_TEST_TESTMUX_PLL_VOL                    (4 << 24)
-#define NV_SOR_TEST_TESTMUX_SLOWCLKINT                 (8 << 24)
-#define NV_SOR_TEST_TESTMUX_AVDD                       (16 << 24)
-#define NV_SOR_TEST_TESTMUX_VDDREG                     (32 << 24)
-#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG              (64 << 24)
-#define NV_SOR_TEST_TESTMUX_REGREF_AVDD                        (128 << 24)
-#define NV_SOR_TEST_CRC_SHIFT                          (23)
-#define NV_SOR_TEST_CRC_PRE_SERIALIZE                  (0 << 23)
-#define NV_SOR_TEST_CRC_POST_DESERIALIZE               (1 << 23)
-#define NV_SOR_TEST_TPAT_SHIFT                         (20)
-#define NV_SOR_TEST_TPAT_DEFAULT_MASK                  (0x7 << 20)
-#define NV_SOR_TEST_TPAT_LO                            (0 << 20)
-#define NV_SOR_TEST_TPAT_TDAT                          (1 << 20)
-#define NV_SOR_TEST_TPAT_RAMP                          (2 << 20)
-#define NV_SOR_TEST_TPAT_WALK                          (3 << 20)
-#define NV_SOR_TEST_TPAT_MAXSTEP                       (4 << 20)
-#define NV_SOR_TEST_TPAT_MINSTEP                       (5 << 20)
-#define NV_SOR_TEST_DSRC_SHIFT                         (16)
-#define NV_SOR_TEST_DSRC_DEFAULT_MASK                  (0x3 << 16)
-#define NV_SOR_TEST_DSRC_NORMAL                                (0 << 16)
-#define NV_SOR_TEST_DSRC_DEBUG                         (1 << 16)
-#define NV_SOR_TEST_DSRC_TGEN                          (2 << 16)
-#define NV_SOR_TEST_HEAD_NUMBER_SHIFT                  (12)
-#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK            (0x0 << 12)
-#define NV_SOR_TEST_HEAD_NUMBER_NONE                   (0 << 12)
-#define NV_SOR_TEST_HEAD_NUMBER_HEAD0                  (1 << 12)
-#define NV_SOR_TEST_HEAD_NUMBER_HEAD1                  (2 << 12)
-#define NV_SOR_TEST_ATTACHED_SHIFT                     (10)
-#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK              (0x1  << 10)
-#define NV_SOR_TEST_ATTACHED_FALSE                     (0 << 10)
-#define NV_SOR_TEST_ATTACHED_TRUE                      (1 << 10)
-#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT              (8)
-#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK        (0x0 << 8)
-#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP              (0 << 8)
-#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE             (1 << 8)
-#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE              (2 << 8)
-#define NV_SOR_TEST_INVD_SHIFT                         (6)
-#define NV_SOR_TEST_INVD_DISABLE                       (0 << 6)
-#define NV_SOR_TEST_INVD_ENABLE                                (1 << 6)
-#define NV_SOR_TEST_TEST_ENABLE_SHIFT                  (1)
-#define NV_SOR_TEST_TEST_ENABLE_DISABLE                        (0 << 1)
-#define NV_SOR_TEST_TEST_ENABLE_ENABLE                 (1 << 1)
-#define NV_SOR_PLL0                                    (0x17)
-#define NV_SOR_PLL0_PWR_SHIFT                          (0)
-#define NV_SOR_PLL0_PWR_ON                             (0)
-#define NV_SOR_PLL0_PWR_OFF                            (1)
-#define NV_SOR_PLL0_VCOPD_SHIFT                                (2)
-#define NV_SOR_PLL0_VCOPD_RESCIND                      (0 << 2)
-#define NV_SOR_PLL0_VCOPD_ASSERT                       (1 << 2)
-#define NV_SOR_PLL2                                    (0x19)
-#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT               (0)
-#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE            (0 << 0)
-#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW               (1 << 0)
-#define NV_SOR_PLL2_AUX1_SHIFT                         (17)
-#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW            (0 << 17)
-#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE         (1 << 17)
-#define NV_SOR_PLL2_AUX2_SHIFT                         (18)
-#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN            (0 << 18)
-#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN               (1 << 18)
-#define NV_SOR_PLL2_AUX6_SHIFT                         (22)
-#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE     (0 << 22)
-#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE      (1 << 22)
-#define NV_SOR_PLL2_AUX7_SHIFT                         (23)
-#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE                (0 << 23)
-#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE         (1 << 23)
-#define NV_SOR_PLL2_AUX8_SHIFT                         (24)
-#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE  (0 << 24)
-#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE   (1 << 24)
-#define NV_SOR_PLL3                                    (0x1a)
-#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT                  (13)
-#define NV_SOR_PLL3_PLLVDD_MODE_V1_8                   (0 << 13)
-#define NV_SOR_PLL3_PLLVDD_MODE_V3_3                   (1 << 13)
-#define NV_SOR_LVDS                                    (0x1c)
-#define NV_SOR_LVDS_ROTDAT_SHIFT                       (28)
-#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK                        (0x7 << 28)
-#define NV_SOR_LVDS_ROTDAT_RST                         (0 << 28)
-#define NV_SOR_LVDS_ROTCLK_SHIFT                       (24)
-#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK                        (0xf << 24)
-#define NV_SOR_LVDS_ROTCLK_RST                         (0 << 24)
-#define NV_SOR_LVDS_PLLDIV_SHIFT                       (21)
-#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK                        (0x1 << 21)
-#define NV_SOR_LVDS_PLLDIV_BY_7                                (0 << 21)
-#define NV_SOR_LVDS_BALANCED_SHIFT                     (19)
-#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK              (0x1 << 19)
-#define NV_SOR_LVDS_BALANCED_DISABLE                   (0 << 19)
-#define NV_SOR_LVDS_BALANCED_ENABLE                    (1 << 19)
-#define NV_SOR_LVDS_NEW_MODE_SHIFT                     (18)
-#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK              (0x1 << 18)
-#define NV_SOR_LVDS_NEW_MODE_DISABLE                   (0 << 18)
-#define NV_SOR_LVDS_NEW_MODE_ENABLE                    (1 << 18)
-#define NV_SOR_LVDS_DUP_SYNC_SHIFT                     (17)
-#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK              (0x1 << 17)
-#define NV_SOR_LVDS_DUP_SYNC_DISABLE                   (0 << 17)
-#define NV_SOR_LVDS_DUP_SYNC_ENABLE                    (1 << 17)
-#define NV_SOR_LVDS_LVDS_EN_SHIFT                      (16)
-#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK               (0x1 << 16)
-#define NV_SOR_LVDS_LVDS_EN_ENABLE                     (1 << 16)
-#define NV_SOR_LVDS_LINKACTB_SHIFT                     (15)
-#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK              (0x1 << 15)
-#define NV_SOR_LVDS_LINKACTB_DISABLE                   (0 << 15)
-#define NV_SOR_LVDS_LINKACTB_ENABLE                    (1 << 15)
-#define NV_SOR_LVDS_LINKACTA_SHIFT                     (14)
-#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK              (0x1 << 14)
-#define NV_SOR_LVDS_LINKACTA_ENABLE                    (1 << 14)
-#define NV_SOR_LVDS_MODE_SHIFT                         (12)
-#define NV_SOR_LVDS_MODE_DEFAULT_MASK                  (0x3 << 12)
-#define NV_SOR_LVDS_MODE_LVDS                          (0 << 12)
-#define NV_SOR_LVDS_UPPER_SHIFT                                (11)
-#define NV_SOR_LVDS_UPPER_DEFAULT_MASK                 (0x1 << 11)
-#define NV_SOR_LVDS_UPPER_FALSE                                (0 << 11)
-#define NV_SOR_LVDS_UPPER_TRUE                         (1 << 11)
-#define NV_SOR_LVDS_PD_TXCB_SHIFT                      (9)
-#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK               (0x1 << 9)
-#define NV_SOR_LVDS_PD_TXCB_ENABLE                     (0 << 9)
-#define NV_SOR_LVDS_PD_TXCB_DISABLE                    (1 << 9)
-#define NV_SOR_LVDS_PD_TXCA_SHIFT                      (8)
-#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK               (0x1 << 8)
-#define NV_SOR_LVDS_PD_TXCA_ENABLE                     (0 << 8)
-#define NV_SOR_LVDS_PD_TXDB_3_SHIFT                    (7)
-#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK             (0x1 << 7)
-#define NV_SOR_LVDS_PD_TXDB_3_ENABLE                   (0 << 7)
-#define NV_SOR_LVDS_PD_TXDB_3_DISABLE                  (1 << 7)
-#define NV_SOR_LVDS_PD_TXDB_2_SHIFT                    (6)
-#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK             (0x1 << 6)
-#define NV_SOR_LVDS_PD_TXDB_2_ENABLE                   (0 << 6)
-#define NV_SOR_LVDS_PD_TXDB_2_DISABLE                  (1 << 6)
-#define NV_SOR_LVDS_PD_TXDB_1_SHIFT                    (5)
-#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK             (0x1 << 5)
-#define NV_SOR_LVDS_PD_TXDB_1_ENABLE                   (0 << 5)
-#define NV_SOR_LVDS_PD_TXDB_1_DISABLE                  (1 << 5)
-#define NV_SOR_LVDS_PD_TXDB_0_SHIFT                    (4)
-#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK             (0x1 << 4)
-#define NV_SOR_LVDS_PD_TXDB_0_ENABLE                   (0 << 4)
-#define NV_SOR_LVDS_PD_TXDB_0_DISABLE                  (1 << 4)
-#define NV_SOR_LVDS_PD_TXDA_3_SHIFT                    (3)
-#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK             (0x1 << 3)
-#define NV_SOR_LVDS_PD_TXDA_3_ENABLE                   (0 << 3)
-#define NV_SOR_LVDS_PD_TXDA_3_DISABLE                  (1 << 3)
-#define NV_SOR_LVDS_PD_TXDA_2_SHIFT                    (2)
-#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK             (0x1 << 2)
-#define NV_SOR_LVDS_PD_TXDA_2_ENABLE                   (0 << 2)
-#define NV_SOR_LVDS_PD_TXDA_1_SHIFT                    (1)
-#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK             (0x1 << 1)
-#define NV_SOR_LVDS_PD_TXDA_1_ENABLE                   (0 << 1)
-#define NV_SOR_LVDS_PD_TXDA_0_SHIFT                    (0)
-#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK             (0x1)
-#define NV_SOR_LVDS_PD_TXDA_0_ENABLE                   (0)
-#define NV_SOR_SEQ_CTL                                 (0x20)
-#define NV_SOR_SEQ_CTL_SWITCH_SHIFT                    (30)
-#define NV_SOR_SEQ_CTL_SWITCH_MASK                     (0x1 << 30)
-#define NV_SOR_SEQ_CTL_SWITCH_WAIT                     (0 << 30)
-#define NV_SOR_SEQ_CTL_SWITCH_FORCE                    (1 << 30)
-#define NV_SOR_SEQ_CTL_STATUS_SHIFT                    (28)
-#define NV_SOR_SEQ_CTL_STATUS_MASK                     (0x1 << 28)
-#define NV_SOR_SEQ_CTL_STATUS_STOPPED                  (0 << 28)
-#define NV_SOR_SEQ_CTL_STATUS_RUNNING                  (1 << 28)
-#define NV_SOR_SEQ_CTL_PC_SHIFT                                (16)
-#define NV_SOR_SEQ_CTL_PC_MASK                         (0xf << 16)
-#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT                 (12)
-#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK                  (0xf << 12)
-#define NV_SOR_SEQ_CTL_PD_PC_SHIFT                     (8)
-#define NV_SOR_SEQ_CTL_PD_PC_MASK                      (0xf << 8)
-#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT                 (4)
-#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK                  (0xf << 4)
-#define NV_SOR_SEQ_CTL_PU_PC_SHIFT                     (0)
-#define NV_SOR_SEQ_CTL_PU_PC_MASK                      (0xf)
-#define NV_SOR_LANE_SEQ_CTL                            (0x21)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT          (31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK               (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING                (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER                (1 << 31)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT            (28)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE             (0 << 28)
-#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY             (1 << 28)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT             (20)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP                        (0 << 20)
-#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN              (1 << 20)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT      (16)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU         (0 << 16)
-#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD         (1 << 16)
-#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT                        (12)
-#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK         (0xf << 12)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT          (9)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP                (0 << 9)
-#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN      (1 << 9)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT          (8)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP                (0 << 8)
-#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN      (1 << 8)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT          (7)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP                (0 << 7)
-#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN      (1 << 7)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT          (6)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP                (0 << 6)
-#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN      (1 << 6)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT          (5)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP                (0 << 5)
-#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN      (1 << 5)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT          (4)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP                (0 << 4)
-#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN      (1 << 4)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT          (3)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP                (0 << 3)
-#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN      (1 << 3)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT          (2)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP                (0 << 2)
-#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN      (1 << 2)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT          (1)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP                (0 << 1)
-#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN      (1 << 1)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT          (0)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP                (0)
-#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN      (1)
-#define NV_SOR_SEQ_INST(i)                             (0x22 + i)
-#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT             (31)
-#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE           (0 << 31)
-#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE            (1 << 31)
-#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT          (30)
-#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL         (0 << 30)
-#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN      (1 << 30)
-#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT         (29)
-#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL                (0 << 29)
-#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST           (1 << 29)
-#define NV_SOR_SEQ_INST_BLANK_V_SHIFT                  (28)
-#define NV_SOR_SEQ_INST_BLANK_V_NORMAL                 (0 << 28)
-#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE               (1 << 28)
-#define NV_SOR_SEQ_INST_BLANK_H_SHIFT                  (27)
-#define NV_SOR_SEQ_INST_BLANK_H_NORMAL                 (0 << 27)
-#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE               (1 << 27)
-#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT                 (26)
-#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL                        (0 << 26)
-#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE              (1 << 26)
-#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT               (25)
-#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL              (0 << 25)
-#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK               (1 << 25)
-#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT             (24)
-#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS       (0 << 24)
-#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE          (1 << 24)
-#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT         (23)
-#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE         (0 << 23)
-#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE          (1 << 23)
-#define NV_SOR_SEQ_INST_PIN_B_SHIFT                    (22)
-#define NV_SOR_SEQ_INST_PIN_B_LOW                      (0 << 22)
-#define NV_SOR_SEQ_INST_PIN_B_HIGH                     (1 << 22)
-#define NV_SOR_SEQ_INST_PIN_A_SHIFT                    (21)
-#define NV_SOR_SEQ_INST_PIN_A_LOW                      (0 << 21)
-#define NV_SOR_SEQ_INST_PIN_A_HIGH                     (1 << 21)
-#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT                 (19)
-#define NV_SOR_SEQ_INST_SEQUENCE_UP                    (0 << 19)
-#define NV_SOR_SEQ_INST_SEQUENCE_DOWN                  (1 << 19)
-#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT                 (18)
-#define NV_SOR_SEQ_INST_LANE_SEQ_STOP                  (0 << 18)
-#define NV_SOR_SEQ_INST_LANE_SEQ_RUN                   (1 << 18)
-#define NV_SOR_SEQ_INST_PDPORT_SHIFT                   (17)
-#define NV_SOR_SEQ_INST_PDPORT_NO                      (0 << 17)
-#define NV_SOR_SEQ_INST_PDPORT_YES                     (1 << 17)
-#define NV_SOR_SEQ_INST_PDPLL_SHIFT                    (16)
-#define NV_SOR_SEQ_INST_PDPLL_NO                       (0 << 16)
-#define NV_SOR_SEQ_INST_PDPLL_YES                      (1 << 16)
-#define NV_SOR_SEQ_INST_HALT_SHIFT                     (15)
-#define NV_SOR_SEQ_INST_HALT_FALSE                     (0 << 15)
-#define NV_SOR_SEQ_INST_HALT_TRUE                      (1 << 15)
-#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT               (12)
-#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK                (0x3 << 12)
-#define NV_SOR_SEQ_INST_WAIT_UNITS_US                  (0 << 12)
-#define NV_SOR_SEQ_INST_WAIT_UNITS_MS                  (1 << 12)
-#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC               (2 << 12)
-#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT                        (0)
-#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK         (0x3ff)
-#define NV_SOR_PWM_DIV                                 (0x32)
-#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK             (0xffffff)
-#define NV_SOR_PWM_CTL                                 (0x33)
-#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT               (31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_DONE                        (0 << 31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING             (1 << 31)
-#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER             (1 << 31)
-#define NV_SOR_PWM_CTL_CLKSEL_SHIFT                    (30)
-#define NV_SOR_PWM_CTL_CLKSEL_PCLK                     (0 << 30)
-#define NV_SOR_PWM_CTL_CLKSEL_XTAL                     (1 << 30)
-#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT                        (0)
-#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK                 (0xffffff)
-#define NV_SOR_DP_LINKCTL(i)                           (0x4e + (i))
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT                (31)
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO           (0 << 31)
-#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES          (1 << 31)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT                (28)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN    (0 << 28)
-#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE   (1 << 28)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SHIFT          (26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_MASK           (0x3 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN      (0 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_D102           (1 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE     (2 << 26)
-#define NV_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7          (3 << 26)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_SHIFT          (24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_MASK           (0x3 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_NOPATTERN      (0 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING1      (1 << 24)
-#define NV_SOR_DP_LINKCTL_TRAININGPTTRN_TRAINING2      (2 << 24)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_SHIFT          (22)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_DISABLE                (0 << 22)
-#define NV_SOR_DP_LINKCTL_CHANNELCODING_ENABLE         (1 << 22)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT              (16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK               (0x1f << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO               (0 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE                        (1 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO                        (3 << 16)
-#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR               (15 << 16)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT          (14)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                (0 << 14)
-#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE         (1 << 14)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_SHIFT            (12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_MASK             (0x3 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_DISABLE          (0 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_GALIOS    (1 << 12)
-#define NV_SOR_DP_LINKCTL_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT               (10)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE             (0 << 10)
-#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE              (1 << 10)
-#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT                 (2)
-#define NV_SOR_DP_LINKCTL_TUSIZE_MASK                  (0x7f << 2)
-#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT                 (0)
-#define NV_SOR_DP_LINKCTL_ENABLE_NO                    (0)
-#define NV_SOR_DP_LINKCTL_ENABLE_YES                   (1)
-#define NV_SOR_DC(i)                                   (0x50 + (i))
-#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT                 (24)
-#define NV_SOR_DC_LANE3_DP_LANE3_MASK                  (0xff << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0             (17 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0             (21 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0             (26 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0             (34 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1             (26 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1             (32 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1             (39 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2             (34 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2             (43 << 24)
-#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3             (51 << 24)
-#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                 (16)
-#define NV_SOR_DC_LANE2_DP_LANE0_MASK                  (0xff << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0             (17 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0             (21 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0             (26 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0             (34 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1             (26 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1             (32 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1             (39 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2             (34 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2             (43 << 16)
-#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3             (51 << 16)
-#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                 (8)
-#define NV_SOR_DC_LANE1_DP_LANE1_MASK                  (0xff << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0             (17 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0             (21 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0             (26 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0             (34 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1             (26 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1             (32 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1             (39 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2             (34 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2             (43 << 8)
-#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3             (51 << 8)
-#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                 (0)
-#define NV_SOR_DC_LANE0_DP_LANE2_MASK                  (0xff)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0             (17)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0             (21)
-#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0             (26)
-#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0             (34)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1             (26)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1             (32)
-#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1             (39)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2             (34)
-#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2             (43)
-#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3             (51)
-#define NV_SOR_LANE4_DRIVE_CURRENT(i)                  (0x52 + (i))
-#define NV_SOR_PR(i)                                   (0x54 + (i))
-#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                 (24)
-#define NV_SOR_PR_LANE3_DP_LANE3_MASK                  (0xff << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0             (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0             (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0             (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0             (0 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1             (4 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1             (6 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1             (17 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2             (8 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2             (13 << 24)
-#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3             (17 << 24)
-#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT                 (16)
-#define NV_SOR_PR_LANE2_DP_LANE0_MASK                  (0xff << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0             (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0             (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0             (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0             (0 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1             (4 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1             (6 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1             (17 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2             (8 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2             (13 << 16)
-#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3             (17 << 16)
-#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT                 (8)
-#define NV_SOR_PR_LANE1_DP_LANE1_MASK                  (0xff >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0             (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0             (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0             (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0             (0 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1             (4 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1             (6 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1             (17 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2             (8 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2             (13 >> 8)
-#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3             (17 >> 8)
-#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT                 (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_MASK                  (0xff)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0             (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0             (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0             (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0             (0)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1             (4)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1             (6)
-#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1             (17)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2             (8)
-#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2             (13)
-#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3             (17)
-#define NV_SOR_LANE4_PREEMPHASIS(i)                    (0x57 + (i))
-#define NV_SOR_DP_CONFIG(i)                            (0x5a + (i))
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT            (31)
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE         (0 << 31)
-#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE         (1 << 31)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT      (28)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE    (0 << 28)
-#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE     (1 << 28)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT          (26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE                (0 << 26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE         (1 << 26)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT      (24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE   (0 << 24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE   (1 << 24)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT          (16)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK           (0xf << 16)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT         (8)
-#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK          (0x7f << 8)
-#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT               (0)
-#define NV_SOR_DP_CONFIG_WATERMARK_MASK                        (0x3f)
-#define NV_SOR_DP_PADCTL(i)                            (0x5e + (i))
-#define NV_SOR_DP_PADCTL_SPARE_SHIFT                   (25)
-#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK            (0x7f << 25)
-#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT                  (24)
-#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE                        (0 << 24)
-#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE                 (1 << 24)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT              (23)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP            (0 << 23)
-#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN          (1 << 23)
-#define NV_SOR_DP_PADCTL_TX_PU_SHIFT                   (22)
-#define NV_SOR_DP_PADCTL_TX_PU_DISABLE                 (0 << 22)
-#define NV_SOR_DP_PADCTL_TX_PU_ENABLE                  (1 << 22)
-#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT                        (20)
-#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK         (0x3 << 20)
-#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT                 (16)
-#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK          (0xf << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE              (0 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX              (1 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN         (2 << 16)
-#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN       (4 << 16)
-#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT             (8)
-#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK      (0xff << 8)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT   (7)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE  (1 << 7)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT   (6)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE  (1 << 6)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT   (5)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE  (1 << 5)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT   (4)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
-#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE  (1 << 4)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT                        (3)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_YES                  (0 << 3)
-#define NV_SOR_DP_PADCTL_PD_TXD_3_NO                   (1 << 3)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT                        (2)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_YES                  (0 << 2)
-#define NV_SOR_DP_PADCTL_PD_TXD_0_NO                   (1 << 2)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT                        (1)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_YES                  (0 << 1)
-#define NV_SOR_DP_PADCTL_PD_TXD_1_NO                   (1 << 1)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT                        (0)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_YES                  (0)
-#define NV_SOR_DP_PADCTL_PD_TXD_2_NO                   (1)
-#define NV_SOR_DP_SPARE(i)                             (0x62 + (i))
-#define NV_SOR_DP_SPARE_REG_SHIFT                      (3)
-#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK               (0x1fffffff << 3)
-#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT              (2)
-#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK        (0x1 << 2)
-#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK         (0 << 2)
-#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK        (1 << 2)
-#define NV_SOR_DP_SPARE_PANEL_SHIFT                    (1)
-#define NV_SOR_DP_SPARE_PANEL_EXTERNAL                 (0 << 1)
-#define NV_SOR_DP_SPARE_PANEL_INTERNAL                 (1 << 1)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT               (0)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO                  (0)
-#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES                 (1)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS                 (0x65)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK            (0x1ffff)
-#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT     (0)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS                 (0x66)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK            (0x1ffff)
-#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT           (0)
-#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER             (0x67)
-#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i)         (0x68 + (i))
+#define NV_SOR_SUPER_STATE0                                    (0x1)
+#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT                       (0)
+#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK                        (0x1)
+#define NV_SOR_SUPER_STATE1                                    (0x2)
+#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT                     (3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_NO                                (0 << 3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_YES                       (1 << 3)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT                   (2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE                    (0 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL                  (1 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT                  (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK           (0x3)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP                  (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE                 (1)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE                  (2)
+#define NV_SOR_STATE0                                          (0x3)
+#define NV_SOR_STATE0_UPDATE_SHIFT                             (0)
+#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK                      (0x1)
+#define NV_SOR_STATE1                                          (0x4)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT                     (17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK              (0xf << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422                        (1 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444                        (2 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422                        (3 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422                        (4 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444                        (5 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444                        (6 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422                        (7 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444                        (8 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444                        (9 << 17)
+#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT                      (15)
+#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK               (0x3 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_OFF                                (0 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X2                         (1 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X4                         (2 << 15)
+#define NV_SOR_STATE1_ASY_DEPOL_SHIFT                          (14)
+#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK                   (0x1 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE                  (0 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE                  (1 << 14)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT                       (13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK                        (0x1 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE               (0 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE               (1 << 13)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT                       (12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK                        (0x1 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE               (0 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE               (1 << 12)
+#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT                       (8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK                        (0xf << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM                 (0 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A                                (8 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B                                (9 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM                      (15 << 8)
+#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT                                (6)
+#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK                 (0x3 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER                        (0 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER              (1 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER            (2 << 6)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT                       (4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK                        (0x3 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_NONE                                (0 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0                    (1 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1                    (2 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH                                (3 << 4)
+#define NV_SOR_STATE1_ASY_OWNER_SHIFT                          (0)
+#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK                   (0xf)
+#define NV_SOR_STATE1_ASY_OWNER_NONE                           (0)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD0                          (1)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD1                          (2)
+#define NV_HEAD_STATE0(i)                                      (0x5)
+#define NV_HEAD_STATE0_INTERLACED_SHIFT                                (4)
+#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK                 (0x3 << 4)
+#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE                  (0 << 4)
+#define NV_HEAD_STATE0_INTERLACED_INTERLACED                   (1 << 4)
+#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT                     (3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK              (0x1 << 3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE                   (0 << 3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE                    (1 << 3)
+#define NV_HEAD_STATE0_DYNRANGE_SHIFT                          (2)
+#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK                   (0x1 << 2)
+#define NV_HEAD_STATE0_DYNRANGE_VESA                           (0 << 2)
+#define NV_HEAD_STATE0_DYNRANGE_CEA                            (1 << 2)
+#define NV_HEAD_STATE0_COLORSPACE_SHIFT                                (0)
+#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK                 (0x3)
+#define NV_HEAD_STATE0_COLORSPACE_RGB                          (0)
+#define NV_HEAD_STATE0_COLORSPACE_YUV_601                      (1)
+#define NV_HEAD_STATE0_COLORSPACE_YUV_709                      (2)
+#define NV_HEAD_STATE1(i)                                      (0x7 + i)
+#define NV_HEAD_STATE1_VTOTAL_SHIFT                            (16)
+#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK                     (0x7fff  << 16)
+#define NV_HEAD_STATE1_HTOTAL_SHIFT                            (0)
+#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK                     (0x7fff)
+#define NV_HEAD_STATE2(i)                                      (0x9 + i)
+#define NV_HEAD_STATE2_VSYNC_END_SHIFT                         (16)
+#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK                  (0x7fff << 16)
+#define NV_HEAD_STATE2_HSYNC_END_SHIFT                         (0)
+#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK                  (0x7fff)
+#define NV_HEAD_STATE3(i)                                      (0xb + i)
+#define NV_HEAD_STATE3_VBLANK_END_SHIFT                                (16)
+#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK                 (0x7fff << 16)
+#define NV_HEAD_STATE3_HBLANK_END_SHIFT                                (0)
+#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK                 (0x7fff)
+#define NV_HEAD_STATE4(i)                                      (0xd + i)
+#define NV_HEAD_STATE4_VBLANK_START_SHIFT                      (16)
+#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK               (0x7fff << 16)
+#define NV_HEAD_STATE4_HBLANK_START_SHIFT                      (0)
+#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK               (0x7fff)
+#define NV_HEAD_STATE5(i)                                      (0xf + i)
+#define NV_SOR_CRC_CNTRL                                       (0x11)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT                  (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO                     (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES                    (1)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS                    (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN                     (1)
+#define NV_SOR_CLK_CNTRL                                       (0x13)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT                      (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK                       (0x3)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK                        (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK                  (1)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK               (2)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK                 (3)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT                   (2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK                    (0x1f << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62                   (6 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7                    (10 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS                    (7 << 2)
+#define NV_SOR_CAP                                             (0x14)
+#define NV_SOR_CAP_DP_A_SHIFT                                  (24)
+#define NV_SOR_CAP_DP_A_DEFAULT_MASK                           (0x1 << 24)
+#define NV_SOR_CAP_DP_A_FALSE                                  (0 << 24)
+#define NV_SOR_CAP_DP_A_TRUE                                   (1 << 24)
+#define NV_SOR_CAP_DP_B_SHIFT                                  (25)
+#define NV_SOR_CAP_DP_B_DEFAULT_MASK                           (0x1 << 24)
+#define NV_SOR_CAP_DP_B_FALSE                                  (0 << 24)
+#define NV_SOR_CAP_DP_B_TRUE                                   (1 << 24)
+#define NV_SOR_PWR                                             (0x15)
+#define NV_SOR_PWR_SETTING_NEW_SHIFT                           (31)
+#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK                    (0x1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_DONE                            (0 << 31)
+#define NV_SOR_PWR_SETTING_NEW_PENDING                         (1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_TRIGGER                         (1 << 31)
+#define NV_SOR_PWR_MODE_SHIFT                                  (28)
+#define NV_SOR_PWR_MODE_DEFAULT_MASK                           (0x1 << 28)
+#define NV_SOR_PWR_MODE_NORMAL                                 (0 << 28)
+#define NV_SOR_PWR_MODE_SAFE                                   (1 << 28)
+#define NV_SOR_PWR_HALT_DELAY_SHIFT                            (24)
+#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK                     (0x1 << 24)
+#define NV_SOR_PWR_HALT_DELAY_DONE                             (0 << 24)
+#define NV_SOR_PWR_HALT_DELAY_ACTIVE                           (1 << 24)
+#define NV_SOR_PWR_SAFE_START_SHIFT                            (17)
+#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK                     (0x1 << 17)
+#define NV_SOR_PWR_SAFE_START_NORMAL                           (0 << 17)
+#define NV_SOR_PWR_SAFE_START_ALT                              (1 << 17)
+#define NV_SOR_PWR_SAFE_STATE_SHIFT                            (16)
+#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK                     (0x1 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PD                               (0 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PU                               (1 << 16)
+#define NV_SOR_PWR_NORMAL_START_SHIFT                          (1)
+#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK                   (0x1 << 1)
+#define NV_SOR_PWR_NORMAL_START_NORMAL                         (0 << 16)
+#define NV_SOR_PWR_NORMAL_START_ALT                            (1 << 16)
+#define NV_SOR_PWR_NORMAL_STATE_SHIFT                          (0)
+#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK                   (0x1)
+#define NV_SOR_PWR_NORMAL_STATE_PD                             (0)
+#define NV_SOR_PWR_NORMAL_STATE_PU                             (1)
+#define NV_SOR_TEST                                            (0x16)
+#define NV_SOR_TEST_TESTMUX_SHIFT                              (24)
+#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK                       (0xff << 24)
+#define NV_SOR_TEST_TESTMUX_AVSS                               (0 << 24)
+#define NV_SOR_TEST_TESTMUX_CLOCKIN                            (2 << 24)
+#define NV_SOR_TEST_TESTMUX_PLL_VOL                            (4 << 24)
+#define NV_SOR_TEST_TESTMUX_SLOWCLKINT                         (8 << 24)
+#define NV_SOR_TEST_TESTMUX_AVDD                               (16 << 24)
+#define NV_SOR_TEST_TESTMUX_VDDREG                             (32 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG                      (64 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_AVDD                                (128 << 24)
+#define NV_SOR_TEST_CRC_SHIFT                                  (23)
+#define NV_SOR_TEST_CRC_PRE_SERIALIZE                          (0 << 23)
+#define NV_SOR_TEST_CRC_POST_DESERIALIZE                       (1 << 23)
+#define NV_SOR_TEST_TPAT_SHIFT                                 (20)
+#define NV_SOR_TEST_TPAT_DEFAULT_MASK                          (0x7 << 20)
+#define NV_SOR_TEST_TPAT_LO                                    (0 << 20)
+#define NV_SOR_TEST_TPAT_TDAT                                  (1 << 20)
+#define NV_SOR_TEST_TPAT_RAMP                                  (2 << 20)
+#define NV_SOR_TEST_TPAT_WALK                                  (3 << 20)
+#define NV_SOR_TEST_TPAT_MAXSTEP                               (4 << 20)
+#define NV_SOR_TEST_TPAT_MINSTEP                               (5 << 20)
+#define NV_SOR_TEST_DSRC_SHIFT                                 (16)
+#define NV_SOR_TEST_DSRC_DEFAULT_MASK                          (0x3 << 16)
+#define NV_SOR_TEST_DSRC_NORMAL                                        (0 << 16)
+#define NV_SOR_TEST_DSRC_DEBUG                                 (1 << 16)
+#define NV_SOR_TEST_DSRC_TGEN                                  (2 << 16)
+#define NV_SOR_TEST_HEAD_NUMBER_SHIFT                          (12)
+#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK                   (0x3 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_NONE                           (0 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD0                          (1 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD1                          (2 << 12)
+#define NV_SOR_TEST_ATTACHED_SHIFT                             (10)
+#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK                      (0x1  << 10)
+#define NV_SOR_TEST_ATTACHED_FALSE                             (0 << 10)
+#define NV_SOR_TEST_ATTACHED_TRUE                              (1 << 10)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT                      (8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK               (0x3 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP                      (0 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE                     (1 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE                      (2 << 8)
+#define NV_SOR_TEST_INVD_SHIFT                                 (6)
+#define NV_SOR_TEST_INVD_DISABLE                               (0 << 6)
+#define NV_SOR_TEST_INVD_ENABLE                                        (1 << 6)
+#define NV_SOR_TEST_TEST_ENABLE_SHIFT                          (1)
+#define NV_SOR_TEST_TEST_ENABLE_DISABLE                                (0 << 1)
+#define NV_SOR_TEST_TEST_ENABLE_ENABLE                         (1 << 1)
+#define NV_SOR_PLL0                                            (0x17)
+#define NV_SOR_PLL0_ICHPMP_SHFIT                               (24)
+#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK                                (0xf << 24)
+#define NV_SOR_PLL0_VCOCAP_SHIFT                               (8)
+#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK                                (0xf << 8)
+#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT                         (6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK                  (0x3 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V25                           (0 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V15                           (1 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V35                           (2 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V45                           (3 << 6)
+#define NV_SOR_PLL0_PULLDOWN_SHIFT                             (5)
+#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK                      (0x1 << 5)
+#define NV_SOR_PLL0_PULLDOWN_DISABLE                           (0 << 5)
+#define NV_SOR_PLL0_PULLDOWN_ENABLE                            (1 << 5)
+#define NV_SOR_PLL0_RESISTORSEL_SHIFT                          (4)
+#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK                   (0x1 << 4)
+#define NV_SOR_PLL0_RESISTORSEL_INT                            (0 << 4)
+#define NV_SOR_PLL0_RESISTORSEL_EXT                            (1 << 4)
+#define NV_SOR_PLL0_VCOPD_SHIFT                                        (2)
+#define NV_SOR_PLL0_VCOPD_MASK                                 (1 << 2)
+#define NV_SOR_PLL0_VCOPD_RESCIND                              (0 << 2)
+#define NV_SOR_PLL0_VCOPD_ASSERT                               (1 << 2)
+#define NV_SOR_PLL0_PWR_SHIFT                                  (0)
+#define NV_SOR_PLL0_PWR_MASK                                   (1)
+#define NV_SOR_PLL0_PWR_ON                                     (0)
+#define NV_SOR_PLL0_PWR_OFF                                    (1)
+#define NV_SOR_PLL1                                            (0x18)
+#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT                         (15)
+#define NV_SOR_PLL1_TERM_COMPOUT_LOW                           (0 << 15)
+#define NV_SOR_PLL1_TERM_COMPOUT_HIGH                          (1 << 15)
+#define NV_SOR_PLL2                                            (0x19)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT                       (0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE                    (0 << 0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW                       (1 << 0)
+#define NV_SOR_PLL2_AUX1_SHIFT                                 (17)
+#define NV_SOR_PLL2_AUX1_SEQ_MASK                              (1 << 17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW                    (0 << 17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE                 (1 << 17)
+#define NV_SOR_PLL2_AUX2_SHIFT                                 (18)
+#define NV_SOR_PLL2_AUX2_MASK                                  (1 << 18)
+#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN                    (0 << 18)
+#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN                       (1 << 18)
+#define NV_SOR_PLL2_AUX6_SHIFT                                 (22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK                        (1 << 22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE             (0 << 22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE              (1 << 22)
+#define NV_SOR_PLL2_AUX7_SHIFT                                 (23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK                   (1 << 23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE                        (0 << 23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE                 (1 << 23)
+#define NV_SOR_PLL2_AUX8_SHIFT                                 (24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK             (1 << 24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE          (0 << 24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE           (1 << 24)
+#define NV_SOR_PLL3                                            (0x1a)
+#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT                          (13)
+#define NV_SOR_PLL3_PLLVDD_MODE_MASK                           (1 << 13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V1_8                           (0 << 13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V3_3                           (1 << 13)
+#define NV_SOR_CSTM                                            (0x1b)
+#define NV_SOR_CSTM_ROTDAT_SHIFT                               (28)
+#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK                                (0x7 << 28)
+#define NV_SOR_CSTM_ROTCLK_SHIFT                               (24)
+#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK                                (0xf << 24)
+#define NV_SOR_LVDS                                            (0x1c)
+#define NV_SOR_LVDS_ROTDAT_SHIFT                               (28)
+#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK                                (0x7 << 28)
+#define NV_SOR_LVDS_ROTDAT_RST                                 (0 << 28)
+#define NV_SOR_LVDS_ROTCLK_SHIFT                               (24)
+#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK                                (0xf << 24)
+#define NV_SOR_LVDS_ROTCLK_RST                                 (0 << 24)
+#define NV_SOR_LVDS_PLLDIV_SHIFT                               (21)
+#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK                                (0x1 << 21)
+#define NV_SOR_LVDS_PLLDIV_BY_7                                        (0 << 21)
+#define NV_SOR_LVDS_BALANCED_SHIFT                             (19)
+#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK                      (0x1 << 19)
+#define NV_SOR_LVDS_BALANCED_DISABLE                           (0 << 19)
+#define NV_SOR_LVDS_BALANCED_ENABLE                            (1 << 19)
+#define NV_SOR_LVDS_NEW_MODE_SHIFT                             (18)
+#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK                      (0x1 << 18)
+#define NV_SOR_LVDS_NEW_MODE_DISABLE                           (0 << 18)
+#define NV_SOR_LVDS_NEW_MODE_ENABLE                            (1 << 18)
+#define NV_SOR_LVDS_DUP_SYNC_SHIFT                             (17)
+#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK                      (0x1 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_DISABLE                           (0 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_ENABLE                            (1 << 17)
+#define NV_SOR_LVDS_LVDS_EN_SHIFT                              (16)
+#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK                       (0x1 << 16)
+#define NV_SOR_LVDS_LVDS_EN_ENABLE                             (1 << 16)
+#define NV_SOR_LVDS_LINKACTB_SHIFT                             (15)
+#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK                      (0x1 << 15)
+#define NV_SOR_LVDS_LINKACTB_DISABLE                           (0 << 15)
+#define NV_SOR_LVDS_LINKACTB_ENABLE                            (1 << 15)
+#define NV_SOR_LVDS_LINKACTA_SHIFT                             (14)
+#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK                      (0x1 << 14)
+#define NV_SOR_LVDS_LINKACTA_ENABLE                            (1 << 14)
+#define NV_SOR_LVDS_MODE_SHIFT                                 (12)
+#define NV_SOR_LVDS_MODE_DEFAULT_MASK                          (0x3 << 12)
+#define NV_SOR_LVDS_MODE_LVDS                                  (0 << 12)
+#define NV_SOR_LVDS_UPPER_SHIFT                                        (11)
+#define NV_SOR_LVDS_UPPER_DEFAULT_MASK                         (0x1 << 11)
+#define NV_SOR_LVDS_UPPER_FALSE                                        (0 << 11)
+#define NV_SOR_LVDS_UPPER_TRUE                                 (1 << 11)
+#define NV_SOR_LVDS_PD_TXCB_SHIFT                              (9)
+#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK                       (0x1 << 9)
+#define NV_SOR_LVDS_PD_TXCB_ENABLE                             (0 << 9)
+#define NV_SOR_LVDS_PD_TXCB_DISABLE                            (1 << 9)
+#define NV_SOR_LVDS_PD_TXCA_SHIFT                              (8)
+#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK                       (0x1 << 8)
+#define NV_SOR_LVDS_PD_TXCA_ENABLE                             (0 << 8)
+#define NV_SOR_LVDS_PD_TXDB_3_SHIFT                            (7)
+#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK                     (0x1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_ENABLE                           (0 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_DISABLE                          (1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_2_SHIFT                            (6)
+#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK                     (0x1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_ENABLE                           (0 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_DISABLE                          (1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_1_SHIFT                            (5)
+#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK                     (0x1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_ENABLE                           (0 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_DISABLE                          (1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_0_SHIFT                            (4)
+#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK                     (0x1 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_ENABLE                           (0 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_DISABLE                          (1 << 4)
+#define NV_SOR_LVDS_PD_TXDA_3_SHIFT                            (3)
+#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK                     (0x1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_ENABLE                           (0 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_DISABLE                          (1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_2_SHIFT                            (2)
+#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK                     (0x1 << 2)
+#define NV_SOR_LVDS_PD_TXDA_2_ENABLE                           (0 << 2)
+#define NV_SOR_LVDS_PD_TXDA_1_SHIFT                            (1)
+#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK                     (0x1 << 1)
+#define NV_SOR_LVDS_PD_TXDA_1_ENABLE                           (0 << 1)
+#define NV_SOR_LVDS_PD_TXDA_0_SHIFT                            (0)
+#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK                     (0x1)
+#define NV_SOR_LVDS_PD_TXDA_0_ENABLE                           (0)
+#define NV_SOR_CRCA                                            (0x1d)
+#define NV_SOR_CRCA_VALID_FALSE                                        (0)
+#define NV_SOR_CRCA_VALID_TRUE                                 (1)
+#define NV_SOR_CRCA_VALID_RST                                  (1)
+#define NV_SOR_CRCB                                            (0x1e)
+#define NV_SOR_CRCB_CRC_DEFAULT_MASK                           (0xffffffff)
+#define NV_SOR_SEQ_CTL                                         (0x20)
+#define NV_SOR_SEQ_CTL_SWITCH_SHIFT                            (30)
+#define NV_SOR_SEQ_CTL_SWITCH_MASK                             (0x1 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_WAIT                             (0 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_FORCE                            (1 << 30)
+#define NV_SOR_SEQ_CTL_STATUS_SHIFT                            (28)
+#define NV_SOR_SEQ_CTL_STATUS_MASK                             (0x1 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_STOPPED                          (0 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_RUNNING                          (1 << 28)
+#define NV_SOR_SEQ_CTL_PC_SHIFT                                        (16)
+#define NV_SOR_SEQ_CTL_PC_MASK                                 (0xf << 16)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT                         (12)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK                          (0xf << 12)
+#define NV_SOR_SEQ_CTL_PD_PC_SHIFT                             (8)
+#define NV_SOR_SEQ_CTL_PD_PC_MASK                              (0xf << 8)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT                         (4)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK                          (0xf << 4)
+#define NV_SOR_SEQ_CTL_PU_PC_SHIFT                             (0)
+#define NV_SOR_SEQ_CTL_PU_PC_MASK                              (0xf)
+#define NV_SOR_LANE_SEQ_CTL                                    (0x21)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT                  (31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK                       (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE                   (0 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING                        (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER                        (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT                    (28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE                     (0 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY                     (1 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT                     (20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP                                (0 << 20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN                      (1 << 20)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT              (16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU                 (0 << 16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD                 (1 << 16)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT                                (12)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK                 (0xf << 12)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT                  (9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP                        (0 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN              (1 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT                  (8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP                        (0 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN              (1 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT                  (7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP                        (0 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN              (1 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT                  (6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP                        (0 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN              (1 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT                  (5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP                        (0 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN              (1 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT                  (4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP                        (0 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN              (1 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT                  (3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP                        (0 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN              (1 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT                  (2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP                        (0 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN              (1 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT                  (1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP                        (0 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN              (1 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT                  (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP                        (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN              (1)
+#define NV_SOR_SEQ_INST(i)                                     (0x22 + i)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT                     (31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE                   (0 << 31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE                    (1 << 31)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT                  (30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL                 (0 << 30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN              (1 << 30)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT                 (29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL                        (0 << 29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST                   (1 << 29)
+#define NV_SOR_SEQ_INST_BLANK_V_SHIFT                          (28)
+#define NV_SOR_SEQ_INST_BLANK_V_NORMAL                         (0 << 28)
+#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE                       (1 << 28)
+#define NV_SOR_SEQ_INST_BLANK_H_SHIFT                          (27)
+#define NV_SOR_SEQ_INST_BLANK_H_NORMAL                         (0 << 27)
+#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE                       (1 << 27)
+#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT                         (26)
+#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL                                (0 << 26)
+#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE                      (1 << 26)
+#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT                       (25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL                      (0 << 25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK                       (1 << 25)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT                     (24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS               (0 << 24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE                  (1 << 24)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT                 (23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE                 (0 << 23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE                  (1 << 23)
+#define NV_SOR_SEQ_INST_PIN_B_SHIFT                            (22)
+#define NV_SOR_SEQ_INST_PIN_B_LOW                              (0 << 22)
+#define NV_SOR_SEQ_INST_PIN_B_HIGH                             (1 << 22)
+#define NV_SOR_SEQ_INST_PIN_A_SHIFT                            (21)
+#define NV_SOR_SEQ_INST_PIN_A_LOW                              (0 << 21)
+#define NV_SOR_SEQ_INST_PIN_A_HIGH                             (1 << 21)
+#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT                         (19)
+#define NV_SOR_SEQ_INST_SEQUENCE_UP                            (0 << 19)
+#define NV_SOR_SEQ_INST_SEQUENCE_DOWN                          (1 << 19)
+#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT                         (18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_STOP                          (0 << 18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_RUN                           (1 << 18)
+#define NV_SOR_SEQ_INST_PDPORT_SHIFT                           (17)
+#define NV_SOR_SEQ_INST_PDPORT_NO                              (0 << 17)
+#define NV_SOR_SEQ_INST_PDPORT_YES                             (1 << 17)
+#define NV_SOR_SEQ_INST_PDPLL_SHIFT                            (16)
+#define NV_SOR_SEQ_INST_PDPLL_NO                               (0 << 16)
+#define NV_SOR_SEQ_INST_PDPLL_YES                              (1 << 16)
+#define NV_SOR_SEQ_INST_HALT_SHIFT                             (15)
+#define NV_SOR_SEQ_INST_HALT_FALSE                             (0 << 15)
+#define NV_SOR_SEQ_INST_HALT_TRUE                              (1 << 15)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT                       (12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK                        (0x3 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_US                          (0 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_MS                          (1 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC                       (2 << 12)
+#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT                                (0)
+#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK                 (0x3ff)
+#define NV_SOR_PWM_DIV                                         (0x32)
+#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK                     (0xffffff)
+#define NV_SOR_PWM_CTL                                         (0x33)
+#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT                       (31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_DONE                                (0 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING                     (1 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER                     (1 << 31)
+#define NV_SOR_PWM_CTL_CLKSEL_SHIFT                            (30)
+#define NV_SOR_PWM_CTL_CLKSEL_PCLK                             (0 << 30)
+#define NV_SOR_PWM_CTL_CLKSEL_XTAL                             (1 << 30)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT                                (0)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK                         (0xffffff)
+#define NV_SOR_MSCHECK                                         (0x49)
+#define NV_SOR_MSCHECK_CTL_SHIFT                               (31)
+#define NV_SOR_MSCHECK_CTL_CLEAR                               (0 << 31)
+#define NV_SOR_MSCHECK_CTL_RUN                                 (1 << 31)
+#define NV_SOR_XBAR_CTRL                                       (0x4a)
+#define NV_SOR_DP_LINKCTL(i)                                   (0x4c + (i))
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT                        (31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO                   (0 << 31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES                  (1 << 31)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT                        (28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN            (0 << 28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE           (1 << 28)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT                      (16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK                       (0x1f << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO                       (0 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE                                (1 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO                                (3 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR                       (15 << 16)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT                  (14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                        (0 << 14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE                 (1 << 14)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT                       (10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE                     (0 << 10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE                      (1 << 10)
+#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT                         (2)
+#define NV_SOR_DP_LINKCTL_TUSIZE_MASK                          (0x7f << 2)
+#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT                         (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_NO                            (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_YES                           (1)
+#define NV_SOR_DC(i)                                           (0x4e + (i))
+#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT                         (24)
+#define NV_SOR_DC_LANE3_DP_LANE3_MASK                          (0xff << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0                     (17 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0                     (21 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0                     (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0                     (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1                     (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1                     (32 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1                     (39 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2                     (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2                     (43 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3                     (51 << 24)
+#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                         (16)
+#define NV_SOR_DC_LANE2_DP_LANE0_MASK                          (0xff << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0                     (17 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0                     (21 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0                     (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0                     (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1                     (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1                     (32 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1                     (39 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2                     (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2                     (43 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3                     (51 << 16)
+#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                         (8)
+#define NV_SOR_DC_LANE1_DP_LANE1_MASK                          (0xff << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0                     (17 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0                     (21 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0                     (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0                     (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1                     (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1                     (32 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1                     (39 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2                     (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2                     (43 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3                     (51 << 8)
+#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                         (0)
+#define NV_SOR_DC_LANE0_DP_LANE2_MASK                          (0xff)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0                     (17)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0                     (21)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0                     (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0                     (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1                     (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1                     (32)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1                     (39)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2                     (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2                     (43)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3                     (51)
+#define NV_SOR_LANE4_DRIVE_CURRENT(i)                          (0x50 + (i))
+#define NV_SOR_PR(i)                                           (0x52 + (i))
+#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                         (24)
+#define NV_SOR_PR_LANE3_DP_LANE3_MASK                          (0xff << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0                     (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0                     (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0                     (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0                     (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1                     (4 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1                     (6 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1                     (17 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2                     (8 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2                     (13 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3                     (17 << 24)
+#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT                         (16)
+#define NV_SOR_PR_LANE2_DP_LANE0_MASK                          (0xff << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0                     (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0                     (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0                     (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0                     (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1                     (4 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1                     (6 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1                     (17 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2                     (8 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2                     (13 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3                     (17 << 16)
+#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT                         (8)
+#define NV_SOR_PR_LANE1_DP_LANE1_MASK                          (0xff >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0                     (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0                     (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0                     (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0                     (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1                     (4 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1                     (6 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1                     (17 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2                     (8 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2                     (13 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3                     (17 >> 8)
+#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT                         (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_MASK                          (0xff)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0                     (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0                     (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0                     (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0                     (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1                     (4)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1                     (6)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1                     (17)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2                     (8)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2                     (13)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3                     (17)
+#define NV_SOR_LANE4_PREEMPHASIS(i)                            (0x54 + (i))
+#define NV_SOR_DP_CONFIG(i)                                    (0x58 + (i))
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT                    (31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE                 (0 << 31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE                 (1 << 31)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT              (28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE            (0 << 28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE             (1 << 28)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT                  (26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE                        (0 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE                 (1 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT              (24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE           (0 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE           (1 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT                  (16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK                   (0xf << 16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT                 (8)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK                  (0x7f << 8)
+#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT                       (0)
+#define NV_SOR_DP_CONFIG_WATERMARK_MASK                                (0x3f)
+#define NV_SOR_DP_MN(i)                                                (0x5a + i)
+#define NV_SOR_DP_MN_M_MOD_SHIFT                               (30)
+#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK                                (0x3 << 30)
+#define NV_SOR_DP_MN_M_MOD_NONE                                        (0 << 30)
+#define NV_SOR_DP_MN_M_MOD_INC                                 (1 << 30)
+#define NV_SOR_DP_MN_M_MOD_DEC                                 (2 << 30)
+#define NV_SOR_DP_MN_M_DELTA_SHIFT                             (24)
+#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK                      (0xf << 24)
+#define NV_SOR_DP_MN_N_VAL_SHIFT                               (0)
+#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK                                (0xffffff)
+#define NV_SOR_DP_PADCTL(i)                                    (0x5c + (i))
+#define NV_SOR_DP_PADCTL_SPARE_SHIFT                           (25)
+#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK                    (0x7f << 25)
+#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT                          (24)
+#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE                                (0 << 24)
+#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE                         (1 << 24)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT                      (23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP                    (0 << 23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN                  (1 << 23)
+#define NV_SOR_DP_PADCTL_TX_PU_SHIFT                           (22)
+#define NV_SOR_DP_PADCTL_TX_PU_DISABLE                         (0 << 22)
+#define NV_SOR_DP_PADCTL_TX_PU_ENABLE                          (1 << 22)
+#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT                                (20)
+#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK                 (0x3 << 20)
+#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT                         (16)
+#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK                  (0xf << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE                      (0 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX                      (1 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN                 (2 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN               (4 << 16)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT                     (8)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK              (0xff << 8)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT           (7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE         (0 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE          (1 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT           (6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE         (0 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE          (1 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT           (5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE         (0 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE          (1 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT           (4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE         (0 << 4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE          (1 << 4)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT                                (3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_YES                          (0 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_NO                           (1 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT                                (2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_YES                          (0 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_NO                           (1 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT                                (1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_YES                          (0 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_NO                           (1 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT                                (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_YES                          (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_NO                           (1)
+#define NV_SOR_DP_DEBUG(i)                                     (0x5e + i)
+#define NV_SOR_DP_SPARE(i)                                     (0x60 + (i))
+#define NV_SOR_DP_SPARE_REG_SHIFT                              (3)
+#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK                       (0x1fffffff << 3)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT                      (2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK               (0x1 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK                        (0 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK               (1 << 2)
+#define NV_SOR_DP_SPARE_PANEL_SHIFT                            (1)
+#define NV_SOR_DP_SPARE_PANEL_EXTERNAL                         (0 << 1)
+#define NV_SOR_DP_SPARE_PANEL_INTERNAL                         (1 << 1)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT                       (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO                          (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES                         (1)
+#define NV_SOR_DP_AUDIO_CTRL                                   (0x62)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS                         (0x63)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK                    (0x1ffff)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT             (0)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS                         (0x64)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK                    (0x1ffff)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT                   (0)
+#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER                     (0x65)
+#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i)                 (0x66 + (i))
+#define NV_SOR_DP_TPG                                          (0x6d)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT                        (30)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE              (0 << 30)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE               (1 << 30)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT                  (28)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS          (1 << 28)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI       (2 << 28)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT                      (24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK               (0xf << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN                  (0 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1                  (1 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2                  (2 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3                  (3 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_D102                       (4 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE                 (5 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7                      (6 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM                       (7 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE            (8 << 24)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT                        (22)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE              (0 << 22)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE               (1 << 22)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT                  (20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK           (0x3 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE                        (0 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS          (1 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI       (2 << 20)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT                      (16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK               (0xf << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN                  (0 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1                  (1 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2                  (2 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3                  (3 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_D102                       (4 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE                 (5 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7                      (6 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM                       (7 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE            (8 << 16)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT                        (14)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE              (0 << 14)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE               (1 << 14)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT                  (12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK           (0x3 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE                        (0 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS          (1 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI       (2 << 12)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT                      (8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK               (0xf << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN                  (0 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1                  (1 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2                  (2 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3                  (3 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_D102                       (4 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE                 (5 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7                      (6 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM                       (7 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE            (8 << 8)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT                        (6)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE              (0 << 6)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE               (1 << 6)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT                  (4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK           (0x3 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE                        (0 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS          (1 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI       (2 << 4)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT                      (0)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK               (0xf)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN                  (0)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1                  (1)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2                  (2)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3                  (3)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_D102                       (4)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE                 (5)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7                      (6)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM                       (7)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE            (8)
+
 
 #endif