arm: tegra: LP1 Low Core Voltage Support for T114
Karthik Ramakrishnan [Fri, 25 Jan 2013 23:05:33 +0000 (15:05 -0800)]
The feature was added for T30 and the config name referred to
the lowest Core voltage for Enterprise(CONFIG_TEGRA_LP1_950).
Changed the Kconfig to include T114 support and renamed the
feature name to refer to the lowest Core voltage possible for
the particular platform and not just 950mV.

The initial change for this feature is in http://git-master/r/124135

Bug 1035684

Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Signed-off-by: Hunk Lin <hulin@nvidia.com>
(cherry picked from commit c94f740ede4809a897e18253a9c7fdfb8666970e)
Reviewed-on: http://git-master/r/194260
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/pm.h
arch/arm/mach-tegra/sleep-t30.S
arch/arm/mach-tegra/sleep.h

index fa221d0..b1111ce 100644 (file)
@@ -562,10 +562,10 @@ config ARCH_TEGRA_4GB_MEMORY
          Harmless to select this even if hardware does not support full
          4GB physical memory.
 
-config TEGRA_LP1_950
+config TEGRA_LP1_LOW_COREVOLTAGE
        bool "LP1 low core voltage"
        default n
-       depends on ARCH_TEGRA_3x_SOC
+       depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
        help
                Enable support for LP1 Core voltage to set to lowest
 
index 2e6b64a..09a1d26 100644 (file)
@@ -1387,7 +1387,7 @@ out:
                plat->suspend_mode = TEGRA_SUSPEND_LP2;
        }
 
-#ifdef CONFIG_TEGRA_LP1_950
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
        if (pdata->lp1_lowvolt_support) {
                u32 lp1_core_lowvolt, lp1_core_highvolt;
                memcpy(tegra_lp1_register_pmuslave_addr(), &pdata->pmuslave_addr, 4);
index 706aab2..e0b7106 100644 (file)
@@ -66,7 +66,7 @@ struct tegra_suspend_platform_data {
        /* lp_state = 0 for LP0 state, 1 for LP1 state, 2 for LP2 state */
        void (*board_resume)(int lp_state, enum resume_stage stg);
        unsigned int cpu_resume_boost;  /* CPU frequency resume boost in kHz */
-#ifdef CONFIG_TEGRA_LP1_950
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
        bool lp1_lowvolt_support;
        unsigned int i2c_base_addr;
        unsigned int pmuslave_addr;
index 904cd34..7b188ab 100644 (file)
@@ -467,7 +467,7 @@ ENTRY(tegra3_lp1_reset)
        str     r4, [r0, #CLK_RESET_CCLK_BURST]
 #endif
 
-#ifdef CONFIG_TEGRA_LP1_950
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
 lp1_voltset:
        /* Restore the Core voltage to high on LP1 resume */
        /* Reset(Enable/Disable) the DVC-I2C Controller*/
@@ -802,7 +802,7 @@ tegra11_sdram_pad_address:
        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
 #endif
 
-#ifdef CONFIG_TEGRA_LP1_950
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
        .globl lp1_register_pmuslave_addr
        .globl lp1_register_i2c_base_addr
        .globl lp1_register_core_lowvolt
@@ -1002,7 +1002,7 @@ tegra3_cpu_clk32k:
 lp1_clocks_prepare:
        /* Prepare to set the Core to the lowest voltage if supported.
         * Start by setting the I2C clocks to make the I2C transfer */
-#ifdef CONFIG_TEGRA_LP1_950
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
        /* Set up the PWR I2C GPIOs with the right masks*/
 
        /* Reset(Set/Clr) the DVC-I2C Controller*/
index aae0737..c0dc42e 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -322,10 +322,12 @@ int tegra2_finish_sleep_cpu_secondary(unsigned long int);
 #else
 extern unsigned int tegra3_iram_start;
 extern unsigned int tegra3_iram_end;
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
 extern unsigned int lp1_register_pmuslave_addr;
 extern unsigned int lp1_register_i2c_base_addr;
 extern unsigned int lp1_register_core_lowvolt;
 extern unsigned int lp1_register_core_highvolt;
+#endif
 int tegra3_sleep_core_finish(unsigned long int);
 int tegra3_sleep_cpu_secondary_finish(unsigned long int);
 int tegra3_stop_mc_clk_finish(unsigned long int);
@@ -362,6 +364,7 @@ static inline void *tegra_iram_end(void)
 #endif
 }
 
+#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
 static inline void *tegra_lp1_register_pmuslave_addr(void)
 {
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
@@ -397,5 +400,6 @@ static inline void *tegra_lp1_register_core_highvolt(void)
        return &lp1_register_core_highvolt;
 #endif
 }
+#endif /* For CONFIG_TEGRA_LP1_LOW_COREVOLTAGE */
 #endif
 #endif