video: tegra: Use new Tegra platform types
Yudong Tan [Mon, 27 Jun 2011 21:05:58 +0000 (14:05 -0700)]
This change is needed to support three platforms, silicon,
fpga and simulation.

Change-Id: I70c6edbab85712b037b1ddf15ce72cf1a2affeba
Reviewed-on: http://git-master/r/36354
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rdd2875e5494a504dc4d2df0393bc798765a9b865

drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/rgb.c

index b679d87..64bda03 100644 (file)
@@ -1522,10 +1522,10 @@ EXPORT_SYMBOL(tegra_dc_sync_windows);
 
 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
 {
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-       return 27000000;
-#else
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
        return clk_get_rate(dc->clk);
+#else
+       return 27000000;
 #endif
 }
 
@@ -1797,11 +1797,11 @@ static inline void print_mode(struct tegra_dc *dc,
 
 static inline void enable_dc_irq(unsigned int irq)
 {
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
+       enable_irq(irq);
+#else
        /* Always disable DC interrupts on FPGA. */
        disable_irq(irq);
-#else
-       enable_irq(irq);
 #endif
 }
 
@@ -2415,7 +2415,7 @@ static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
 
 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
 {
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
        struct tegra_dc *dc = ptr;
        unsigned long status;
        unsigned long underflow_mask;
@@ -2457,9 +2457,9 @@ static irqreturn_t tegra_dc_irq(int irq, void *ptr)
                tegra_dc_continuous_irq(dc, status);
 
        return IRQ_HANDLED;
-#else /* CONFIG_TEGRA_FPGA_PLATFORM */
+#else /* CONFIG_TEGRA_SILICON_PLATFORM */
        return IRQ_NONE;
-#endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
+#endif /* !CONFIG_TEGRA_SILICON_PLATFORM */
 }
 
 static void tegra_dc_set_color_control(struct tegra_dc *dc)
@@ -2713,7 +2713,7 @@ static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
        msleep(5);
        tegra_periph_reset_assert(dc->clk);
        msleep(2);
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
        tegra_periph_reset_deassert(dc->clk);
        msleep(1);
 #endif
index 4fea1f7..1c1f4d9 100644 (file)
@@ -1615,7 +1615,7 @@ static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
        /* Get the corresponding register value of shift_clk_div. */
        shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
 
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+#ifndef CONFIG_TEGRA_SILICON_PLATFORM
        shift_clk_div_register = 1;
        if (dsi->info.ganged_type)
                shift_clk_div_register = 0;
index 6afde6b..47d4e69 100644 (file)
@@ -55,13 +55,13 @@ static const u32 tegra_dc_rgb_enable_out_sel_pintable[] = {
        DC_COM_PIN_OUTPUT_SELECT0,      0x00000000,
        DC_COM_PIN_OUTPUT_SELECT1,      0x00000000,
        DC_COM_PIN_OUTPUT_SELECT2,      0x00000000,
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
+       DC_COM_PIN_OUTPUT_SELECT3,      0x00000000,
+#else
        /* The display panel sub-board used on FPGA platforms (panel 86)
           is non-standard. It expects the Data Enable signal on the WR
           pin instead of the DE pin. */
        DC_COM_PIN_OUTPUT_SELECT3,      0x00200000,
-#else
-       DC_COM_PIN_OUTPUT_SELECT3,      0x00000000,
 #endif
        DC_COM_PIN_OUTPUT_SELECT4,      0x00210222,
        DC_COM_PIN_OUTPUT_SELECT5,      0x00002200,