ARM: tegra: vcm30_t124: Enable more interfaces
Ashwin Joshi [Thu, 3 Oct 2013 07:52:15 +0000 (12:52 +0530)]
Enable following interfaces for vcm30_t124 platform:

1.NOR
2.SATA
3.SDIO

Bug 1319925

Change-Id: I2587af3c47c48e9b6d90d8e439886c1460fb6654
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/277183
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/board-vcm30_t124-power.c
arch/arm/mach-tegra/board-vcm30_t124-sdhci.c
arch/arm/mach-tegra/board-vcm30_t124.c

index 9132fe8..a8e7fa3 100644 (file)
@@ -66,6 +66,9 @@ static struct regulator_consumer_supply max77663_sd2_supply[] = {
        REGULATOR_SUPPLY("pwrdet_cam", NULL),
        REGULATOR_SUPPLY("avdd_osc", NULL),
        REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.1"),
+       REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
        REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
        REGULATOR_SUPPLY("vdd_emmc", NULL),
 };
@@ -86,6 +89,7 @@ static struct regulator_consumer_supply max77663_sd3_supply[] = {
        REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
        REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
        REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
+       REGULATOR_SUPPLY("hvdd_sata", NULL),
 };
 
 static struct regulator_consumer_supply max77663_sd4_supply[] = {
@@ -141,6 +145,9 @@ static struct regulator_consumer_supply max77663_ldo7_supply[] = {
 };
 
 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
+       REGULATOR_SUPPLY("avdd_sata", NULL),
+       REGULATOR_SUPPLY("vdd_sata", NULL),
+       REGULATOR_SUPPLY("avdd_sata_pll", NULL),
 };
 
 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
@@ -195,6 +202,8 @@ static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
                .flags = _flags, \
        }
 
+/* FIXME: Revisit maximum constraint value for all supplies */
+
 MAX77663_PDATA_INIT(SD0, sd0,  600000, 3387500, NULL, 1, 0, 0,
                FPS_SRC_NONE, -1, -1, 0);
 
@@ -225,7 +234,7 @@ MAX77663_PDATA_INIT(LDO3, ldo3, 800000, 3950000, NULL, 1, 1, 0,
 MAX77663_PDATA_INIT(LDO4, ldo4, 1000000, 1000000, NULL, 0, 1, 0,
                FPS_SRC_0, -1, -1, 0);
 
-MAX77663_PDATA_INIT(LDO5, ldo5, 800000, 2800000, NULL, 0, 1, 0,
+MAX77663_PDATA_INIT(LDO5, ldo5, 800000, 3950000, NULL, 0, 1, 0,
                FPS_SRC_NONE, -1, -1, 0);
 
 MAX77663_PDATA_INIT(LDO6, ldo6, 800000, 3950000, NULL, 0, 0, 0,
index fe6d12f..341a968 100644 (file)
@@ -102,40 +102,48 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .is_8bit = false,
-       .tap_delay = 0x06,
-       .max_clk_limit = 52000000,
-       .ddr_clk_limit = 30000000,
-       .uhs_mask = MMC_UHS_MASK_DDR50,
+       .tap_delay = 0x4,
+       .trim_delay = 0x4,
+       .ddr_trim_delay = 0x4,
        .mmc_data = {
                .built_in = 1,
-       }
+               .ocr_mask = MMC_OCR_1V8_MASK,
+       },
+       .uhs_mask = MMC_MASK_HS200,
+       .ddr_clk_limit = 30000000,
+       .max_clk_limit = 52000000,
+       /*      .max_clk = 12000000, */
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .cd_gpio = TEGRA_GPIO_PQ5,
        .wp_gpio = TEGRA_GPIO_PQ4,
        .power_gpio = -1,
-       .is_8bit = false,
-       /* WAR: Operating SDR104 cards at upto 104 MHz, as signal errors are
-        * seen when they are operated at any higher frequency.
-        */
-       .max_clk_limit = 104000000,
-       .ddr_clk_limit = 30000000,
+       .tap_delay = 0x0,
+       .trim_delay = 0x3,
+       .uhs_mask = MMC_UHS_MASK_SDR104 |
+               MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
        .mmc_data = {
                .ocr_mask = MMC_OCR_2V8_MASK,
        },
-       .cd_wakeup_incapable = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data4 = {
        .cd_gpio = -1,
        .wp_gpio = -1,
        .power_gpio = -1,
-       .is_8bit = true,
-       .tap_delay = 0x06,
-       .max_clk_limit = 52000000,
+       .is_8bit = 0,
+       .tap_delay = 0x4,
+       .trim_delay = 0x4,
+       .ddr_trim_delay = 0x4,
+       .mmc_data = {
+               .built_in = 1,
+               .ocr_mask = MMC_OCR_1V8_MASK,
+       },
+       .uhs_mask = MMC_MASK_HS200,
        .ddr_clk_limit = 51000000,
-       .uhs_mask = MMC_UHS_MASK_DDR50,
+       .max_clk_limit = 102000000,
+       /*      .max_clk = 12000000, */
 };
 
 static int vcm30_t124_wifi_status_register(
@@ -203,14 +211,15 @@ int __init vcm30_t124_sdhci_init(void)
        tegra_sdhci_device3.dev.platform_data = &tegra_sdhci_platform_data3;
        tegra_sdhci_device4.dev.platform_data = &tegra_sdhci_platform_data4;
 
-       is_e1860 = tegra_is_board(NULL, "61860", NULL, NULL, NULL);
-       if (is_e1860)
-               tegra_sdhci_platform_data3.mmc_data.ocr_mask = MMC_OCR_3V2_MASK;
+/* FIXME: Enable this check after SKU support is working */
+/*     is_e1860 = tegra_is_board(NULL, "61860", NULL, NULL, NULL);
+       if (is_e1860)*/
+               tegra_sdhci_platform_data3.mmc_data.ocr_mask = MMC_OCR_3V3_MASK;
 
-       platform_device_register(&tegra_sdhci_device1);
-       platform_device_register(&tegra_sdhci_device2);
+/*     platform_device_register(&tegra_sdhci_device1); */
+/*     platform_device_register(&tegra_sdhci_device2); */
        platform_device_register(&tegra_sdhci_device3);
-       platform_device_register(&tegra_sdhci_device4);
+/*     platform_device_register(&tegra_sdhci_device4); */
 
        return 0;
 }
index 0d9ef4b..cbdc733 100644 (file)
 #include <linux/i2c.h>
 #include <linux/platform_data/serial-tegra.h>
 #include <linux/platform_data/tegra_usb.h>
+#include <linux/platform_data/tegra_nor.h>
+#include <linux/platform_data/tegra_ahci.h>
 #include <linux/spi/spi-tegra.h>
 #include <linux/of_platform.h>
+#include <linux/kernel.h>
 
 #include <mach/tegra_asoc_pdata.h>
 #include <mach/pci.h>
@@ -78,6 +81,7 @@ static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
        { "uartb",      "pll_p",        408000000,      false},
        { "uartc",      "pll_p",        408000000,      false},
        { "uartd",      "pll_p",        408000000,      false},
+       { "nor",        "pll_p",        102000000,      true},
        { NULL,         NULL,           0,              0},
 };
 
@@ -112,6 +116,58 @@ static struct tegra_i2c_platform_data vcm30_t124_i2c5_platform_data = {
        .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
 };
 
+static struct tegra_nor_platform_data vcm30_t124_nor_data = {
+       .flash = {
+               .map_name = "cfi_probe",
+               .width = 2,
+       },
+       .chip_parms = {
+               .MuxMode = NorMuxMode_ADNonMux,
+               .ReadMode = NorReadMode_Page,
+               .PageLength = NorPageLength_8Word,
+               .ReadyActive = NorReadyActive_WithData,
+               /* FIXME: Need to use characterized value */
+               .timing_default = {
+                       .timing0 = 0x30300273,
+                       .timing1 = 0x00030302,
+               },
+               .timing_read = {
+                       .timing0 = 0x30300273,
+                       .timing1 = 0x00030302,
+               },
+       },
+};
+
+static struct cs_info vcm30_t124_cs_info[] = {
+       {
+               .cs = CS_0,
+               .num_cs_gpio = 0,
+               .virt = IO_ADDRESS(TEGRA_NOR_FLASH_BASE),
+               .size = SZ_64M,
+               .phys = TEGRA_NOR_FLASH_BASE,
+       },
+};
+
+static void vcm30_t124_nor_init(void)
+{
+       tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
+
+       vcm30_t124_nor_data.info.cs = kzalloc(sizeof(struct cs_info) *
+                                       ARRAY_SIZE(vcm30_t124_cs_info),
+                                       GFP_KERNEL);
+        if (!vcm30_t124_nor_data.info.cs)
+                BUG();
+
+        vcm30_t124_nor_data.info.num_chips = ARRAY_SIZE(vcm30_t124_cs_info);
+
+        memcpy(vcm30_t124_nor_data.info.cs, vcm30_t124_cs_info,
+                                sizeof(struct cs_info) * ARRAY_SIZE(vcm30_t124_cs_info));
+
+       tegra_nor_device.dev.platform_data = &vcm30_t124_nor_data;
+       platform_device_register(&tegra_nor_device);
+}
+
+
 static void vcm30_t124_i2c_init(void)
 {
        struct board_info board_info;
@@ -225,6 +281,20 @@ static void vcm30_t124_pcie_init(void)
 #endif
 }
 
+#ifdef CONFIG_SATA_AHCI_TEGRA
+static struct tegra_ahci_platform_data ahci_plat_data = {
+        .gen2_rx_eq = 7,
+};
+
+static void vcm30_t124_sata_init(void)
+{
+        tegra_sata_device.dev.platform_data = &ahci_plat_data;
+        platform_device_register(&tegra_sata_device);
+}
+#else
+static void vcm30_t124_sata_init(void) { }
+#endif
+
 /* FIXME: Check which devices are needed from the below list */
 static struct platform_device *vcm30_t124_devices[] __initdata = {
        &tegra_pmu_device,
@@ -410,13 +480,14 @@ static void __init tegra_vcm30_t124_late_init(void)
        vcm30_t124_pinmux_init();
        vcm30_t124_usb_init();
 /*     vcm30_t124_xusb_init(); */
+       vcm30_t124_nor_init();
        vcm30_t124_i2c_init();
        vcm30_t124_spi_init();
        vcm30_t124_uart_init();
        platform_add_devices(vcm30_t124_devices,
                        ARRAY_SIZE(vcm30_t124_devices));
        tegra_io_dpd_init();
-       /* vcm30_t124_sdhci_init(); */
+       vcm30_t124_sdhci_init();
        vcm30_t124_regulator_init();
        /* vcm30_t124_suspend_init(); */
 #if 0
@@ -427,6 +498,7 @@ static void __init tegra_vcm30_t124_late_init(void)
        /* vcm30_t124_panel_init(); */
        /* vcm30_t124_pmon_init(); */
        vcm30_t124_pcie_init();
+       vcm30_t124_sata_init();
 #ifdef CONFIG_TEGRA_WDT_RECOVERY
        tegra_wdt_recovery_init();
 #endif