arm: tegra: decouple MCLK from vi device
David Schalig [Thu, 30 May 2013 08:24:38 +0000 (17:24 +0900)]
Allow clocks vi_sensor and vi_sensor2 to be used from any device,
not only tegra_camera (vi) device. This is a prerequisite to
move sensor MCLK control into sensor drivers, and to use MCLK for
non-camera devices.

Also, the default recommendation for camera MCLK is different
between T20/T30/T114 and T148: On T148 cameras should use vi_sensor2
while on other Tegra families it should be vi_sensor. Thus
create a clock alias 'default_mclk', to allow sensor drivers without
explicit MCLK config default to the right one.

Bug 1298672

Change-Id: Ifda4d39d927560e2f2c50c953f2a9c372e9cf72c
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/234044
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra14_clocks.c

index bce6ba9..b3c8df5 100644 (file)
@@ -6883,7 +6883,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
        PERIPH_CLK_EX("vi",     "vi",                   "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "vi",                   "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK("vi_sensor", NULL,                   "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
@@ -7169,6 +7169,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
        CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
        CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
+       CLK_DUPLICATE("vi_sensor", NULL, "default_mclk"),
 };
 
 struct clk *tegra_ptr_clks[] = {
index 9d74291..c97ee43 100644 (file)
@@ -6401,9 +6401,9 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  408000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  800000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  800000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-       PERIPH_CLK_EX("vi",     "vi",           "vi",   20,     0x148,  800000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "vi",           "vi_sensor",    164,    0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("vi_sensor2",        "vi",           "vi_sensor2",   165,    0x658,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK_EX("vi",     "vi",                   "vi",   20,     0x148,  800000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+       PERIPH_CLK("vi_sensor", NULL,                   "vi_sensor",    164,    0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK("vi_sensor2",NULL,                   "vi_sensor2",   165,    0x658,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  800000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
@@ -6599,6 +6599,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("csus", "touch_clk", "e1680_ts_clk_con"),
        CLK_DUPLICATE("dmic0", "tegra-dmic.0", NULL),
        CLK_DUPLICATE("dmic1", "tegra-dmic.1", NULL),
+       CLK_DUPLICATE("vi_sensor2", NULL, "default_mclk"),
 };
 
 struct clk *tegra_ptr_clks[] = {