ARM: tegra: clock: Add read fence in delayed writes
Alex Frid [Thu, 5 Sep 2013 03:02:35 +0000 (20:02 -0700)]
Added explicit read fence after clock register writes that include
propagation delay. This is necessary on Tegra11 and Tegra12 platforms
where udelay implementation is based on CPU arch timers (on platforms
that use tegra microsecond timer for udelay, timer count read serves
as a fence).

Change-Id: I56a9af1bfa5ae7a9f6f51d129708eaa5cbd8ee27
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270481
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra12_clocks.c

index a40b1d7..48c33c5 100644 (file)
@@ -596,13 +596,15 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), reg_clk_base + (reg));    \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(2);                                              \
        } while (0)
 
 #define pll_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), reg_clk_base + (reg));    \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(1);                                              \
        } while (0)
 
index 454822c..948fb82 100644 (file)
@@ -656,13 +656,15 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), (void *)((u32)reg_clk_base + (reg)));     \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(2);                                              \
        } while (0)
 
 #define pll_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), (void *)((u32)reg_clk_base + (reg)));     \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(1);                                              \
        } while (0)