Revert "iommu/tegra: smmu: Add device tree support for SMMU"
Dan Willemsen [Wed, 6 Feb 2013 05:24:32 +0000 (21:24 -0800)]
This reverts commit 0760e8faa960f8ee991fa4acb802db4e20661281.

Change-Id: I92e01b224d9fcec75636e24f505a21962f14b8bf
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt [deleted file]
drivers/iommu/Kconfig
drivers/iommu/tegra-smmu.c

diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt
deleted file mode 100644 (file)
index 89fb543..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
-
-Required properties:
-- compatible : "nvidia,tegra30-smmu"
-- reg : Should contain 3 register banks(address and length) for each
-  of the SMMU register blocks.
-- interrupts : Should contain MC General interrupt.
-- nvidia,#asids : # of ASIDs
-- dma-window : IOVA start address and length.
-- nvidia,ahb : phandle to the ahb bus connected to SMMU.
-
-Example:
-       smmu {
-               compatible = "nvidia,tegra30-smmu";
-               reg = <0x7000f010 0x02c
-                      0x7000f1f0 0x010
-                      0x7000f228 0x05c>;
-               nvidia,#asids = <4>;            /* # of ASIDs */
-               dma-window = <0 0x40000000>;    /* IOVA start & length */
-               nvidia,ahb = <&ahb>;
-       };
index 4e99a85..62f1ff0 100644 (file)
@@ -158,7 +158,7 @@ config TEGRA_IOMMU_GART
 
 config TEGRA_IOMMU_SMMU
        bool "Tegra SMMU IOMMU Support"
-       depends on ARCH_TEGRA && TEGRA_AHB
+       depends on ARCH_TEGRA
        select IOMMU_API
        help
          Enables support for remapping discontiguous physical memory
index 4d8b444..f714505 100644 (file)
@@ -30,8 +30,6 @@
 #include <linux/sched.h>
 #include <linux/iommu.h>
 #include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_iommu.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/tegra-ahb.h>
@@ -164,6 +162,12 @@ enum {
 
 #define SMMU_PDE_NEXT_SHIFT            28
 
+/* AHB Arbiter Registers */
+#define AHB_XBAR_CTRL                          0xe0
+#define AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE      1
+#define AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT     17
+
+#define SMMU_NUM_ASIDS                         4
 #define SMMU_TLB_FLUSH_VA_SECTION__MASK                0xffc00000
 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT       12 /* right shift */
 #define SMMU_TLB_FLUSH_VA_GROUP__MASK          0xffffc000
@@ -183,7 +187,6 @@ enum {
 
 #define SMMU_PAGE_SHIFT 12
 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
-#define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
 
 #define SMMU_PDIR_COUNT        1024
 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
@@ -232,8 +235,6 @@ enum {
 #define SMMU_ASID_DISABLE      0
 #define SMMU_ASID_ASID(n)      ((n) & ~SMMU_ASID_ENABLE(0))
 
-#define NUM_SMMU_REG_BANKS     3
-
 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
 #define smmu_client_disable_hwgrp(c)   smmu_client_set_hwgrp(c, 0, 0)
 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
@@ -323,7 +324,7 @@ struct smmu_debugfs_info {
  * Per SMMU device - IOMMU device
  */
 struct smmu_device {
-       void __iomem    *regs[NUM_SMMU_REG_BANKS];
+       void __iomem    *regs, *regs_ahbarb;
        unsigned long   iovmm_base;     /* remappable base address */
        unsigned long   page_count;     /* total remappable size */
        spinlock_t      lock;
@@ -342,8 +343,6 @@ struct smmu_device {
        struct dentry *debugfs_root;
        struct smmu_debugfs_info *debugfs_info;
 
-       struct device_node *ahb;
-
        int             num_as;
        struct smmu_as  as[0];          /* Run-time allocated array */
 };
@@ -351,40 +350,24 @@ struct smmu_device {
 static struct smmu_device *smmu_handle; /* unique for a system */
 
 /*
- *     SMMU register accessors
+ *     SMMU/AHB register accessors
  */
 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
 {
-       BUG_ON(offs < 0x10);
-       if (offs < 0x3c)
-               return readl(smmu->regs[0] + offs - 0x10);
-       BUG_ON(offs < 0x1f0);
-       if (offs < 0x200)
-               return readl(smmu->regs[1] + offs - 0x1f0);
-       BUG_ON(offs < 0x228);
-       if (offs < 0x284)
-               return readl(smmu->regs[2] + offs - 0x228);
-       BUG();
+       return readl(smmu->regs + offs);
 }
-
 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
 {
-       BUG_ON(offs < 0x10);
-       if (offs < 0x3c) {
-               writel(val, smmu->regs[0] + offs - 0x10);
-               return;
-       }
-       BUG_ON(offs < 0x1f0);
-       if (offs < 0x200) {
-               writel(val, smmu->regs[1] + offs - 0x1f0);
-               return;
-       }
-       BUG_ON(offs < 0x228);
-       if (offs < 0x284) {
-               writel(val, smmu->regs[2] + offs - 0x228);
-               return;
-       }
-       BUG();
+       writel(val, smmu->regs + offs);
+}
+
+static inline u32 ahb_read(struct smmu_device *smmu, size_t offs)
+{
+       return readl(smmu->regs_ahbarb + offs);
+}
+static inline void ahb_write(struct smmu_device *smmu, u32 val, size_t offs)
+{
+       writel(val, smmu->regs_ahbarb + offs);
 }
 
 #define VA_PAGE_TO_PA(va, page)        \
@@ -488,7 +471,7 @@ static void smmu_flush_regs(struct smmu_device *smmu, int enable)
        FLUSH_SMMU_REGS(smmu);
 }
 
-static int smmu_setup_regs(struct smmu_device *smmu)
+static void smmu_setup_regs(struct smmu_device *smmu)
 {
        int i;
        u32 val;
@@ -516,7 +499,10 @@ static int smmu_setup_regs(struct smmu_device *smmu)
 
        smmu_flush_regs(smmu, 1);
 
-       return tegra_ahb_enable_smmu(smmu->ahb);
+       val = ahb_read(smmu, AHB_XBAR_CTRL);
+       val |= AHB_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
+               AHB_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
+       ahb_write(smmu, val, AHB_XBAR_CTRL);
 }
 
 static void flush_ptc_and_tlb(struct smmu_device *smmu,
@@ -1178,21 +1164,20 @@ static int tegra_smmu_resume(struct device *dev)
 {
        struct smmu_device *smmu = dev_get_drvdata(dev);
        unsigned long flags;
-       int err;
 
        spin_lock_irqsave(&smmu->lock, flags);
-       err = smmu_setup_regs(smmu);
+       smmu_setup_regs(smmu);
        spin_unlock_irqrestore(&smmu->lock, flags);
-       return err;
+       return 0;
 }
 
 static int tegra_smmu_probe(struct platform_device *pdev)
 {
        struct smmu_device *smmu;
+       struct resource *regs, *regs2, *window;
        struct device *dev = &pdev->dev;
-       int i, asids, err = 0;
-       dma_addr_t uninitialized_var(base);
-       size_t bytes, uninitialized_var(size);
+       int i;
+       size_t bytes;
 
        if (smmu_handle)
                return -EIO;
@@ -1216,46 +1201,32 @@ static int tegra_smmu_probe(struct platform_device *pdev)
 
        BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
 
-       if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
+       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       regs2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+       window = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+       if (!regs || !regs2 || !window) {
+               dev_err(dev, "No SMMU resources\n");
                return -ENODEV;
+       }
 
-       bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
+       bytes = sizeof(*smmu) + SMMU_NUM_ASIDS * sizeof(*smmu->as);
        smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
        if (!smmu) {
                dev_err(dev, "failed to allocate smmu_device\n");
                return -ENOMEM;
        }
 
-       for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) {
-               struct resource *res;
-
-               res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-               if (!res)
-                       return -ENODEV;
-               smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
-               if (!smmu->regs[i])
-                       return -EBUSY;
-       }
-
-       err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
-       if (err)
-               return -ENODEV;
-
-       if (size & SMMU_PAGE_MASK)
-               return -EINVAL;
-
-       size >>= SMMU_PAGE_SHIFT;
-       if (!size)
-               return -EINVAL;
-
-       smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
-       if (!smmu->ahb)
-               return -ENODEV;
-
        smmu->dev = dev;
-       smmu->num_as = asids;
-       smmu->iovmm_base = base;
-       smmu->page_count = size;
+       smmu->num_as = SMMU_NUM_ASIDS;
+       smmu->iovmm_base = (unsigned long)window->start;
+       smmu->page_count = resource_size(window) >> SMMU_PAGE_SHIFT;
+       smmu->regs = devm_ioremap(dev, regs->start, resource_size(regs));
+       smmu->regs_ahbarb = devm_ioremap(dev, regs2->start,
+                                        resource_size(regs2));
+       if (!smmu->regs || !smmu->regs_ahbarb) {
+               dev_err(dev, "failed to remap SMMU registers\n");
+               return -ENXIO;
+       }
 
        smmu->translation_enable_0 = ~0;
        smmu->translation_enable_1 = ~0;
@@ -1276,9 +1247,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)
                INIT_LIST_HEAD(&as->client);
        }
        spin_lock_init(&smmu->lock);
-       err = smmu_setup_regs(smmu);
-       if (err)
-               return err;
+       smmu_setup_regs(smmu);
        platform_set_drvdata(pdev, smmu);
 
        smmu->avp_vector_page = alloc_page(GFP_KERNEL);
@@ -1311,14 +1280,6 @@ const struct dev_pm_ops tegra_smmu_pm_ops = {
        .resume         = tegra_smmu_resume,
 };
 
-#ifdef CONFIG_OF
-static struct of_device_id tegra_smmu_of_match[] = {
-       { .compatible = "nvidia,tegra30-smmu", },
-       { },
-};
-MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
-#endif
-
 static struct platform_driver tegra_smmu_driver = {
        .probe          = tegra_smmu_probe,
        .remove         = tegra_smmu_remove,
@@ -1326,7 +1287,6 @@ static struct platform_driver tegra_smmu_driver = {
                .owner  = THIS_MODULE,
                .name   = "tegra_smmu",
                .pm     = &tegra_smmu_pm_ops,
-               .of_match_table = of_match_ptr(tegra_smmu_of_match),
        },
 };
 
@@ -1402,5 +1362,4 @@ module_exit(tegra_smmu_exit);
 
 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
-MODULE_ALIAS("platform:tegra-smmu");
 MODULE_LICENSE("GPL v2");