Arm: Tegra: Roth: Support Roth platform
Pavan Kunapuli [Fri, 9 Nov 2012 09:00:59 +0000 (14:00 +0530)]
Adding initial support for Roth platform
based on dalmore platform.

Populate power tree based on board design for roth.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

Bug 1169149

Change-Id: I2e14b464cc199c59a246500388fb1480866e10a3
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/160908
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/board-dalmore.c
arch/arm/mach-tegra/board-roth-memory.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-pinmux-t11x.h [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-powermon.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-sdhci.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth-sensors.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth.c [new file with mode: 0644]
arch/arm/mach-tegra/board-roth.h

index 50289f4..320a25c 100644 (file)
@@ -187,6 +187,14 @@ config MACH_TEGRA_PLUTO
        help
          Support for NVIDIA PLUTO development platform
 
+config MACH_ROTH
+       bool "Thor board"
+       depends on ARCH_TEGRA_11x_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+       help
+         Support for NVIDIA THOR development platform
+
 choice
        prompt "Tegra platform type"
        default TEGRA_SILICON_PLATFORM
index 0bf681c..bfec21e 100644 (file)
@@ -71,7 +71,6 @@
 #include "board-common.h"
 #include "clock.h"
 #include "board-dalmore.h"
-#include "board-roth.h"
 #include "devices.h"
 #include "gpio-names.h"
 #include "fuse.h"
@@ -671,9 +670,6 @@ static int __init dalmore_touch_init(void)
 
 static void __init tegra_dalmore_init(void)
 {
-       struct board_info board_info;
-
-       tegra_get_display_board_info(&board_info);
        tegra_battery_edp_init(2500);
        tegra_clk_init_from_table(dalmore_clk_init_table);
        tegra_soc_device_init("dalmore");
@@ -693,10 +689,7 @@ static void __init tegra_dalmore_init(void)
        dalmore_suspend_init();
        dalmore_emc_init();
        dalmore_touch_init();
-       if (board_info.board_id == BOARD_E1582)
-               roth_panel_init();
-       else
-               dalmore_panel_init();
+       dalmore_panel_init();
        dalmore_kbc_init();
        dalmore_pmon_init();
        dalmore_setup_bluesleep();
diff --git a/arch/arm/mach-tegra/board-roth-memory.c b/arch/arm/mach-tegra/board-roth-memory.c
new file mode 100644 (file)
index 0000000..cc1e5e0
--- /dev/null
@@ -0,0 +1,460 @@
+/*
+ * Copyright (C) 2012 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_data/tegra_emc.h>
+
+#include "board.h"
+#include "board-roth.h"
+
+#include "tegra-board-id.h"
+#include "tegra11_emc.h"
+#include "fuse.h"
+#include "devices.h"
+
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_table[] = {
+       {
+               0x40,       /* Rev 4.0 */
+               204000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000002, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000009, /* EMC_RC */
+                       0x00000035, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000032, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000038, /* EMC_TXSR */
+                       0x00000038, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000009, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x000000a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00054000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05055504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x01000003, /* MC_EMEM_ARB_CFG */
+                       0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73840a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000006, /* EMC_EINPUT */
+                       0x00000002, /* EMC_EINPUT_DURATION */
+                       0x00054000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000006, /* EMC_EINPUT */
+                       0x00000002, /* EMC_EINPUT_DURATION */
+                       0x00054000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00054000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+       },
+       {
+               0x40,       /* Rev 4.0 */
+               408000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000014, /* EMC_RC */
+                       0x00000073, /* EMC_RFC */
+                       0x0000000a, /* EMC_RFC_SLR */
+                       0x0000000f, /* EMC_RAS */
+                       0x00000006, /* EMC_RP */
+                       0x00000009, /* EMC_R2W */
+                       0x0000000d, /* EMC_W2R */
+                       0x00000004, /* EMC_R2P */
+                       0x0000000e, /* EMC_W2P */
+                       0x00000006, /* EMC_RD_RCD */
+                       0x00000006, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000002, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000009, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000006, /* EMC_QRST */
+                       0x0000000f, /* EMC_RDV_MASK */
+                       0x00000bcb, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000005, /* EMC_PDEX2WR */
+                       0x0000000c, /* EMC_PDEX2RD */
+                       0x00000005, /* EMC_PCHG2PDEN */
+                       0x00000004, /* EMC_ACT2PDEN */
+                       0x0000006a, /* EMC_AR2PDEN */
+                       0x00000015, /* EMC_RW2PDEN */
+                       0x00000079, /* EMC_TXSR */
+                       0x0000020a, /* EMC_TXSRDLL */
+                       0x00000008, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000015, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000006, /* EMC_TCLKSTABLE */
+                       0x00000007, /* EMC_TCLKSTOP */
+                       0x00000cd4, /* EMC_TREFBW */
+                       0x00000107, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x001c0084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x00000125, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05055504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0158000c, /* EMC_MRS_WAIT_CNT */
+                       0x0158000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000808, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x02000006, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x07050303, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00110a0c, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7007130d, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000009, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000007, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x00145145, /* EMC_XM2DQSPADCTRL4 */
+                       0x18618600, /* EMC_XM2DQSPADCTRL3 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10b0b, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000009, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000007, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x00145145, /* EMC_XM2DQSPADCTRL4 */
+                       0x18618600, /* EMC_XM2DQSPADCTRL3 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10b0b, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x0320000e, /* EMC_CFG */
+               0x80000731, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+       },
+};
+
+static struct tegra11_emc_pdata e1613_h9ccnnn8jtmlar_ntm_pdata = {
+       .description = "e1613_h9ccnnn8jtmlar_ntm",
+};
+
+static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_pdata = {
+       .description = "e1611_h5tc4g63mfr_pba",
+       .tables = e1611_h5tc4g63mfr_pba_table,
+       .num_tables = ARRAY_SIZE(e1611_h5tc4g63mfr_pba_table),
+};
+
+static struct tegra11_emc_pdata *roth_get_emc_data(void)
+{
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+
+       if (board_info.board_id == BOARD_E1611 ||
+               board_info.board_id == BOARD_P2454)
+               return &e1611_h5tc4g63mfr_pba_pdata;
+
+       return &e1613_h9ccnnn8jtmlar_ntm_pdata;
+}
+
+int __init roth_emc_init(void)
+{
+       tegra_emc_device.dev.platform_data = roth_get_emc_data();
+       platform_device_register(&tegra_emc_device);
+       tegra11_emc_init();
+       return 0;
+}
+#else
+int __init roth_emc_init(void)
+{
+       return 0;
+}
+#endif /* CONFIG_ARCH_TEGRA_11x_SOC */
diff --git a/arch/arm/mach-tegra/board-roth-pinmux-t11x.h b/arch/arm/mach-tegra/board-roth-pinmux-t11x.h
new file mode 100644 (file)
index 0000000..c996a6f
--- /dev/null
@@ -0,0 +1,291 @@
+/*
+ * arch/arm/mach-tegra/board-roth-pinmux-t11x.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth floor, Boston, MA  02110-1301, USA
+ */
+
+static __initdata struct tegra_pingroup_config roth_pinmux_common[] = {
+
+       /* EXTPERIPH1 pinmux */
+       DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S0 pinmux */
+       DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S1 pinmux */
+       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S3 pinmux */
+       DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+       /* CLDVFS pinmux */
+       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* ULPI pinmux */
+       DEFAULT_PINMUX(ULPI_CLK,      ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DIR,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_STP,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* VI pinmux */
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VI_ALT1 pinmux */
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VGP4 pinmux */
+       VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* UARTD pinmux */
+       DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI4 pinmux */
+       DEFAULT_PINMUX(GMI_AD5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD6,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD7,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD12,      RSVD1,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,     SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_WR_N,      SPI4,        NORMAL,    NORMAL,   INPUT),
+
+       /* PWM1 pinmux */
+       DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* SOC pinmux */
+       DEFAULT_PINMUX(GMI_CS1_N,     SOC,         NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_OE_N,      SOC,         NORMAL,    TRISTATE, INPUT),
+
+       /* EXTPERIPH2 pinmux */
+       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_COL4,       SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+
+       /* BLINK pinmux */
+       DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* KBC pinmux */
+       DEFAULT_PINMUX(KB_COL0,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL1,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL2,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW0,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW1,       KBC,         PULL_UP,   NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW2,       KBC,         PULL_UP,   NORMAL, INPUT),
+
+       /*Audio Codec*/
+       DEFAULT_PINMUX(DAP3_DIN,      RSVD,   NORMAL,    TRISTATE,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,     RSVD,   NORMAL,    TRISTATE,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV0,      RSVD,   NORMAL,    TRISTATE,    OUTPUT),
+       DEFAULT_PINMUX(KB_ROW7,       RSVD,   PULL_UP,   NORMAL,      INPUT),
+
+       /* UARTA pinmux */
+       DEFAULT_PINMUX(KB_ROW10,      UARTA,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2CPWR pinmux */
+       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* SYSCLK pinmux */
+       DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* RTCK pinmux */
+       DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL, INPUT),
+
+       /* CLK pinmux */
+       DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+       /* PWRON pinmux */
+       DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* CPU pinmux */
+       DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+       /* PMI pinmux */
+       DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+       /* RESET_OUT_N pinmux */
+       DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+       /* EXTPERIPH3 pinmux */
+       DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* UARTB pinmux */
+       DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* IRDA pinmux */
+       DEFAULT_PINMUX(UART2_RXD,     IRDA,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_TXD,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* UARTC pinmux */
+       DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* OWR pinmux */
+       DEFAULT_PINMUX(OWR,           OWR,         NORMAL,    NORMAL,   INPUT),
+
+       /* CEC pinmux */
+       CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* I2C4 pinmux */
+       DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+       DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+
+       /* USB pinmux */
+       USB_PINMUX(SPDIF_IN, USB, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE),
+       USB_PINMUX(USB_VBUS_EN0, USB, PULL_UP, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* nct */
+       DEFAULT_PINMUX(GPIO_X6_AUD,   SPI6,        PULL_UP,   TRISTATE, INPUT),
+};
+
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+       DEFAULT_PINMUX(CLK1_REQ,      RSVD3,       PULL_DOWN, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(USB_VBUS_EN1,  RSVD3,       PULL_DOWN, TRISTATE, OUTPUT),
+};
+
+static struct gpio_init_pin_info init_gpio_mode_roth_common[] = {
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP2, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH2, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PS0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK5, true, 1),
+};
diff --git a/arch/arm/mach-tegra/board-roth-pinmux.c b/arch/arm/mach-tegra/board-roth-pinmux.c
new file mode 100644 (file)
index 0000000..12cf5b5
--- /dev/null
@@ -0,0 +1,686 @@
+/*
+ * arch/arm/mach-tegra/board-roth-pinmux.c
+ *
+ * Copyright (C) 2012 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <mach/pinmux.h>
+#include <mach/gpio-tegra.h>
+#include "board.h"
+#include "board-roth.h"
+#include "devices.h"
+#include "gpio-names.h"
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+#include <mach/pinmux-t11.h>
+#else
+#include <mach/pinmux-tegra30.h>
+#endif
+
+#define DEFAULT_DRIVE(_name)                                   \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_DISABLE,                       \
+               .schmitt = TEGRA_SCHMITT_ENABLE,                \
+               .drive = TEGRA_DRIVE_DIV_1,                     \
+               .pull_down = TEGRA_PULL_31,                     \
+               .pull_up = TEGRA_PULL_31,                       \
+               .slew_rising = TEGRA_SLEW_SLOWEST,              \
+               .slew_falling = TEGRA_SLEW_SLOWEST,             \
+       }
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+               .hsm = TEGRA_HSM_##_hsm,                    \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,        \
+               .drive = TEGRA_DRIVE_##_drive,              \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,    \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * drive_type - Drive type to be used depending on the resistors.
+ */
+
+#define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
+               _pullup_drive, _pulldn_slew, _pullup_slew, _drive_type) \
+       {                                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,               \
+               .hsm = TEGRA_HSM_##_hsm,                                \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,                    \
+               .drive = TEGRA_DRIVE_##_drive,                          \
+                .pull_down = TEGRA_PULL_##_pulldn_drive,               \
+               .pull_up = TEGRA_PULL_##_pullup_drive,                  \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,               \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,              \
+               .drive_type = TEGRA_DRIVE_TYPE_##_drive_type,           \
+       }
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_DEFAULT,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_##_od,           \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .rcv_sel        = TEGRA_PIN_RCV_SEL_##_rcv_sel,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
+       }
+
+#define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od)   \
+       {                                                               \
+               .pingroup   = TEGRA_PINGROUP_##_pingroup,                   \
+               .func       = TEGRA_MUX_##_mux,                             \
+               .pupd       = TEGRA_PUPD_##_pupd,                           \
+               .tristate   = TEGRA_TRI_##_tri,                             \
+               .io         = TEGRA_PIN_##_io,                              \
+               .lock       = TEGRA_PIN_LOCK_##_lock,                       \
+               .od         = TEGRA_PIN_OD_##_od,                           \
+               .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,                   \
+       }
+
+#define USB_PINMUX CEC_PINMUX
+
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)   \
+       {                                       \
+               .gpio_nr        = _gpio,        \
+               .is_input       = _is_input,    \
+               .value          = _value,       \
+       }
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+
+static __initdata struct tegra_drive_pingroup_config roth_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1, DISABLE, DISABLE, DIV_1, 36, 20, SLOW, SLOW),
+
+       /* SDMMC3 */
+       SET_DRIVE(SDIO3, DISABLE, DISABLE, DIV_1, 22, 36, FASTEST, FASTEST),
+
+       /* SDMMC4 */
+       SET_DRIVE_WITH_TYPE(GMA, DISABLE, DISABLE, DIV_1, 2, 1, FASTEST, FASTEST, 1),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static __initdata struct tegra_pingroup_config roth_pinmux_set_nontristate[] = {
+       DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_X5_AUD,     RSVD,   PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X6_AUD,     RSVD3,  PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_W3_AUD,     SPI6,   PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X1_AUD,     RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  PULL_UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,   PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,        RSVD,   NORMAL,       NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GPIO_PBB3,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       RSVD3,  PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       RSVD3,  PULL_DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GMI_AD0,         GMI,    NORMAL,       NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,         GMI,    NORMAL,       NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD10,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD12,        GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,         GMI,    NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD3,         GMI,    NORMAL,       NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD8,         GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CLK,         GMI,    PULL_DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       GMI,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_DQS_P,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,       GMI,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        GMI,    PULL_UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(SDMMC1_WP_N,     SPI4,   PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,       NORMAL,    OUTPUT),
+
+       DEFAULT_PINMUX(KB_COL3,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,    PULL_UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,    PULL_UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_ROW3,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,    PULL_DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(CLK3_REQ,        RSVD3,  NORMAL,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(HDMI_INT,        RSVD,   PULL_DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GMI_AD9,         PWM1,   NORMAL,    NORMAL,     OUTPUT),
+};
+
+#include "board-roth-pinmux-t11x.h"
+
+#else
+
+/* !!!FIXME!!!! POPULATE THIS TABLE */
+static __initdata struct tegra_drive_pingroup_config roth_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+       /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */
+       SET_DRIVE(DAP2,         DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* All I2C pins are driven to maximum drive strength */
+       /* GEN1 I2C */
+       SET_DRIVE(DBG,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* GEN2 I2C */
+       SET_DRIVE(AT5,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* CAM I2C */
+       SET_DRIVE(GME,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* DDC I2C */
+       SET_DRIVE(DDC,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* PWR_I2C */
+       SET_DRIVE(AO1,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* UART3 */
+       SET_DRIVE(UART3,        DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1,        DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+       /* SDMMC3 */
+       SET_DRIVE(SDIO3,        DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+       /* SDMMC4 */
+       SET_DRIVE(GMA,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMB,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMC,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMD,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+
+};
+
+static __initdata struct tegra_pingroup_config roth_pinmux_common[] = {
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT6,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT7,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,      SDMMC4,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,      SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_RST_N,    RSVD1,           PULL_DOWN,  NORMAL,     INPUT),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL,        I2C1,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(GEN1_I2C_SDA,        I2C1,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL,        I2C2,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(GEN2_I2C_SDA,        I2C2,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL,         I2C3,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(CAM_I2C_SDA,         I2C3,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C4 pinmux */
+       I2C_PINMUX(DDC_SCL,             I2C4,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(DDC_SDA,             I2C4,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* Power I2C pinmux */
+       I2C_PINMUX(PWR_I2C_SCL,         I2CPWR,         NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(PWR_I2C_SDA,         I2CPWR,         NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* LCD */
+       DEFAULT_PINMUX(LCD_PCLK,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DE,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_HSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_VSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D0,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D1,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D2,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D3,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D4,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D5,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D6,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D7,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D8,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D9,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D10,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D11,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D12,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D13,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D14,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D15,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D16,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D17,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D18,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D19,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D20,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D21,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D22,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D23,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+
+       /* UART B : GPS */
+       DEFAULT_PINMUX(UART2_RXD,       IRDA,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_TXD,       IRDA,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,     UARTB,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_CTS_N,     UARTB,           NORMAL,    NORMAL,     INPUT),
+
+       /*UART C : BT */
+       DEFAULT_PINMUX(UART3_TXD,       UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,       UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_CTS_N,     UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,     UARTC,           NORMAL,    NORMAL,     OUTPUT),
+
+       /* UART D : DEBUG */
+       DEFAULT_PINMUX(GMI_A16,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A18,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A19,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+
+       /*  KBC keys */
+       DEFAULT_PINMUX(KB_COL0,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL1,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL2,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL3,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW0,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW1,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW2,         KBC,             PULL_UP,   NORMAL,     INPUT),
+
+       /* I2S0 : for MODEM */
+       DEFAULT_PINMUX(DAP1_FS,         I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DIN,        I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,       I2S0,            NORMAL,    NORMAL,     INPUT),
+
+       /* I2S1 : for CODEC */
+       DEFAULT_PINMUX(DAP2_FS,         I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DIN,        I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,       I2S1,            NORMAL,    NORMAL,     INPUT),
+
+       /* I2S3 : for BT */
+       DEFAULT_PINMUX(DAP4_FS,         I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DIN,        I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,       I2S3,            NORMAL,    NORMAL,     INPUT),
+
+       /* SPI1 : touch */
+       DEFAULT_PINMUX(SPI1_MOSI,       SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_SCK,        SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MISO,       SPI1,            NORMAL,    NORMAL,     INPUT),
+
+       /* SPIDIF */
+       DEFAULT_PINMUX(SPDIF_IN,        SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,           NORMAL,    NORMAL,     OUTPUT),
+
+       /* FIXED FUNCTION AND CONFIGURATION */
+       DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,          NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(OWR,             OWR,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD4,         RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_OUT,        EXTPERIPH1,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK2_OUT,        EXTPERIPH2,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK3_OUT,        EXTPERIPH3,      NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(HDMI_INT,        RSVD0,           NORMAL,    TRISTATE,   INPUT),
+
+       /* GPIO */
+       /* POWER RAIL GPIO */
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD14,        RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT5,     SDMMC3,          NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW7,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_M1,          DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR0,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR1,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR2,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+
+       /* CAMERA */
+       DEFAULT_PINMUX(CAM_MCLK,        VI_ALT2,         PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB3,       VGP3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       VGP5,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       VGP6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW5,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW9,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW10,        KBC,             NORMAL,    NORMAL,     OUTPUT),
+
+       /* MODEM */
+       DEFAULT_PINMUX(GPIO_PV0,        RSVD,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,        RSVD,            NORMAL,    NORMAL,     INPUT),
+
+       /* GPS and BT */
+       DEFAULT_PINMUX(GPIO_PU0,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU1,        RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU2,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU3,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        PWM1,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        PWM2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW14,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK3_REQ,        DEV3,            NORMAL,    NORMAL,     OUTPUT),
+
+       /* LCD GPIO */
+       DEFAULT_PINMUX(GMI_AD0,         RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,         RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD3,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD5,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD6,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD7,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD8,         PWM0,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD9,         RSVD2,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,        PWM3,            NORMAL,    NORMAL,     OUTPUT),
+
+       /* TOUCH */
+       DEFAULT_PINMUX(GMI_WAIT,        RSVD1,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        RSVD1,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDOUT,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DC1,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_WR_N,        DISPLAYA,        PULL_UP,   NORMAL,     INPUT),
+
+       /* SDMMC */
+       DEFAULT_PINMUX(GMI_IORDY,       RSVD1,           PULL_UP,   NORMAL,     INPUT),
+
+       /* CODEC */
+       DEFAULT_PINMUX(SPI2_SCK,        SPI2,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SPI2_CS1_N,      SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD12,        RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+
+       /* nct */
+       DEFAULT_PINMUX(SPI2_CS0_N,      SPI6,            PULL_UP,   TRISTATE,   INPUT),
+
+       /* OTHERS */
+       DEFAULT_PINMUX(KB_ROW3,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_DQS,         RSVD1,           NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(GMI_AD15,        RSVD1,           PULL_UP,   NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CLK,         RSVD1,           PULL_UP,   NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(GMI_RST_N,       NAND,            PULL_UP,   NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_DC0,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS0_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS1_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SCK,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDIN,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CRT_HSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CRT_VSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_WAKE_N,      PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,             NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(KB_ROW15,        KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SPI2_CS2_N,      SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MISO,       SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MOSI,       SPI2,            NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(KB_ROW11,        KBC,             PULL_UP,   TRISTATE,   INPUT),
+       DEFAULT_PINMUX(KB_ROW12,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_ROW13,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+};
+
+/*Do not use for now*/
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+       DEFAULT_PINMUX(ULPI_CLK,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA0,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_NXT,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_STP,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+
+       DEFAULT_PINMUX(GMI_AD10,        PWM2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD13,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(CLK1_REQ,        DAP,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS1_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,       NAND,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       NAND,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_OE_N,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_WR_N,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV2,        OWR,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV3,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL4,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D0,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D1,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D10,          VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D11,          VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D2,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D3,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D4,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D5,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D6,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D7,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D8,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D9,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_HSYNC,        VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_MCLK,         VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_PCLK,         VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_VSYNC,        VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+
+};
+
+
+static void __init roth_pinmux_audio_init(void)
+{
+       int ret = gpio_request(TEGRA_GPIO_CDC_IRQ, "rt5640");
+       if (ret < 0) {
+               pr_err("%s() Error in gpio_request() for gpio %d\n",
+                                __func__, ret);
+       }
+       ret = gpio_direction_input(TEGRA_GPIO_CDC_IRQ);
+       if (ret < 0) {
+               pr_err("%s() Error in setting gpio %d to in/out\n",
+                               __func__, ret);
+               gpio_free(TEGRA_GPIO_CDC_IRQ);
+       }
+
+}
+
+static struct gpio_init_pin_info init_gpio_mode_roth_common[] = {
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC7, false, 1),
+};
+
+#endif
+
+static void __init roth_gpio_init_configure(void)
+{
+       int len;
+       int i;
+       struct gpio_init_pin_info *pins_info;
+
+       len = ARRAY_SIZE(init_gpio_mode_roth_common);
+       pins_info = init_gpio_mode_roth_common;
+
+       for (i = 0; i < len; ++i) {
+               tegra_gpio_init_configure(pins_info->gpio_nr,
+                       pins_info->is_input, pins_info->value);
+               pins_info++;
+       }
+}
+
+int __init roth_pinmux_init(void)
+{
+       struct board_info board_info;
+       tegra_get_board_info(&board_info);
+       /*BUG_ON(board_info.board_id != BOARD_E1565);*/
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       tegra_pinmux_config_table(roth_pinmux_set_nontristate,
+                                       ARRAY_SIZE(roth_pinmux_set_nontristate));
+       roth_gpio_init_configure();
+
+       tegra_pinmux_config_table(roth_pinmux_common, ARRAY_SIZE(roth_pinmux_common));
+       tegra_drive_pinmux_config_table(roth_drive_pinmux,
+                                       ARRAY_SIZE(roth_drive_pinmux));
+       tegra_pinmux_config_table(unused_pins_lowpower,
+               ARRAY_SIZE(unused_pins_lowpower));
+
+#else
+       tegra30_default_pinmux();
+
+       roth_gpio_init_configure();
+
+       tegra_pinmux_config_table(roth_pinmux_common, ARRAY_SIZE(roth_pinmux_common));
+       tegra_drive_pinmux_config_table(roth_drive_pinmux,
+                                       ARRAY_SIZE(roth_drive_pinmux));
+
+       tegra_pinmux_config_table(unused_pins_lowpower,
+               ARRAY_SIZE(unused_pins_lowpower));
+       roth_pinmux_audio_init();
+#endif
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-roth-power.c b/arch/arm/mach-tegra/board-roth-power.c
new file mode 100644 (file)
index 0000000..43c0661
--- /dev/null
@@ -0,0 +1,793 @@
+/*
+ * arch/arm/mach-tegra/board-roth-power.c
+ *
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/palmas.h>
+#include <linux/regulator/tps51632-regulator.h>
+#include <linux/gpio.h>
+#include <linux/regulator/userspace-consumer.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/edp.h>
+#include <mach/gpio-tegra.h>
+
+#include "cpu-tegra.h"
+#include "pm.h"
+#include "tegra-board-id.h"
+#include "board.h"
+#include "gpio-names.h"
+#include "board-roth.h"
+#include "tegra_cl_dvfs.h"
+#include "devices.h"
+#include "tegra11_soctherm.h"
+
+#define PMC_CTRL               0x0
+#define PMC_CTRL_INTR_LOW      (1 << 17)
+
+/* TPS51632 DC-DC converter */
+static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
+       REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+static struct regulator_init_data tps51632_init_data = {
+       .constraints = {                                                \
+               .min_uV = 500000,                                       \
+               .max_uV = 1520000,                                      \
+               .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
+                                       REGULATOR_MODE_STANDBY),        \
+               .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
+                                       REGULATOR_CHANGE_STATUS |       \
+                                       REGULATOR_CHANGE_VOLTAGE),      \
+               .always_on = 1,                                         \
+               .boot_on =  1,                                          \
+               .apply_uV = 0,                                          \
+       },                                                              \
+       .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
+               .consumer_supplies = tps51632_dcdc_supply,              \
+};
+
+static struct tps51632_regulator_platform_data tps51632_pdata = {
+       .reg_init_data = &tps51632_init_data,           \
+       .enable_pwm = false,                            \
+       .max_voltage_uV = 1520000,                      \
+       .base_voltage_uV = 500000,                      \
+       .slew_rate_uv_per_us = 6000,                    \
+};
+
+static struct i2c_board_info __initdata tps51632_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("tps51632", 0x43),
+               .platform_data  = &tps51632_pdata,
+       },
+};
+
+/************************ Palmas based regulator ****************/
+static struct regulator_consumer_supply palmas_smps12_supply[] = {
+       REGULATOR_SUPPLY("vddio_ddr0", NULL),
+       REGULATOR_SUPPLY("vddio_ddr1", NULL),
+};
+
+static struct regulator_consumer_supply palmas_smps3_supply[] = {
+       REGULATOR_SUPPLY("avdd_osc", NULL),
+       REGULATOR_SUPPLY("vddio_sys", NULL),
+       REGULATOR_SUPPLY("vddio_gmi", NULL),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+       REGULATOR_SUPPLY("vddio_audio", NULL),
+       REGULATOR_SUPPLY("pwrdet_audio", NULL),
+       REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
+       REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
+       REGULATOR_SUPPLY("vddio_uart", NULL),
+       REGULATOR_SUPPLY("pwrdet_uart", NULL),
+       REGULATOR_SUPPLY("dbvdd", NULL),
+};
+
+static struct regulator_consumer_supply palmas_smps45_supply[] = {
+       REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct regulator_consumer_supply palmas_smps8_supply[] = {
+       REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
+       REGULATOR_SUPPLY("avdd_pllx", NULL),
+       REGULATOR_SUPPLY("avdd_pllm", NULL),
+       REGULATOR_SUPPLY("avdd_pllu", NULL),
+       REGULATOR_SUPPLY("avdd_plle", NULL),
+       REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
+       REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
+};
+
+static struct regulator_consumer_supply palmas_smps9_supply[] = {
+       REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
+};
+
+static struct regulator_consumer_supply palmas_smps10_supply[] = {
+       REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
+       REGULATOR_SUPPLY("vdd_vbrtr", NULL),
+       REGULATOR_SUPPLY("vdd_lcd", NULL),
+       REGULATOR_SUPPLY("vdd_5v0", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo2_supply[] = {
+       REGULATOR_SUPPLY("vdd_2v8_display", NULL),
+       REGULATOR_SUPPLY("vci_2v8", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo3_supply[] = {
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
+       REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
+       REGULATOR_SUPPLY("pwrdet_mipi", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo6_supply[] = {
+       REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo8_supply[] = {
+       REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldo9_supply[] = {
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
+};
+
+static struct regulator_consumer_supply palmas_ldousb_supply[] = {
+       REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
+       REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
+       REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
+};
+
+static struct regulator_consumer_supply palmas_regen1_supply[] = {
+       REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
+       REGULATOR_SUPPLY("vdd", "4-004c"),
+       REGULATOR_SUPPLY("vdd", "0-004c"),
+       REGULATOR_SUPPLY("vdd", "0-004d"),
+};
+
+static struct regulator_consumer_supply palmas_regen2_supply[] = {
+       REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
+};
+
+#define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
+       _boot_on, _apply_uv)                                            \
+       static struct regulator_init_data reg_idata_##_name = {         \
+               .constraints = {                                        \
+                       .name = palmas_rails(_name),                    \
+                       .min_uV = (_minmv)*1000,                        \
+                       .max_uV = (_maxmv)*1000,                        \
+                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
+                                       REGULATOR_MODE_STANDBY),        \
+                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
+                                       REGULATOR_CHANGE_STATUS |       \
+                                       REGULATOR_CHANGE_VOLTAGE),      \
+                       .always_on = _always_on,                        \
+                       .boot_on = _boot_on,                            \
+                       .apply_uV = _apply_uv,                          \
+               },                                                      \
+               .num_consumer_supplies =                                \
+                       ARRAY_SIZE(palmas_##_name##_supply),            \
+               .consumer_supplies = palmas_##_name##_supply,           \
+               .supply_regulator = _supply_reg,                        \
+       }
+
+PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
+PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
+PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
+PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 0, 1, 1);
+PALMAS_PDATA_INIT(smps9, 2850,  2850, NULL, 0, 0, 0);
+PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
+PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
+PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 0, 0, 1);
+PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
+PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
+PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
+PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
+PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
+PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
+
+#define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
+static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
+       PALMAS_REG_PDATA(smps12),
+       NULL,
+       PALMAS_REG_PDATA(smps3),
+       PALMAS_REG_PDATA(smps45),
+       NULL,
+       NULL,
+       NULL,
+       PALMAS_REG_PDATA(smps8),
+       PALMAS_REG_PDATA(smps9),
+       PALMAS_REG_PDATA(smps10),
+       NULL,   /* LDO1 */
+       PALMAS_REG_PDATA(ldo2),
+       PALMAS_REG_PDATA(ldo3),
+       NULL,
+       NULL,
+       PALMAS_REG_PDATA(ldo6),
+       NULL,
+       PALMAS_REG_PDATA(ldo8),
+       PALMAS_REG_PDATA(ldo9),
+       NULL,
+       PALMAS_REG_PDATA(ldousb),
+       PALMAS_REG_PDATA(regen1),
+       PALMAS_REG_PDATA(regen2),
+       NULL,
+       NULL,
+       NULL,
+};
+
+#define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,  \
+               _tstep, _vsel)                                          \
+       static struct palmas_reg_init reg_init_data_##_name = {         \
+               .warm_reset = _warm_reset,                              \
+               .roof_floor =   _roof_floor,                            \
+               .mode_sleep = _mode_sleep,                              \
+               .tstep = _tstep,                                        \
+               .vsel = _vsel,                                          \
+       }
+
+PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
+PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
+
+#define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
+static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
+       PALMAS_REG_INIT_DATA(smps12),
+       PALMAS_REG_INIT_DATA(smps123),
+       PALMAS_REG_INIT_DATA(smps3),
+       PALMAS_REG_INIT_DATA(smps45),
+       PALMAS_REG_INIT_DATA(smps457),
+       PALMAS_REG_INIT_DATA(smps6),
+       PALMAS_REG_INIT_DATA(smps7),
+       PALMAS_REG_INIT_DATA(smps8),
+       PALMAS_REG_INIT_DATA(smps9),
+       PALMAS_REG_INIT_DATA(smps10),
+       PALMAS_REG_INIT_DATA(ldo1),
+       PALMAS_REG_INIT_DATA(ldo2),
+       PALMAS_REG_INIT_DATA(ldo3),
+       PALMAS_REG_INIT_DATA(ldo4),
+       PALMAS_REG_INIT_DATA(ldo5),
+       PALMAS_REG_INIT_DATA(ldo6),
+       PALMAS_REG_INIT_DATA(ldo7),
+       PALMAS_REG_INIT_DATA(ldo8),
+       PALMAS_REG_INIT_DATA(ldo9),
+       PALMAS_REG_INIT_DATA(ldoln),
+       PALMAS_REG_INIT_DATA(ldousb),
+       PALMAS_REG_INIT_DATA(regen1),
+       PALMAS_REG_INIT_DATA(regen2),
+       PALMAS_REG_INIT_DATA(regen3),
+       PALMAS_REG_INIT_DATA(sysen1),
+       PALMAS_REG_INIT_DATA(sysen2),
+};
+
+static struct palmas_pmic_platform_data pmic_platform = {
+       .enable_ldo8_tracking = true,
+       .disabe_ldo8_tracking_suspend = true,
+};
+
+static struct palmas_platform_data palmas_pdata = {
+       .gpio_base = PALMAS_TEGRA_GPIO_BASE,
+       .irq_base = PALMAS_TEGRA_IRQ_BASE,
+       .pmic_pdata = &pmic_platform,
+       .mux_from_pdata = true,
+       .pad1 = 0,
+       .pad2 = 0,
+       .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
+       .use_power_off = true,
+};
+
+static struct i2c_board_info palma_device[] = {
+       {
+               I2C_BOARD_INFO("tps65913", 0x58),
+               .irq            = INT_EXTERNAL_PMU,
+               .platform_data  = &palmas_pdata,
+       },
+};
+
+static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
+       REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
+};
+
+static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
+       REGULATOR_SUPPLY("fan_5v0", NULL),
+};
+
+/* LCD_BL_EN GMI_AD10 */
+static struct regulator_consumer_supply fixed_reg_lcd_bl_supply[] = {
+       REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
+};
+
+/* Touch 3v3 GMI_AD13 */
+static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
+       REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
+       REGULATOR_SUPPLY("vdd_display", NULL),
+};
+
+/* VDD_3V3_COM controled by Wifi */
+static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
+       REGULATOR_SUPPLY("vdd_3v3_com", NULL),
+};
+
+/* VDD_1v8_COM controled by Wifi */
+static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
+       REGULATOR_SUPPLY("vdd_1v8_com", NULL),
+};
+
+/* vdd_3v3_sd PH0 */
+static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
+       REGULATOR_SUPPLY("vdd_3v3_sd", NULL),
+};
+
+/* Macro for defining fixed regulator sub device data */
+#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
+#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,  \
+       _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
+       static struct regulator_init_data ri_data_##_var =              \
+       {                                                               \
+               .supply_regulator = _in_supply,                         \
+               .num_consumer_supplies =                                \
+                       ARRAY_SIZE(fixed_reg_##_name##_supply),         \
+               .consumer_supplies = fixed_reg_##_name##_supply,        \
+               .constraints = {                                        \
+                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
+                                       REGULATOR_MODE_STANDBY),        \
+                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
+                                       REGULATOR_CHANGE_STATUS |       \
+                                       REGULATOR_CHANGE_VOLTAGE),      \
+                       .always_on = _always_on,                        \
+                       .boot_on = _boot_on,                            \
+               },                                                      \
+       };                                                              \
+       static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
+       {                                                               \
+               .supply_name = FIXED_SUPPLY(_name),                     \
+               .microvolts = _millivolts * 1000,                       \
+               .gpio = _gpio_nr,                                       \
+               .gpio_is_open_drain = _open_drain,                      \
+               .enable_high = _active_high,                            \
+               .enabled_at_boot = _boot_state,                         \
+               .init_data = &ri_data_##_var,                           \
+       };                                                              \
+       static struct platform_device fixed_reg_##_var##_dev = {        \
+               .name = "reg-fixed-voltage",                            \
+               .id = _id,                                              \
+               .dev = {                                                \
+                       .platform_data = &fixed_reg_##_var##_pdata,     \
+               },                                                      \
+       }
+
+FIXED_REG(3,   fan_5v0,        fan_5v0,
+       palmas_rails(smps10),   0,      0,
+       PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
+
+FIXED_REG(3,   vdd_hdmi_5v0,   vdd_hdmi_5v0,
+       palmas_rails(smps10),   0,      0,
+       TEGRA_GPIO_PK1, false,  true,   0,      5000);
+
+FIXED_REG(3,   lcd_bl, lcd_bl,
+       NULL,   0,      0,
+       TEGRA_GPIO_PH2, false,  true,   0,      5000);
+
+FIXED_REG(3,   ts_3v3, ts_3v3,
+       palmas_rails(regen1),   0,      0,
+       TEGRA_GPIO_PH5, false,  true,   0,      3300);
+
+FIXED_REG(3,   com_3v3,        com_3v3,
+       palmas_rails(regen1),   0,      0,
+       -1,     false,  true,   0,      3300);
+
+FIXED_REG(3,   sd_3v3, sd_3v3,
+       palmas_rails(regen1),   0,      0,
+       TEGRA_GPIO_PH0, false,  true,   0,      3300);
+
+FIXED_REG(3,   com_1v8,        com_1v8,
+       palmas_rails(smps3),    0,      0,
+       -1,     false,  true,   0,      1800);
+
+/*
+ * Creating the fixed regulator device tables
+ */
+
+#define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
+
+#define ROTH_COMMON_FIXED_REG          \
+       ADD_FIXED_REG(usb1_vbus),               \
+       ADD_FIXED_REG(usb3_vbus),               \
+       ADD_FIXED_REG(vdd_hdmi_5v0),
+
+#define E1612_FIXED_REG                                \
+       ADD_FIXED_REG(avdd_usb_hdmi),           \
+       ADD_FIXED_REG(en_1v8_cam),              \
+       ADD_FIXED_REG(vpp_fuse),                \
+
+#define ROTH_FIXED_REG                         \
+       ADD_FIXED_REG(en_1v8_cam_roth),
+
+/* Gpio switch regulator platform data for Roth */
+static struct platform_device *fixed_reg_devs_roth[] = {
+       ADD_FIXED_REG(fan_5v0),
+       ADD_FIXED_REG(vdd_hdmi_5v0),
+       ADD_FIXED_REG(lcd_bl),
+       ADD_FIXED_REG(ts_3v3),
+       ADD_FIXED_REG(com_3v3),
+       ADD_FIXED_REG(sd_3v3),
+       ADD_FIXED_REG(com_1v8),
+};
+
+int __init roth_palmas_regulator_init(void)
+{
+       void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+       u32 pmc_ctrl;
+       int i;
+
+       /* TPS65913: Normal state of INT request line is LOW.
+        * configure the power management controller to trigger PMU
+        * interrupts when HIGH.
+        */
+       pmc_ctrl = readl(pmc + PMC_CTRL);
+       writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+       for (i = 0; i < PALMAS_NUM_REGS ; i++) {
+               pmic_platform.reg_data[i] = roth_reg_data[i];
+               pmic_platform.reg_init[i] = roth_reg_init[i];
+       }
+
+       i2c_register_board_info(4, palma_device,
+                       ARRAY_SIZE(palma_device));
+       return 0;
+}
+
+static int ac_online(void)
+{
+       return 1;
+}
+
+static struct resource roth_pda_resources[] = {
+       [0] = {
+               .name   = "ac",
+       },
+};
+
+static struct pda_power_pdata roth_pda_data = {
+       .is_ac_online   = ac_online,
+};
+
+static struct platform_device roth_pda_power_device = {
+       .name           = "pda-power",
+       .id             = -1,
+       .resource       = roth_pda_resources,
+       .num_resources  = ARRAY_SIZE(roth_pda_resources),
+       .dev    = {
+               .platform_data  = &roth_pda_data,
+       },
+};
+
+static struct tegra_suspend_platform_data roth_suspend_data = {
+       .cpu_timer      = 300,
+       .cpu_off_timer  = 300,
+       .suspend_mode   = TEGRA_SUSPEND_LP0,
+       .core_timer     = 0x157e,
+       .core_off_timer = 2000,
+       .corereq_high   = true,
+       .sysclkreq_high = true,
+       .min_residency_noncpu = 600,
+       .min_residency_crail = 1000,
+};
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+/* board parameters for cpu dfll */
+static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
+       .sample_rate = 12500,
+
+       .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+       .cf = 10,
+       .ci = 0,
+       .cg = 2,
+
+       .droop_cut_value = 0xF,
+       .droop_restore_ramp = 0x0,
+       .scale_out_ramp = 0x0,
+};
+#endif
+
+/* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
+#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
+static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
+static inline void fill_reg_map(void)
+{
+       int i;
+       for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
+               pmu_cpu_vdd_map[i].reg_value = i + 0x23;
+               pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
+       }
+}
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
+       .dfll_clk_name = "dfll_cpu",
+       .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+       .u.pmu_i2c = {
+               .fs_rate = 400000,
+               .slave_addr = 0x86,
+               .reg = 0x00,
+       },
+       .vdd_map = pmu_cpu_vdd_map,
+       .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
+
+       .cfg_param = &roth_cl_dvfs_param,
+};
+
+static int __init roth_cl_dvfs_init(void)
+{
+       fill_reg_map();
+       tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
+       platform_device_register(&tegra_cl_dvfs_device);
+
+       return 0;
+}
+#endif
+
+static struct regulator_bulk_data roth_gps_regulator_supply[] = {
+       [0] = {
+               .supply = "vdd_gps_3v3",
+       },
+       [1] = {
+               .supply = "vdd_gps_1v8",
+       },
+};
+
+static struct regulator_userspace_consumer_data roth_gps_regulator_pdata = {
+       .num_supplies   = ARRAY_SIZE(roth_gps_regulator_supply),
+       .supplies       = roth_gps_regulator_supply,
+};
+
+static struct platform_device roth_gps_regulator_device = {
+       .name   = "reg-userspace-consumer",
+       .id     = 2,
+       .dev    = {
+                       .platform_data = &roth_gps_regulator_pdata,
+       },
+};
+
+static struct regulator_bulk_data roth_bt_regulator_supply[] = {
+       [0] = {
+               .supply = "vdd_bt_3v3",
+       },
+       [1] = {
+               .supply = "vddio_bt_1v8",
+       },
+};
+
+static struct regulator_userspace_consumer_data roth_bt_regulator_pdata = {
+       .num_supplies   = ARRAY_SIZE(roth_bt_regulator_supply),
+       .supplies       = roth_bt_regulator_supply,
+};
+
+static struct platform_device roth_bt_regulator_device = {
+       .name   = "reg-userspace-consumer",
+       .id     = 1,
+       .dev    = {
+                       .platform_data = &roth_bt_regulator_pdata,
+       },
+};
+
+static int __init roth_fixed_regulator_init(void)
+{
+       if (!machine_is_roth())
+               return 0;
+
+       return platform_add_devices(fixed_reg_devs_roth,
+                               ARRAY_SIZE(fixed_reg_devs_roth));
+}
+subsys_initcall_sync(roth_fixed_regulator_init);
+
+int __init roth_regulator_init(void)
+{
+       struct board_info board_info;
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+       roth_cl_dvfs_init();
+#endif
+       tegra_get_board_info(&board_info);
+       roth_palmas_regulator_init();
+
+       i2c_register_board_info(4, tps51632_boardinfo, 1);
+       platform_device_register(&roth_pda_power_device);
+       platform_device_register(&roth_bt_regulator_device);
+       platform_device_register(&roth_gps_regulator_device);
+       return 0;
+}
+
+int __init roth_suspend_init(void)
+{
+       tegra_init_suspend(&roth_suspend_data);
+       return 0;
+}
+
+int __init roth_edp_init(void)
+{
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+       unsigned int regulator_mA;
+
+       regulator_mA = get_maximum_cpu_current_supported();
+       if (!regulator_mA)
+               regulator_mA = 15000;
+
+       pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+
+       tegra_init_cpu_edp_limits(regulator_mA);
+#endif
+       return 0;
+}
+
+static struct soctherm_platform_data roth_soctherm_data = {
+       .soctherm_clk_rate = 136000000,
+       .tsensor_clk_rate = 500000,
+       .sensor_data = {
+               [TSENSE_CPU0] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU1] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU2] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_CPU3] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_MEM0] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_MEM1] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_GPU] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+               [TSENSE_PLLX] = {
+                       .enable = true,
+                       .therm_a = 570,
+                       .therm_b = -744,
+                       .tall = 16300,
+                       .tiddq = 1,
+                       .ten_count = 1,
+                       .tsample = 163,
+                       .pdiv = 10,
+               },
+       },
+};
+
+static struct balanced_throttle tj_throttle = {
+       .throt_tab_size = 10,
+       .throt_tab = {
+               {      0, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 760000, 1000 },
+               { 760000, 1050 },
+               {1000000, 1050 },
+               {1000000, 1100 },
+       },
+};
+
+static int __init roth_soctherm_init(void)
+{
+       roth_soctherm_data.therm[THERM_CPU].cdev =
+                       balanced_throttle_register(&tj_throttle);
+
+       return tegra11_soctherm_init(&roth_soctherm_data);
+}
+module_init(roth_soctherm_init);
diff --git a/arch/arm/mach-tegra/board-roth-powermon.c b/arch/arm/mach-tegra/board-roth-powermon.c
new file mode 100644 (file)
index 0000000..45eddf5
--- /dev/null
@@ -0,0 +1,302 @@
+/*
+ * arch/arm/mach-tegra/board-roth-powermon.c
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation. All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/ina219.h>
+
+#include "board.h"
+#include "board-roth.h"
+
+#define PRECISION_MULTIPLIER_ROTH 1000
+
+enum {
+       VDD_12V_DCIN_RS,
+       VDD_AC_BAT_VIN1,
+       VDD_5V0_SYS,
+       VDD_3V3_SYS,
+       VDD_3V3_SYS_VIN4_5_7,
+       AVDD_USB_HDMI,
+       VDD_AC_BAT_D1,
+       VDD_AO_SMPS12_IN,
+       VDD_3V3_SYS_SMPS45_IN,
+       VDD_AO_SMPS2_IN,
+       VDDIO_HV_AP,
+       VDD_1V8_LDO3_IN,
+       VDD_3V3_SYS_LDO4_IN,
+       VDD_AO_LDO8_IN,
+       VDD_1V8_AP,
+       VDD_1V8_DSM,
+};
+
+static struct ina219_platform_data power_mon_info[] = {
+       [VDD_12V_DCIN_RS] = {
+               .calibration_data  = 0xaec0,
+               .power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_12V_DCIN_RS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_AC_BAT_VIN1] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_AC_BAT_VIN1",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_5V0_SYS] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 2.5000762963 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_5V0_SYS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_3V3_SYS] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 2.5000762963 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_3V3_SYS",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_3V3_SYS_VIN4_5_7] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_3V3_SYS_VIN4_5_7",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [AVDD_USB_HDMI] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "AVDD_USB_HDMI",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_AC_BAT_D1] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 12.50038148 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_AC_BAT_D1",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_AO_SMPS12_IN] = {
+               .calibration_data  = 0xaec0,
+               .power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_AO_SMPS12_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_3V3_SYS_SMPS45_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_3V3_SYS_SMPS45_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_AO_SMPS2_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_AO_SMPS2_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDDIO_HV_AP] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDDIO_HV_AP",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_1V8_LDO3_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_1V8_LDO3_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_3V3_SYS_LDO4_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_3V3_SYS_LDO4_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_AO_LDO8_IN] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_AO_LDO8_IN",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_1V8_AP] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_1V8_AP",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+
+       [VDD_1V8_DSM] = {
+               .calibration_data  = 0xfffe,
+               .power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_ROTH,
+               .rail_name = "VDD_1V8_DSM",
+               .divisor = 20,
+               .precision_multiplier = PRECISION_MULTIPLIER_ROTH,
+       },
+};
+
+enum {
+       INA_I2C_ADDR_40,
+       INA_I2C_ADDR_41,
+       INA_I2C_ADDR_42,
+       INA_I2C_ADDR_43,
+       INA_I2C_ADDR_44,
+       INA_I2C_ADDR_45,
+       INA_I2C_ADDR_46,
+       INA_I2C_ADDR_47,
+       INA_I2C_ADDR_48,
+       INA_I2C_ADDR_49,
+       INA_I2C_ADDR_4A,
+       INA_I2C_ADDR_4B,
+       INA_I2C_ADDR_4C,
+       INA_I2C_ADDR_4D,
+       INA_I2C_ADDR_4E,
+       INA_I2C_ADDR_4F,
+};
+
+static struct i2c_board_info roth_i2c0_ina219_board_info[] = {
+       [INA_I2C_ADDR_40] = {
+               I2C_BOARD_INFO("ina219", 0x40),
+               .platform_data = &power_mon_info[VDD_12V_DCIN_RS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_41] = {
+               I2C_BOARD_INFO("ina219", 0x41),
+               .platform_data = &power_mon_info[VDD_AC_BAT_VIN1],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_42] = {
+               I2C_BOARD_INFO("ina219", 0x42),
+               .platform_data = &power_mon_info[VDD_5V0_SYS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_43] = {
+               I2C_BOARD_INFO("ina219", 0x43),
+               .platform_data = &power_mon_info[VDD_3V3_SYS],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_44] = {
+               I2C_BOARD_INFO("ina219", 0x44),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_VIN4_5_7],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_45] = {
+               I2C_BOARD_INFO("ina219", 0x45),
+               .platform_data = &power_mon_info[AVDD_USB_HDMI],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_46] = {
+               I2C_BOARD_INFO("ina219", 0x46),
+               .platform_data = &power_mon_info[VDD_AC_BAT_D1],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_47] = {
+               I2C_BOARD_INFO("ina219", 0x47),
+               .platform_data = &power_mon_info[VDD_AO_SMPS12_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_48] = {
+               I2C_BOARD_INFO("ina219", 0x48),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_SMPS45_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_49] = {
+               I2C_BOARD_INFO("ina219", 0x49),
+               .platform_data = &power_mon_info[VDD_AO_SMPS2_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4A] = {
+               I2C_BOARD_INFO("ina219", 0x4A),
+               .platform_data = &power_mon_info[VDDIO_HV_AP],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4B] = {
+               I2C_BOARD_INFO("ina219", 0x4B),
+               .platform_data = &power_mon_info[VDD_1V8_LDO3_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4C] = {
+               I2C_BOARD_INFO("ina219", 0x4C),
+               .platform_data = &power_mon_info[VDD_3V3_SYS_LDO4_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4D] = {
+               I2C_BOARD_INFO("ina219", 0x4D),
+               .platform_data = &power_mon_info[VDD_AO_LDO8_IN],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4E] = {
+               I2C_BOARD_INFO("ina219", 0x4E),
+               .platform_data = &power_mon_info[VDD_1V8_AP],
+               .irq = -1,
+       },
+
+       [INA_I2C_ADDR_4F] = {
+               I2C_BOARD_INFO("ina219", 0x4F),
+               .platform_data = &power_mon_info[VDD_1V8_DSM],
+               .irq = -1,
+       },
+};
+
+int __init roth_pmon_init(void)
+{
+       i2c_register_board_info(1, roth_i2c0_ina219_board_info,
+               ARRAY_SIZE(roth_i2c0_ina219_board_info));
+
+       return 0;
+}
+
diff --git a/arch/arm/mach-tegra/board-roth-sdhci.c b/arch/arm/mach-tegra/board-roth-sdhci.c
new file mode 100644 (file)
index 0000000..f5bb54b
--- /dev/null
@@ -0,0 +1,406 @@
+/*
+ * arch/arm/mach-tegra/board-roth-sdhci.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mmc/host.h>
+#include <linux/wl12xx.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+#include<mach/gpio-tegra.h>
+#include <mach/io_dpd.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-roth.h"
+
+
+#define ROTH_WLAN_PWR  TEGRA_GPIO_PCC5
+#define ROTH_WLAN_RST  TEGRA_GPIO_PX7
+#define ROTH_WLAN_WOW  TEGRA_GPIO_PU5
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+static int roth_wifi_status_register(void (*callback)(int , void *), void *);
+
+static int roth_wifi_reset(int on);
+static int roth_wifi_power(int on);
+static int roth_wifi_set_carddetect(int val);
+
+static struct wifi_platform_data roth_wifi_control = {
+       .set_power      = roth_wifi_power,
+       .set_reset      = roth_wifi_reset,
+       .set_carddetect = roth_wifi_set_carddetect,
+};
+
+static struct resource wifi_resource[] = {
+       [0] = {
+               .name   = "bcm4329_wlan_irq",
+               .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
+                               | IORESOURCE_IRQ_SHAREABLE,
+       },
+};
+
+static struct platform_device roth_wifi_device = {
+       .name           = "bcm4329_wlan",
+       .id             = 1,
+       .num_resources  = 1,
+       .resource       = wifi_resource,
+       .dev            = {
+               .platform_data = &roth_wifi_control,
+       },
+};
+
+static struct resource sdhci_resource0[] = {
+       [0] = {
+               .start  = INT_SDMMC1,
+               .end    = INT_SDMMC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC1_BASE,
+               .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource2[] = {
+       [0] = {
+               .start  = INT_SDMMC3,
+               .end    = INT_SDMMC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC3_BASE,
+               .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource3[] = {
+       [0] = {
+               .start  = INT_SDMMC4,
+               .end    = INT_SDMMC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC4_BASE,
+               .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+static struct embedded_sdio_data embedded_sdio_data0 = {
+       .cccr   = {
+               .sdio_vsn       = 2,
+               .multi_block    = 1,
+               .low_speed      = 0,
+               .wide_bus       = 0,
+               .high_power     = 1,
+               .high_speed     = 1,
+       },
+       .cis  = {
+               .vendor  = 0x02d0,
+               .device  = 0x4329,
+       },
+};
+#endif
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+       .mmc_data = {
+               .register_status_notify = roth_wifi_status_register,
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+               .embedded_sdio = &embedded_sdio_data0,
+#endif
+               .built_in = 0,
+               .ocr_mask = MMC_OCR_1V8_MASK,
+       },
+#ifndef CONFIG_MMC_EMBEDDED_SDIO
+       .pm_flags = MMC_PM_KEEP_POWER,
+#endif
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .tap_delay = 0x2,
+       .trim_delay = 0x2,
+       .ddr_clk_limit = 41000000,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .tap_delay = 0x3,
+       .trim_delay = 0x3,
+       .ddr_clk_limit = 41000000,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .is_8bit = 1,
+       .tap_delay = 0x5,
+       .trim_delay = 0x3,
+       .ddr_clk_limit = 41000000,
+       .mmc_data = {
+               .built_in = 1,
+       }
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+       .name           = "sdhci-tegra",
+       .id             = 0,
+       .resource       = sdhci_resource0,
+       .num_resources  = ARRAY_SIZE(sdhci_resource0),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data0,
+       },
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+       .name           = "sdhci-tegra",
+       .id             = 2,
+       .resource       = sdhci_resource2,
+       .num_resources  = ARRAY_SIZE(sdhci_resource2),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data2,
+       },
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+       .name           = "sdhci-tegra",
+       .id             = 3,
+       .resource       = sdhci_resource3,
+       .num_resources  = ARRAY_SIZE(sdhci_resource3),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data3,
+       },
+};
+
+static int roth_wifi_status_register(
+               void (*callback)(int card_present, void *dev_id),
+               void *dev_id)
+{
+       if (wifi_status_cb)
+               return -EAGAIN;
+       wifi_status_cb = callback;
+       wifi_status_cb_devid = dev_id;
+       return 0;
+}
+
+static int roth_wifi_set_carddetect(int val)
+{
+       pr_debug("%s: %d\n", __func__, val);
+       if (wifi_status_cb)
+               wifi_status_cb(val, wifi_status_cb_devid);
+       else
+               pr_warning("%s: Nobody to notify\n", __func__);
+       return 0;
+}
+
+static struct regulator *roth_vdd_com_3v3;
+static struct regulator *roth_vddio_com_1v8;
+#define ROTH_VDD_WIFI_3V3 "vdd_wifi_3v3"
+#define ROTH_VDD_WIFI_1V8 "vddio_wifi_1v8"
+
+
+static int roth_wifi_regulator_enable(void)
+{
+       int ret = 0;
+
+       /* Enable COM's vdd_com_3v3 regulator*/
+       if (IS_ERR_OR_NULL(roth_vdd_com_3v3)) {
+               roth_vdd_com_3v3 = regulator_get(NULL, ROTH_VDD_WIFI_3V3);
+               if (IS_ERR_OR_NULL(roth_vdd_com_3v3)) {
+                       pr_err("Couldn't get regulator "
+                               ROTH_VDD_WIFI_3V3 "\n");
+                       return PTR_ERR(roth_vdd_com_3v3);
+               }
+
+               ret = regulator_enable(roth_vdd_com_3v3);
+               if (ret < 0) {
+                       pr_err("Couldn't enable regulator "
+                               ROTH_VDD_WIFI_3V3 "\n");
+                       regulator_put(roth_vdd_com_3v3);
+                       roth_vdd_com_3v3 = NULL;
+                       return ret;
+               }
+       }
+
+       /* Enable COM's vddio_com_1v8 regulator*/
+       if (IS_ERR_OR_NULL(roth_vddio_com_1v8)) {
+               roth_vddio_com_1v8 = regulator_get(NULL,
+                       ROTH_VDD_WIFI_1V8);
+               if (IS_ERR_OR_NULL(roth_vddio_com_1v8)) {
+                       pr_err("Couldn't get regulator "
+                               ROTH_VDD_WIFI_1V8 "\n");
+                       regulator_disable(roth_vdd_com_3v3);
+
+                       regulator_put(roth_vdd_com_3v3);
+                       roth_vdd_com_3v3 = NULL;
+                       return PTR_ERR(roth_vddio_com_1v8);
+               }
+
+               ret = regulator_enable(roth_vddio_com_1v8);
+               if (ret < 0) {
+                       pr_err("Couldn't enable regulator "
+                               ROTH_VDD_WIFI_1V8 "\n");
+                       regulator_put(roth_vddio_com_1v8);
+                       roth_vddio_com_1v8 = NULL;
+
+                       regulator_disable(roth_vdd_com_3v3);
+                       regulator_put(roth_vdd_com_3v3);
+                       roth_vdd_com_3v3 = NULL;
+                       return ret;
+               }
+       }
+
+       return ret;
+}
+
+static void roth_wifi_regulator_disable(void)
+{
+       /* Disable COM's vdd_com_3v3 regulator*/
+       if (!IS_ERR_OR_NULL(roth_vdd_com_3v3)) {
+               regulator_disable(roth_vdd_com_3v3);
+               regulator_put(roth_vdd_com_3v3);
+               roth_vdd_com_3v3 = NULL;
+       }
+
+       /* Disable COM's vddio_com_1v8 regulator*/
+       if (!IS_ERR_OR_NULL(roth_vddio_com_1v8)) {
+               regulator_disable(roth_vddio_com_1v8);
+               regulator_put(roth_vddio_com_1v8);
+               roth_vddio_com_1v8 = NULL;
+       }
+}
+
+static int roth_wifi_power(int on)
+{
+       struct tegra_io_dpd *sd_dpd;
+       int ret = 0;
+
+       pr_debug("%s: %d\n", __func__, on);
+       /* Enable COM's regulators on wi-fi poer on*/
+       if (on == 1) {
+               ret = roth_wifi_regulator_enable();
+               if (ret < 0) {
+                       pr_err("Failed to enable COM regulators\n");
+                       return ret;
+               }
+       }
+
+       /*
+        * FIXME : we need to revisit IO DPD code
+        * on how should multiple pins under DPD get controlled
+        *
+        * roth GPIO WLAN enable is part of SDMMC3 pin group
+        */
+       sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev);
+       if (sd_dpd) {
+               mutex_lock(&sd_dpd->delay_lock);
+               tegra_io_dpd_disable(sd_dpd);
+               mutex_unlock(&sd_dpd->delay_lock);
+       }
+       gpio_set_value(ROTH_WLAN_PWR, on);
+       mdelay(100);
+       gpio_set_value(ROTH_WLAN_RST, on);
+       mdelay(200);
+       if (sd_dpd) {
+               mutex_lock(&sd_dpd->delay_lock);
+               tegra_io_dpd_enable(sd_dpd);
+               mutex_unlock(&sd_dpd->delay_lock);
+       }
+
+       /* Disable COM's regulators on wi-fi poer off*/
+       if (on != 1) {
+               pr_debug("Disabling COM regulators\n");
+               roth_wifi_regulator_disable();
+       }
+
+       return ret;
+}
+
+static int roth_wifi_reset(int on)
+{
+       pr_debug("%s: do nothing\n", __func__);
+       return 0;
+}
+
+static int __init roth_wifi_init(void)
+{
+       int rc;
+
+       rc = gpio_request(ROTH_WLAN_PWR, "wlan_power");
+       if (rc)
+               pr_err("WLAN_PWR gpio request failed:%d\n", rc);
+       rc = gpio_request(ROTH_WLAN_RST, "wlan_rst");
+       if (rc)
+               pr_err("WLAN_RST gpio request failed:%d\n", rc);
+       rc = gpio_request(ROTH_WLAN_WOW, "bcmsdh_sdmmc");
+       if (rc)
+               pr_err("WLAN_WOW gpio request failed:%d\n", rc);
+
+       rc = gpio_direction_output(ROTH_WLAN_PWR, 0);
+       if (rc)
+               pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
+       gpio_direction_output(ROTH_WLAN_RST, 0);
+       if (rc)
+               pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc);
+       rc = gpio_direction_input(ROTH_WLAN_WOW);
+       if (rc)
+               pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc);
+
+       wifi_resource[0].start = wifi_resource[0].end =
+               gpio_to_irq(ROTH_WLAN_WOW);
+
+       platform_device_register(&roth_wifi_device);
+       return 0;
+}
+
+#ifdef CONFIG_TEGRA_PREPOWER_WIFI
+static int __init roth_wifi_prepower(void)
+{
+       if (!machine_is_roth())
+               return 0;
+
+       roth_wifi_power(1);
+
+       return 0;
+}
+
+subsys_initcall_sync(roth_wifi_prepower);
+#endif
+
+int __init roth_sdhci_init(void)
+{
+       platform_device_register(&tegra_sdhci_device3);
+       platform_device_register(&tegra_sdhci_device2);
+       platform_device_register(&tegra_sdhci_device0);
+       roth_wifi_init();
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-roth-sensors.c b/arch/arm/mach-tegra/board-roth-sensors.c
new file mode 100644 (file)
index 0000000..47efee7
--- /dev/null
@@ -0,0 +1,609 @@
+/*
+ * arch/arm/mach-tegra/board-roth-sensors.c
+ *
+ * Copyright (c) 2012 NVIDIA CORPORATION, All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * Neither the name of NVIDIA CORPORATION nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/mpu.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio.h>
+#include <linux/therm_est.h>
+#include <linux/nct1008.h>
+#include <mach/edp.h>
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux-t11.h>
+#include <mach/pinmux.h>
+#include <media/imx091.h>
+#include <media/ov9772.h>
+#include <media/as364x.h>
+#include <media/ad5816.h>
+#include <generated/mach-types.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-roth.h"
+#include "cpu-tegra.h"
+#include "devices.h"
+#include "tegra-board-id.h"
+
+static struct board_info board_info;
+
+static struct balanced_throttle tj_throttle = {
+       .throt_tab_size = 10,
+       .throt_tab = {
+               {      0, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 640000, 1000 },
+               { 760000, 1000 },
+               { 760000, 1050 },
+               {1000000, 1050 },
+               {1000000, 1100 },
+       },
+};
+
+static struct nct1008_platform_data roth_nct1008_pdata = {
+       .supported_hwrev = true,
+       .ext_range = true,
+       .conv_rate = 0x08,
+       .offset = 80, /* 4 * 20C. Bug 844025 - 1C for device accuracies */
+       .shutdown_ext_limit = 90, /* C */
+       .shutdown_local_limit = 120, /* C */
+
+       /* Thermal Throttling */
+       .passive = {
+               .create_cdev = (struct thermal_cooling_device *(*)(void *))
+                               balanced_throttle_register,
+               .cdev_data = &tj_throttle,
+               .trip_temp = 80000,
+               .tc1 = 0,
+               .tc2 = 1,
+               .passive_delay = 2000,
+       }
+};
+
+static struct i2c_board_info roth_i2c4_nct1008_board_info[] = {
+       {
+               I2C_BOARD_INFO("nct1008", 0x4C),
+               .platform_data = &roth_nct1008_pdata,
+               .irq = -1,
+       }
+};
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
+       }
+
+static struct tegra_pingroup_config mclk_disable =
+       VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config mclk_enable =
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config pbb0_disable =
+       VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+static struct tegra_pingroup_config pbb0_enable =
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
+
+/*
+ * As a workaround, roth_vcmvdd need to be allocated to activate the
+ * sensor devices. This is due to the focuser device(AD5816) will hook up
+ * the i2c bus if it is not powered up.
+*/
+static struct regulator *roth_vcmvdd;
+
+static int roth_get_vcmvdd(void)
+{
+       if (!roth_vcmvdd) {
+               roth_vcmvdd = regulator_get(NULL, "vdd_af_cam1");
+               if (unlikely(WARN_ON(IS_ERR(roth_vcmvdd)))) {
+                       pr_err("%s: can't get regulator vcmvdd: %ld\n",
+                               __func__, PTR_ERR(roth_vcmvdd));
+                       roth_vcmvdd = NULL;
+                       return -ENODEV;
+               }
+       }
+       return 0;
+}
+
+static int roth_imx091_power_on(struct imx091_power_rail *pw)
+{
+       int err;
+
+       if (unlikely(!pw || !pw->avdd || !pw->iovdd))
+               return -EFAULT;
+
+       if (roth_get_vcmvdd())
+               goto imx091_poweron_fail;
+
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+       usleep_range(10, 20);
+
+       err = regulator_enable(pw->avdd);
+       if (err)
+               goto imx091_avdd_fail;
+
+       err = regulator_enable(pw->iovdd);
+       if (err)
+               goto imx091_iovdd_fail;
+
+       usleep_range(1, 2);
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 1);
+
+       err = regulator_enable(roth_vcmvdd);
+       if (unlikely(err))
+               goto imx091_vcmvdd_fail;
+
+       tegra_pinmux_config_table(&mclk_enable, 1);
+       usleep_range(300, 310);
+
+       return 1;
+
+imx091_vcmvdd_fail:
+       regulator_disable(pw->iovdd);
+
+imx091_iovdd_fail:
+       regulator_disable(pw->avdd);
+
+imx091_avdd_fail:
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+
+imx091_poweron_fail:
+       pr_err("%s FAILED\n", __func__);
+       return -ENODEV;
+}
+
+static int roth_imx091_power_off(struct imx091_power_rail *pw)
+{
+       if (unlikely(!pw || !roth_vcmvdd || !pw->avdd || !pw->iovdd))
+               return -EFAULT;
+
+       usleep_range(1, 2);
+       tegra_pinmux_config_table(&mclk_disable, 1);
+       gpio_set_value(CAM1_POWER_DWN_GPIO, 0);
+       usleep_range(1, 2);
+
+       regulator_disable(roth_vcmvdd);
+       regulator_disable(pw->iovdd);
+       regulator_disable(pw->avdd);
+
+       return 1;
+}
+
+struct imx091_platform_data roth_imx091_data = {
+       .power_on = roth_imx091_power_on,
+       .power_off = roth_imx091_power_off,
+};
+
+static int roth_ov9772_power_on(struct ov9772_power_rail *pw)
+{
+       int err;
+
+       if (unlikely(!pw || !pw->avdd || !pw->dovdd))
+               return -EFAULT;
+
+       if (roth_get_vcmvdd())
+               goto ov9772_get_vcmvdd_fail;
+
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+       gpio_set_value(CAM_RSTN, 0);
+
+       err = regulator_enable(pw->avdd);
+       if (unlikely(err))
+               goto ov9772_avdd_fail;
+
+       err = regulator_enable(pw->dovdd);
+       if (unlikely(err))
+               goto ov9772_dovdd_fail;
+
+       gpio_set_value(CAM_RSTN, 1);
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 1);
+
+       err = regulator_enable(roth_vcmvdd);
+       if (unlikely(err))
+               goto ov9772_vcmvdd_fail;
+
+       tegra_pinmux_config_table(&pbb0_enable, 1);
+       usleep_range(340, 380);
+
+       /* return 1 to skip the in-driver power_on sequence */
+       return 1;
+
+ov9772_vcmvdd_fail:
+       regulator_disable(pw->dovdd);
+
+ov9772_dovdd_fail:
+       regulator_disable(pw->avdd);
+
+ov9772_avdd_fail:
+       gpio_set_value(CAM_RSTN, 0);
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+
+ov9772_get_vcmvdd_fail:
+       pr_err("%s FAILED\n", __func__);
+       return -ENODEV;
+}
+
+static int roth_ov9772_power_off(struct ov9772_power_rail *pw)
+{
+       if (unlikely(!pw || !roth_vcmvdd || !pw->avdd || !pw->dovdd))
+               return -EFAULT;
+
+       usleep_range(21, 25);
+       tegra_pinmux_config_table(&pbb0_disable, 1);
+
+       gpio_set_value(CAM2_POWER_DWN_GPIO, 0);
+       gpio_set_value(CAM_RSTN, 0);
+
+       regulator_disable(roth_vcmvdd);
+       regulator_disable(pw->dovdd);
+       regulator_disable(pw->avdd);
+
+       /* return 1 to skip the in-driver power_off sequence */
+       return 1;
+}
+
+static struct nvc_gpio_pdata ov9772_gpio_pdata[] = {
+       { OV9772_GPIO_TYPE_SHTDN, CAM2_POWER_DWN_GPIO, true, 0, },
+       { OV9772_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
+};
+
+static struct ov9772_platform_data roth_ov9772_pdata = {
+       .num            = 1,
+       .dev_name       = "camera",
+       .gpio_count     = ARRAY_SIZE(ov9772_gpio_pdata),
+       .gpio           = ov9772_gpio_pdata,
+       .power_on       = roth_ov9772_power_on,
+       .power_off      = roth_ov9772_power_off,
+};
+
+static int roth_as3648_power_on(struct as364x_power_rail *pw)
+{
+       int err = roth_get_vcmvdd();
+
+       if (err)
+               return err;
+
+       return regulator_enable(roth_vcmvdd);
+}
+
+static int roth_as3648_power_off(struct as364x_power_rail *pw)
+{
+       if (!roth_vcmvdd)
+               return -ENODEV;
+
+       return regulator_disable(roth_vcmvdd);
+}
+
+static struct as364x_platform_data roth_as3648_pdata = {
+       .config         = {
+               .max_total_current_mA = 1000,
+               .max_peak_current_mA = 600,
+               .strobe_type = 1,
+               },
+       .pinstate       = {
+               .mask   = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
+               .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
+               },
+       .dev_name       = "torch",
+       .type           = AS3648,
+       .gpio_strobe    = CAM_FLASH_STROBE,
+       .led_mask       = 3,
+
+       .power_on_callback = roth_as3648_power_on,
+       .power_off_callback = roth_as3648_power_off,
+};
+
+static struct ad5816_platform_data pluto_ad5816_pdata = {
+       .cfg            = 0,
+       .num            = 0,
+       .sync           = 0,
+       .dev_name       = "focuser",
+};
+
+static struct i2c_board_info roth_i2c_board_info_e1625[] = {
+       {
+               I2C_BOARD_INFO("imx091", 0x36),
+               .platform_data = &roth_imx091_data,
+       },
+       {
+               I2C_BOARD_INFO("ov9772", 0x10),
+               .platform_data = &roth_ov9772_pdata,
+       },
+       {
+               I2C_BOARD_INFO("as3648", 0x30),
+               .platform_data = &roth_as3648_pdata,
+       },
+       {
+               I2C_BOARD_INFO("ad5816", 0x0E),
+               .platform_data = &pluto_ad5816_pdata,
+       },
+};
+
+static int roth_camera_init(void)
+{
+       tegra_pinmux_config_table(&mclk_disable, 1);
+       tegra_pinmux_config_table(&pbb0_disable, 1);
+
+       i2c_register_board_info(2, roth_i2c_board_info_e1625,
+               ARRAY_SIZE(roth_i2c_board_info_e1625));
+       return 0;
+}
+
+/* MPU board file definition   */
+static struct mpu_platform_data mpu9150_gyro_data = {
+       .int_config     = 0x10,
+       .level_shifter  = 0,
+       /* Located in board_[platformname].h */
+       .orientation    = MPU_GYRO_ORIENTATION,
+       .sec_slave_type = SECONDARY_SLAVE_TYPE_COMPASS,
+       .sec_slave_id   = COMPASS_ID_AK8975,
+       .secondary_i2c_addr     = MPU_COMPASS_ADDR,
+       .secondary_read_reg     = 0x06,
+       .secondary_orientation  = MPU_COMPASS_ORIENTATION,
+       .key            = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
+                          0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
+};
+
+#define TEGRA_CAMERA_GPIO(_gpio, _label, _value)               \
+       {                                                       \
+               .gpio = _gpio,                                  \
+               .label = _label,                                \
+               .value = _value,                                \
+       }
+
+static struct i2c_board_info roth_i2c_board_info_cm3218[] = {
+       {
+               I2C_BOARD_INFO("cm3218", 0x48),
+       },
+};
+
+static struct i2c_board_info __initdata inv_mpu9150_i2c2_board_info[] = {
+       {
+               I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
+               .platform_data = &mpu9150_gyro_data,
+       },
+};
+
+static void mpuirq_init(void)
+{
+       int ret = 0;
+       unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
+       unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
+       char *gyro_name = MPU_GYRO_NAME;
+
+       pr_info("*** MPU START *** mpuirq_init...\n");
+
+       ret = gpio_request(gyro_irq_gpio, gyro_name);
+
+       if (ret < 0) {
+               pr_err("%s: gpio_request failed %d\n", __func__, ret);
+               return;
+       }
+
+       ret = gpio_direction_input(gyro_irq_gpio);
+       if (ret < 0) {
+               pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
+               gpio_free(gyro_irq_gpio);
+               return;
+       }
+       pr_info("*** MPU END *** mpuirq_init...\n");
+
+       inv_mpu9150_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
+       i2c_register_board_info(gyro_bus_num, inv_mpu9150_i2c2_board_info,
+               ARRAY_SIZE(inv_mpu9150_i2c2_board_info));
+}
+
+static int roth_nct1008_init(void)
+{
+       int nct1008_port = -1;
+       int ret = 0;
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       if ((board_info.board_id == BOARD_E1611) ||
+           (board_info.board_id == BOARD_E1612) ||
+           (board_info.board_id == BOARD_E1641) ||
+           (board_info.board_id == BOARD_E1613) ||
+           (board_info.board_id == BOARD_P2454))
+       {
+               /* per email from Matt 9/10/2012 */
+               nct1008_port = TEGRA_GPIO_PX6;
+       } else {
+               nct1008_port = TEGRA_GPIO_PX6;
+               pr_err("Warning: nct alert_port assumed TEGRA_GPIO_PX6"
+                      " for unknown roth board id E%d\n",
+                      board_info.board_id);
+       }
+#else
+       /* roth + AP30 interposer has SPI2_CS0 gpio */
+       nct1008_port = TEGRA_GPIO_PX3;
+#endif
+
+       if (nct1008_port >= 0) {
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+               const struct tegra_edp_limits *cpu_edp_limits;
+               int cpu_edp_limits_size;
+               int i;
+
+               /* edp capping */
+               tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
+
+               if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
+                       BUG();
+
+               for (i = 0; i < cpu_edp_limits_size-1; i++) {
+                       roth_nct1008_pdata.active[i].create_cdev =
+                               (struct thermal_cooling_device *(*)(void *))
+                                       edp_cooling_device_create;
+                       roth_nct1008_pdata.active[i].cdev_data = (void *)i;
+                       roth_nct1008_pdata.active[i].trip_temp =
+                               cpu_edp_limits[i].temperature * 1000;
+                       roth_nct1008_pdata.active[i].hysteresis = 1000;
+               }
+               roth_nct1008_pdata.active[i].create_cdev = NULL;
+#endif
+
+               roth_i2c4_nct1008_board_info[0].irq = gpio_to_irq(nct1008_port);
+               pr_info("%s: roth nct1008 irq %d", __func__, roth_i2c4_nct1008_board_info[0].irq);
+
+               ret = gpio_request(nct1008_port, "temp_alert");
+               if (ret < 0)
+                       return ret;
+
+               ret = gpio_direction_input(nct1008_port);
+               if (ret < 0) {
+                       pr_info("%s: calling gpio_free(nct1008_port)", __func__);
+                       gpio_free(nct1008_port);
+               }
+       }
+
+       /* roth has thermal sensor on GEN1-I2C i.e. instance 0 */
+       i2c_register_board_info(0, roth_i2c4_nct1008_board_info,
+               ARRAY_SIZE(roth_i2c4_nct1008_board_info));
+
+       return ret;
+}
+
+static struct i2c_board_info __initdata bq20z45_pdata[] = {
+       {
+               I2C_BOARD_INFO("sbs-battery", 0x0B),
+       },
+};
+
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+static int tegra_skin_match(struct thermal_zone_device *thz, void *data)
+{
+       return strcmp((char *)data, thz->type) == 0;
+}
+
+static int tegra_skin_get_temp(void *data, long *temp)
+{
+       struct thermal_zone_device *thz;
+
+       thz = thermal_zone_device_find(data, tegra_skin_match);
+
+       if (!thz || thz->ops->get_temp(thz, temp))
+               *temp = 25000;
+
+       return 0;
+}
+
+static struct therm_est_data skin_data = {
+       .toffset = 9793,
+       .polling_period = 1100,
+       .ndevs = 2,
+       .devs = {
+                       {
+                               .dev_data = "nct_ext",
+                               .get_temp = tegra_skin_get_temp,
+                               .coeffs = {
+                                       2, 1, 1, 1,
+                                       1, 1, 1, 1,
+                                       1, 1, 1, 0,
+                                       1, 1, 0, 0,
+                                       0, 0, -1, -7
+                               },
+                       },
+                       {
+                               .dev_data = "nct_int",
+                               .get_temp = tegra_skin_get_temp,
+                               .coeffs = {
+                                       -11, -7, -5, -3,
+                                       -3, -2, -1, 0,
+                                       0, 0, 1, 1,
+                                       1, 2, 2, 3,
+                                       4, 6, 11, 18
+                               },
+                       },
+       },
+       .trip_temp = 43000,
+       .tc1 = 1,
+       .tc2 = 15,
+       .passive_delay = 15000,
+};
+
+static struct balanced_throttle skin_throttle = {
+       .throt_tab_size = 6,
+       .throt_tab = {
+               { 640000, 1200 },
+               { 640000, 1200 },
+               { 760000, 1200 },
+               { 760000, 1200 },
+               {1000000, 1200 },
+               {1000000, 1200 },
+       },
+};
+
+static int __init roth_skin_init(void)
+{
+       struct thermal_cooling_device *skin_cdev;
+
+       skin_cdev = balanced_throttle_register(&skin_throttle);
+
+       skin_data.cdev = skin_cdev;
+       tegra_skin_therm_est_device.dev.platform_data = &skin_data;
+       platform_device_register(&tegra_skin_therm_est_device);
+
+       return 0;
+}
+late_initcall(roth_skin_init);
+#endif
+
+int __init roth_sensors_init(void)
+{
+       int err;
+
+       tegra_get_board_info(&board_info);
+
+       err = roth_nct1008_init();
+       if (err)
+               return err;
+
+       roth_camera_init();
+       mpuirq_init();
+
+       i2c_register_board_info(0, roth_i2c_board_info_cm3218,
+               ARRAY_SIZE(roth_i2c_board_info_cm3218));
+
+       i2c_register_board_info(0, bq20z45_pdata,
+               ARRAY_SIZE(bq20z45_pdata));
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-roth.c b/arch/arm/mach-tegra/board-roth.c
new file mode 100644 (file)
index 0000000..f3932e4
--- /dev/null
@@ -0,0 +1,680 @@
+/*
+ * arch/arm/mach-tegra/board-roth.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/rm31080a_ts.h>
+#include <linux/tegra_uart.h>
+#include <linux/memblock.h>
+#include <linux/spi-tegra.h>
+#include <linux/nfc/pn544.h>
+#include <linux/rfkill-gpio.h>
+#include <linux/skbuff.h>
+#include <linux/ti_wilink_st.h>
+#include <linux/regulator/consumer.h>
+#include <linux/smb349-charger.h>
+#include <linux/max17048_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c/at24.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/io_dpd.h>
+#include <mach/i2s.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/gpio-tegra.h>
+#include <mach/tegra_fiq_debugger.h>
+#include <mach/edp.h>
+
+#include "board-touch-raydium.h"
+#include "board.h"
+#include "board-common.h"
+#include "clock.h"
+#include "board-roth.h"
+#include "board-roth.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+#include "pm.h"
+#include "common.h"
+#include "tegra-board-id.h"
+
+static struct rfkill_gpio_platform_data roth_bt_rfkill_pdata = {
+               .name           = "bt_rfkill",
+               .shutdown_gpio  = TEGRA_GPIO_PQ7,
+               .type           = RFKILL_TYPE_BLUETOOTH,
+};
+
+static struct platform_device roth_bt_rfkill_device = {
+       .name = "rfkill_gpio",
+       .id             = -1,
+       .dev = {
+               .platform_data = &roth_bt_rfkill_pdata,
+       },
+};
+
+static struct resource roth_bluesleep_resources[] = {
+       [0] = {
+               .name = "gpio_host_wake",
+                       .start  = TEGRA_GPIO_PU6,
+                       .end    = TEGRA_GPIO_PU6,
+                       .flags  = IORESOURCE_IO,
+       },
+       [1] = {
+               .name = "gpio_ext_wake",
+                       .start  = TEGRA_GPIO_PEE1,
+                       .end    = TEGRA_GPIO_PEE1,
+                       .flags  = IORESOURCE_IO,
+       },
+       [2] = {
+               .name = "host_wake",
+                       .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+       },
+};
+
+static struct platform_device roth_bluesleep_device = {
+       .name           = "bluesleep",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(roth_bluesleep_resources),
+       .resource       = roth_bluesleep_resources,
+};
+
+static noinline void __init roth_setup_bt_rfkill(void)
+{
+       if ((tegra_get_commchip_id() == COMMCHIP_BROADCOM_BCM43241) ||
+               (tegra_get_commchip_id() == COMMCHIP_DEFAULT))
+               roth_bt_rfkill_pdata.reset_gpio = TEGRA_GPIO_INVALID;
+       else
+               roth_bt_rfkill_pdata.reset_gpio = TEGRA_GPIO_PQ6;
+       platform_device_register(&roth_bt_rfkill_device);
+}
+
+static noinline void __init roth_setup_bluesleep(void)
+{
+       roth_bluesleep_resources[2].start =
+               roth_bluesleep_resources[2].end =
+                       gpio_to_irq(TEGRA_GPIO_PU6);
+       platform_device_register(&roth_bluesleep_device);
+       return;
+}
+static __initdata struct tegra_clk_init_table roth_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "pll_m",      NULL,           0,              false},
+       { "hda",        "pll_p",        108000000,      false},
+       { "hda2codec_2x", "pll_p",      48000000,       false},
+       { "pwm",        "pll_p",        3187500,        false},
+       { "blink",      "clk_32k",      32768,          true},
+       { "i2s1",       "pll_a_out0",   0,              false},
+       { "i2s3",       "pll_a_out0",   0,              false},
+       { "i2s4",       "pll_a_out0",   0,              false},
+       { "spdif_out",  "pll_a_out0",   0,              false},
+       { "d_audio",    "clk_m",        12000000,       false},
+       { "dam0",       "clk_m",        12000000,       false},
+       { "dam1",       "clk_m",        12000000,       false},
+       { "dam2",       "clk_m",        12000000,       false},
+       { "audio1",     "i2s1_sync",    0,              false},
+       { "audio3",     "i2s3_sync",    0,              false},
+       /* Setting vi_sensor-clk to true for validation purpose, will imapact
+        * power, later set to be false.*/
+       { "vi_sensor",  "pll_p",        150000000,      false},
+       { "cilab",      "pll_p",        150000000,      false},
+       { "cilcd",      "pll_p",        150000000,      false},
+       { "cile",       "pll_p",        150000000,      false},
+       { "i2c1",       "pll_p",        3200000,        false},
+       { "i2c2",       "pll_p",        3200000,        false},
+       { "i2c3",       "pll_p",        3200000,        false},
+       { "i2c4",       "pll_p",        3200000,        false},
+       { "i2c5",       "pll_p",        3200000,        false},
+       { NULL,         NULL,           0,              0},
+};
+
+static struct tegra_i2c_platform_data roth_i2c1_platform_data = {
+       .adapter_nr     = 0,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C1_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C1_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data roth_i2c2_platform_data = {
+       .adapter_nr     = 1,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .is_clkon_always = true,
+       .scl_gpio               = {TEGRA_GPIO_I2C2_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C2_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data roth_i2c3_platform_data = {
+       .adapter_nr     = 2,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C3_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C3_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data roth_i2c4_platform_data = {
+       .adapter_nr     = 3,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 10000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C4_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C4_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data roth_i2c5_platform_data = {
+       .adapter_nr     = 4,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_I2C5_SCL, 0},
+       .sda_gpio               = {TEGRA_GPIO_I2C5_SDA, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_11x_SOC)
+static struct i2c_board_info __initdata rt5640_board_info = {
+       I2C_BOARD_INFO("rt5640", 0x1c),
+};
+#endif
+
+static struct pn544_i2c_platform_data nfc_pdata = {
+       .irq_gpio = TEGRA_GPIO_PW2,
+       .ven_gpio = TEGRA_GPIO_PQ3,
+       .firm_gpio = TEGRA_GPIO_PH0,
+};
+
+static struct i2c_board_info __initdata nfc_board_info = {
+       I2C_BOARD_INFO("pn544", 0x28),
+       .platform_data = &nfc_pdata,
+};
+
+static void roth_i2c_init(void)
+{
+       tegra11_i2c_device1.dev.platform_data = &roth_i2c1_platform_data;
+       tegra11_i2c_device2.dev.platform_data = &roth_i2c2_platform_data;
+       tegra11_i2c_device3.dev.platform_data = &roth_i2c3_platform_data;
+       tegra11_i2c_device4.dev.platform_data = &roth_i2c4_platform_data;
+       tegra11_i2c_device5.dev.platform_data = &roth_i2c5_platform_data;
+
+       nfc_board_info.irq = gpio_to_irq(TEGRA_GPIO_PW2);
+       i2c_register_board_info(0, &nfc_board_info, 1);
+
+       platform_device_register(&tegra11_i2c_device5);
+       platform_device_register(&tegra11_i2c_device4);
+       platform_device_register(&tegra11_i2c_device3);
+       platform_device_register(&tegra11_i2c_device2);
+       platform_device_register(&tegra11_i2c_device1);
+
+       i2c_register_board_info(0, &rt5640_board_info, 1);
+}
+
+static struct platform_device *roth_uart_devices[] __initdata = {
+       &tegra_uarta_device,
+       &tegra_uartb_device,
+       &tegra_uartc_device,
+       &tegra_uartd_device,
+};
+static struct uart_clk_parent uart_parent_clk[] = {
+       [0] = {.name = "clk_m"},
+       [1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+       [2] = {.name = "pll_m"},
+#endif
+};
+
+static struct tegra_uart_platform_data roth_uart_pdata;
+static struct tegra_uart_platform_data roth_loopback_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+       int debug_port_id;
+
+       debug_port_id = uart_console_debug_init(3);
+       if (debug_port_id < 0)
+               return;
+
+       roth_uart_devices[debug_port_id] = uart_console_debug_device;
+}
+
+static void __init roth_uart_init(void)
+{
+       struct clk *c;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+               c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+               if (IS_ERR_OR_NULL(c)) {
+                       pr_err("Not able to get the clock for %s\n",
+                                               uart_parent_clk[i].name);
+                       continue;
+               }
+               uart_parent_clk[i].parent_clk = c;
+               uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+       }
+       roth_uart_pdata.parent_clk_list = uart_parent_clk;
+       roth_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+       roth_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
+       roth_loopback_uart_pdata.parent_clk_count =
+                                               ARRAY_SIZE(uart_parent_clk);
+       roth_loopback_uart_pdata.is_loopback = true;
+       tegra_uarta_device.dev.platform_data = &roth_uart_pdata;
+       tegra_uartb_device.dev.platform_data = &roth_uart_pdata;
+       tegra_uartc_device.dev.platform_data = &roth_uart_pdata;
+       tegra_uartd_device.dev.platform_data = &roth_uart_pdata;
+
+       /* Register low speed only if it is selected */
+       if (!is_tegra_debug_uartport_hs())
+               uart_debug_init();
+
+       platform_add_devices(roth_uart_devices,
+                               ARRAY_SIZE(roth_uart_devices));
+}
+
+static struct resource tegra_rtc_resources[] = {
+       [0] = {
+               .start = TEGRA_RTC_BASE,
+               .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = INT_RTC,
+               .end = INT_RTC,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_rtc_device = {
+       .name = "tegra_rtc",
+       .id   = -1,
+       .resource = tegra_rtc_resources,
+       .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct tegra_asoc_platform_data roth_audio_pdata = {
+       .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
+       .gpio_hp_det            = TEGRA_GPIO_HP_DET,
+       .gpio_hp_mute           = -1,
+       .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
+       .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
+       .gpio_ldo1_en           = TEGRA_GPIO_LDO1_EN,
+       .gpio_codec1 = TEGRA_GPIO_CODEC1_EN,
+       .gpio_codec2 = TEGRA_GPIO_CODEC2_EN,
+       .gpio_codec3 = TEGRA_GPIO_CODEC3_EN,
+       .i2s_param[HIFI_CODEC]  = {
+               .audio_port_id  = 1,
+               .is_i2s_master  = 1,
+               .i2s_mode       = TEGRA_DAIFMT_I2S,
+       },
+       .i2s_param[BT_SCO]      = {
+               .audio_port_id  = 3,
+               .is_i2s_master  = 1,
+               .i2s_mode       = TEGRA_DAIFMT_DSP_A,
+       },
+};
+
+static struct platform_device roth_audio_device = {
+       .name   = "tegra-snd-rt5640",
+       .id     = 0,
+       .dev    = {
+               .platform_data = &roth_audio_pdata,
+       },
+};
+
+static struct platform_device tegra_camera = {
+       .name = "tegra_camera",
+       .id = -1,
+};
+
+static struct platform_device *roth_devices[] __initdata = {
+       &tegra_pmu_device,
+       &tegra_rtc_device,
+       &tegra_udc_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
+       &tegra_smmu_device,
+#endif
+#if defined(CONFIG_TEGRA_AVP)
+       &tegra_avp_device,
+#endif
+       &tegra_camera,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+       &tegra11_se_device,
+#endif
+       &tegra_ahub_device,
+       &tegra_dam_device0,
+       &tegra_dam_device1,
+       &tegra_dam_device2,
+       &tegra_i2s_device1,
+       &tegra_i2s_device3,
+       &tegra_i2s_device4,
+       &tegra_spdif_device,
+       &spdif_dit_device,
+       &bluetooth_dit_device,
+       &roth_audio_device,
+       &tegra_hda_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+       &tegra_aes_device,
+#endif
+};
+
+#ifdef CONFIG_USB_SUPPORT
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_DEVICE,
+       .u_data.dev = {
+               .vbus_pmu_irq = 0,
+               .vbus_gpio = -1,
+               .charging_supported = false,
+               .remote_wakeup_supported = false,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+       .port_otg = true,
+       .has_hostpc = true,
+       .unaligned_dma_buf_supported = false,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = true,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+               .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 15,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+       .port_otg = false,
+       .has_hostpc = true,
+       .unaligned_dma_buf_supported = false,
+       .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+       .op_mode = TEGRA_USB_OPMODE_HOST,
+       .u_data.host = {
+               .vbus_gpio = -1,
+               .hot_plug = true,
+               .remote_wakeup_supported = true,
+               .power_off_on_suspend = true,
+       },
+       .u_cfg.utmi = {
+       .hssync_start_delay = 0,
+               .elastic_limit = 16,
+               .idle_wait_delay = 17,
+               .term_range_adj = 6,
+               .xcvr_setup = 8,
+               .xcvr_lsfslew = 2,
+               .xcvr_lsrslew = 2,
+               .xcvr_setup_offset = 0,
+               .xcvr_use_fuses = 1,
+       },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+       .ehci_device = &tegra_ehci1_device,
+       .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+static void roth_usb_init(void)
+{
+       tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+       platform_device_register(&tegra_otg_device);
+
+       /* Setup the udc platform data */
+       tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+
+       tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+       platform_device_register(&tegra_ehci3_device);
+}
+
+#else
+static void roth_usb_init(void) { }
+#endif
+
+static void roth_audio_init(void)
+{
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+
+       roth_audio_pdata.codec_name = "rt5640.0-001c";
+       roth_audio_pdata.codec_dai_name = "rt5640-aif1";
+}
+
+
+static struct platform_device *roth_spi_devices[] __initdata = {
+        &tegra11_spi_device4,
+};
+
+struct spi_clk_parent spi_parent_clk_roth[] = {
+        [0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+        [1] = {.name = "pll_m"},
+        [2] = {.name = "clk_m"},
+#else
+        [1] = {.name = "clk_m"},
+#endif
+};
+
+static struct tegra_spi_platform_data roth_spi_pdata = {
+       .is_dma_based           = false,
+       .max_dma_buffer         = 16 * 1024,
+        .is_clkon_always        = false,
+        .max_rate               = 25000000,
+};
+
+static void __init roth_spi_init(void)
+{
+        int i;
+        struct clk *c;
+        struct board_info board_info, display_board_info;
+
+        tegra_get_board_info(&board_info);
+        tegra_get_display_board_info(&display_board_info);
+
+        for (i = 0; i < ARRAY_SIZE(spi_parent_clk_roth); ++i) {
+                c = tegra_get_clock_by_name(spi_parent_clk_roth[i].name);
+                if (IS_ERR_OR_NULL(c)) {
+                        pr_err("Not able to get the clock for %s\n",
+                                                spi_parent_clk_roth[i].name);
+                        continue;
+                }
+                spi_parent_clk_roth[i].parent_clk = c;
+                spi_parent_clk_roth[i].fixed_clk_rate = clk_get_rate(c);
+        }
+        roth_spi_pdata.parent_clk_list = spi_parent_clk_roth;
+        roth_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk_roth);
+       tegra11_spi_device4.dev.platform_data = &roth_spi_pdata;
+        platform_add_devices(roth_spi_devices,
+                                ARRAY_SIZE(roth_spi_devices));
+}
+
+static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "extern2",    "pll_p",        41000000,       true},
+       { "clk_out_2",  "extern2",      40800000,       true},
+       { NULL,         NULL,           0,              0},
+};
+
+struct rm_spi_ts_platform_data rm31080ts_roth_data = {
+       .gpio_reset = 0,
+       .config = 0,
+};
+
+static struct tegra_spi_device_controller_data dev_cdata = {
+       .rx_clk_tap_delay = 0,
+       .tx_clk_tap_delay = 0,
+};
+
+struct spi_board_info rm31080a_roth_spi_board[1] = {
+       {
+        .modalias = "rm_ts_spidev",
+        .bus_num = 3,
+        .chip_select = 2,
+        .max_speed_hz = 12 * 1000 * 1000,
+        .mode = SPI_MODE_0,
+        .controller_data = &dev_cdata,
+        .platform_data = &rm31080ts_roth_data,
+        },
+};
+
+static int __init roth_touch_init(void)
+{
+       struct board_info board_info;
+
+       tegra_get_display_board_info(&board_info);
+       tegra_clk_init_from_table(touch_clk_init_table);
+       clk_enable(tegra_get_clock_by_name("clk_out_2"));
+       if (board_info.board_id == BOARD_E1582)
+               rm31080ts_roth_data.platform_id = RM_PLATFORM_P005;
+       else
+               rm31080ts_roth_data.platform_id = RM_PLATFORM_D010;
+       rm31080a_roth_spi_board[0].irq = gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
+       touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
+                               TOUCH_GPIO_RST_RAYDIUM_SPI,
+                               &rm31080ts_roth_data,
+                               &rm31080a_roth_spi_board[0],
+                               ARRAY_SIZE(rm31080a_roth_spi_board));
+       return 0;
+}
+
+static void __init tegra_roth_init(void)
+{
+
+       tegra_battery_edp_init(2500);
+       tegra_clk_init_from_table(roth_clk_init_table);
+       tegra_soc_device_init("roth");
+       tegra_enable_pinmux();
+       roth_pinmux_init();
+       roth_i2c_init();
+       roth_spi_init();
+       roth_usb_init();
+       roth_edp_init();
+       roth_uart_init();
+       roth_audio_init();
+       platform_add_devices(roth_devices, ARRAY_SIZE(roth_devices));
+       //tegra_ram_console_debug_init();
+       tegra_io_dpd_init();
+       roth_regulator_init();
+       roth_sdhci_init();
+       roth_suspend_init();
+       roth_emc_init();
+       roth_touch_init();
+       roth_panel_init();
+       roth_pmon_init();
+       roth_setup_bluesleep();
+       roth_setup_bt_rfkill();
+       tegra_release_bootloader_fb();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+       tegra_wdt_recovery_init();
+#endif
+       tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
+       roth_sensors_init();
+}
+
+static void __init roth_ramconsole_reserve(unsigned long size)
+{
+       tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+static void __init tegra_roth_dt_init(void)
+{
+       tegra_roth_init();
+
+       of_platform_populate(NULL,
+               of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init tegra_roth_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+       /* 1920*1200*4*2 = 18432000 bytes */
+       tegra_reserve(0, SZ_16M + SZ_2M, SZ_4M);
+#else
+       tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
+#endif
+       roth_ramconsole_reserve(SZ_1M);
+}
+
+static const char * const roth_dt_board_compat[] = {
+       "nvidia,roth",
+       NULL
+};
+
+MACHINE_START(ROTH, "roth")
+       .atag_offset    = 0x100,
+       .smp            = smp_ops(tegra_smp_ops),
+       .map_io         = tegra_map_common_io,
+       .reserve        = tegra_roth_reserve,
+       .init_early     = tegra11x_init_early,
+       .init_irq       = tegra_init_irq,
+       .handle_irq     = gic_handle_irq,
+       .timer          = &tegra_timer,
+       .init_machine   = tegra_roth_dt_init,
+       .restart        = tegra_assert_system_reset,
+       .dt_compat      = roth_dt_board_compat,
+MACHINE_END
index 77670b4..3b1306a 100644 (file)
 #ifndef _MACH_TEGRA_BOARD_ROTH_H
 #define _MACH_TEGRA_BOARD_ROTH_H
 
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <linux/mfd/max77663-core.h>
+#include "gpio-names.h"
+
+/* External peripheral act as gpio */
+/* MAX77663 GPIO */
+#define MAX77663_GPIO_BASE      TEGRA_NR_GPIOS
+#define PALMAS_TEGRA_GPIO_BASE TEGRA_NR_GPIOS
+#define MAX77663_GPIO_END       (MAX77663_GPIO_BASE + MAX77663_GPIO_NR)
+
+/* Hall Effect Sensor GPIO */
+#define TEGRA_GPIO_HALL                TEGRA_GPIO_PS0
+
+/* Audio-related GPIOs */
+#define TEGRA_GPIO_CDC_IRQ             TEGRA_GPIO_PW3
+#define TEGRA_GPIO_LDO1_EN             TEGRA_GPIO_PV3
+#define TEGRA_GPIO_CODEC1_EN   TEGRA_GPIO_PP3
+#define TEGRA_GPIO_CODEC2_EN   TEGRA_GPIO_PP1
+#define TEGRA_GPIO_CODEC3_EN   TEGRA_GPIO_PV0
+
+#define TEGRA_GPIO_SPKR_EN             -1
+#define TEGRA_GPIO_HP_DET              TEGRA_GPIO_PR7
+#define TEGRA_GPIO_INT_MIC_EN          TEGRA_GPIO_PK3
+#define TEGRA_GPIO_EXT_MIC_EN          TEGRA_GPIO_PK4
+
+#define TEGRA_GPIO_W_DISABLE           TEGRA_GPIO_PDD7
+#define TEGRA_GPIO_MODEM_RSVD1         TEGRA_GPIO_PV0
+#define TEGRA_GPIO_MODEM_RSVD2         TEGRA_GPIO_PH7
+
+/* External peripheral act as interrupt controller */
+/* MAX77663 IRQs */
+#define PALMAS_TEGRA_IRQ_BASE   TEGRA_NR_IRQS
+#define MAX77663_IRQ_BASE      TEGRA_NR_IRQS
+#define MAX77663_IRQ_END       (MAX77663_IRQ_BASE + MAX77663_IRQ_NR)
+#define MAX77663_IRQ_ACOK_RISING MAX77663_IRQ_ONOFF_ACOK_RISING
+
+/* I2C related GPIOs */
+#define TEGRA_GPIO_I2C1_SCL            TEGRA_GPIO_PC4
+#define TEGRA_GPIO_I2C1_SDA             TEGRA_GPIO_PC5
+#define TEGRA_GPIO_I2C2_SCL             TEGRA_GPIO_PT5
+#define TEGRA_GPIO_I2C2_SDA             TEGRA_GPIO_PT6
+#define TEGRA_GPIO_I2C3_SCL             TEGRA_GPIO_PBB1
+#define TEGRA_GPIO_I2C3_SDA             TEGRA_GPIO_PBB2
+#define TEGRA_GPIO_I2C4_SCL             TEGRA_GPIO_PV4
+#define TEGRA_GPIO_I2C4_SDA             TEGRA_GPIO_PV5
+#define TEGRA_GPIO_I2C5_SCL             TEGRA_GPIO_PZ6
+#define TEGRA_GPIO_I2C5_SDA             TEGRA_GPIO_PZ7
+
+/* Camera related GPIOs */
+#define CAM_RSTN                       TEGRA_GPIO_PBB3
+#define CAM_FLASH_STROBE               TEGRA_GPIO_PBB4
+#define CAM1_POWER_DWN_GPIO            TEGRA_GPIO_PBB5
+#define CAM2_POWER_DWN_GPIO            TEGRA_GPIO_PBB6
+#define CAM_AF_PWDN                    TEGRA_GPIO_PBB7
+#define CAM_GPIO1                      TEGRA_GPIO_PCC1
+#define CAM_GPIO2                      TEGRA_GPIO_PCC2
+
+/* Touchscreen definitions */
+#define TOUCH_GPIO_IRQ_RAYDIUM_SPI      TEGRA_GPIO_PK2
+#define TOUCH_GPIO_RST_RAYDIUM_SPI      TEGRA_GPIO_PK4
+
+/* Invensense MPU Definitions */
+#define MPU_GYRO_NAME           "mpu9150"
+#define MPU_GYRO_IRQ_GPIO       TEGRA_GPIO_PR3
+#define MPU_GYRO_ADDR           0x69
+#define MPU_GYRO_BUS_NUM        0
+#define MPU_GYRO_ORIENTATION    { -1, 0, 0, 0, -1, 0, 0, 0, 1 }
+#define MPU_ACCEL_NAME          "kxtf9"
+#define MPU_ACCEL_IRQ_GPIO      0 /* DISABLE ACCELIRQ:  TEGRA_GPIO_PJ2 */
+#define MPU_ACCEL_ADDR          0x0F
+#define MPU_ACCEL_BUS_NUM       0
+#define MPU_ACCEL_ORIENTATION   { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+#define MPU_COMPASS_NAME        "ak8975"
+#define MPU_COMPASS_IRQ_GPIO    0
+#define MPU_COMPASS_ADDR        0x0D
+#define MPU_COMPASS_BUS_NUM     0
+#define MPU_COMPASS_ORIENTATION { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
+
+
+int roth_regulator_init(void);
+int roth_suspend_init(void);
+int roth_sdhci_init(void);
+int roth_pinmux_init(void);
+int roth_sensors_init(void);
+int roth_emc_init(void);
+int roth_edp_init(void);
 int roth_panel_init(void);
+int roth_kbc_init(void);
+int roth_pmon_init(void);
 
 #endif