Merge branch 'akpm' (Andrew's patch-bomb)
Linus Torvalds [Tue, 9 Oct 2012 07:23:15 +0000 (16:23 +0900)]
Merge patches from Andrew Morton:
 "A few misc things and very nearly all of the MM tree.  A tremendous
  amount of stuff (again), including a significant rbtree library
  rework."

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (160 commits)
  sparc64: Support transparent huge pages.
  mm: thp: Use more portable PMD clearing sequenece in zap_huge_pmd().
  mm: Add and use update_mmu_cache_pmd() in transparent huge page code.
  sparc64: Document PGD and PMD layout.
  sparc64: Eliminate PTE table memory wastage.
  sparc64: Halve the size of PTE tables
  sparc64: Only support 4MB huge pages and 8KB base pages.
  memory-hotplug: suppress "Trying to free nonexistent resource <XXXXXXXXXXXXXXXX-YYYYYYYYYYYYYYYY>" warning
  mm: memcg: clean up mm_match_cgroup() signature
  mm: document PageHuge somewhat
  mm: use %pK for /proc/vmallocinfo
  mm, thp: fix mlock statistics
  mm, thp: fix mapped pages avoiding unevictable list on mlock
  memory-hotplug: update memory block's state and notify userspace
  memory-hotplug: preparation to notify memory block's state at memory hot remove
  mm: avoid section mismatch warning for memblock_type_name
  make GFP_NOTRACK definition unconditional
  cma: decrease cc.nr_migratepages after reclaiming pagelist
  CMA: migrate mlocked pages
  kpageflags: fix wrong KPF_THP on non-huge compound pages
  ...

298 files changed:
Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt [new file with mode: 0644]
Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt [new file with mode: 0644]
Documentation/devicetree/bindings/spi/spi-octeon.txt [new file with mode: 0644]
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arch/alpha/include/asm/Kbuild
arch/avr32/include/asm/Kbuild
arch/blackfin/Kconfig
arch/blackfin/configs/BF533-EZKIT_defconfig
arch/blackfin/configs/BF609-EZKIT_defconfig
arch/blackfin/kernel/bfin_gpio.c
arch/blackfin/kernel/reboot.c
arch/blackfin/mach-bf537/boards/cm_bf537e.c
arch/blackfin/mach-bf537/boards/stamp.c
arch/blackfin/mach-bf609/include/mach/defBF609.h
arch/blackfin/mach-common/cpufreq.c
arch/blackfin/mach-common/ints-priority.c
arch/blackfin/mach-common/smp.c
arch/cris/include/asm/Kbuild
arch/frv/include/asm/Kbuild
arch/h8300/include/asm/Kbuild
arch/hexagon/include/asm/Kbuild
arch/ia64/include/asm/Kbuild
arch/m32r/include/asm/Kbuild
arch/m68k/include/asm/Kbuild
arch/microblaze/include/asm/Kbuild
arch/mips/Kbuild.platforms
arch/mips/Kconfig
arch/mips/ath79/clock.c
arch/mips/ath79/dev-usb.c
arch/mips/ath79/mach-db120.c
arch/mips/bcm63xx/Makefile
arch/mips/bcm63xx/boards/board_bcm963xx.c
arch/mips/bcm63xx/clk.c
arch/mips/bcm63xx/dev-usb-usbd.c [new file with mode: 0644]
arch/mips/bcm63xx/irq.c
arch/mips/bcm63xx/setup.c
arch/mips/cavium-octeon/csrc-octeon.c
arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
arch/mips/cavium-octeon/octeon-irq.c
arch/mips/cavium-octeon/setup.c
arch/mips/configs/cavium_octeon_defconfig [moved from arch/mips/configs/cavium-octeon_defconfig with 100% similarity]
arch/mips/configs/mipssim_defconfig [deleted file]
arch/mips/configs/nlm_xlp_defconfig
arch/mips/configs/pnx8335_stb225_defconfig [moved from arch/mips/configs/pnx8335-stb225_defconfig with 100% similarity]
arch/mips/configs/pnx8550_jbs_defconfig [moved from arch/mips/configs/pnx8550-jbs_defconfig with 100% similarity]
arch/mips/configs/pnx8550_stb810_defconfig [moved from arch/mips/configs/pnx8550-stb810_defconfig with 100% similarity]
arch/mips/configs/sb1250_swarm_defconfig [moved from arch/mips/configs/sb1250-swarm_defconfig with 100% similarity]
arch/mips/configs/sead3_defconfig [new file with mode: 0644]
arch/mips/include/asm/cpu-features.h
arch/mips/include/asm/cpu.h
arch/mips/include/asm/gic.h
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h [new file with mode: 0644]
arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h [new file with mode: 0644]
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
arch/mips/include/asm/mach-cavium-octeon/irq.h
arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
arch/mips/include/asm/mach-lantiq/gpio.h
arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h [moved from arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h with 83% similarity]
arch/mips/include/asm/mach-sead3/irq.h [new file with mode: 0644]
arch/mips/include/asm/mach-sead3/kernel-entry-init.h [new file with mode: 0644]
arch/mips/include/asm/mach-sead3/war.h [moved from arch/mips/include/asm/mach-mipssim/war.h with 72% similarity]
arch/mips/include/asm/mips-boards/maltaint.h
arch/mips/include/asm/mips-boards/sead3int.h [new file with mode: 0644]
arch/mips/include/asm/mips-boards/simint.h [deleted file]
arch/mips/include/asm/mipsregs.h
arch/mips/include/asm/octeon/cvmx-agl-defs.h
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
arch/mips/include/asm/octeon/cvmx-ciu-defs.h
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h [new file with mode: 0644]
arch/mips/include/asm/octeon/cvmx-dbg-defs.h
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
arch/mips/include/asm/octeon/cvmx-iob-defs.h
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
arch/mips/include/asm/octeon/cvmx-l2t-defs.h
arch/mips/include/asm/octeon/cvmx-led-defs.h
arch/mips/include/asm/octeon/cvmx-mio-defs.h
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
arch/mips/include/asm/octeon/cvmx-mpi-defs.h [new file with mode: 0644]
arch/mips/include/asm/octeon/cvmx-npei-defs.h
arch/mips/include/asm/octeon/cvmx-npi-defs.h
arch/mips/include/asm/octeon/cvmx-pci-defs.h
arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
arch/mips/include/asm/octeon/cvmx-pip-defs.h
arch/mips/include/asm/octeon/cvmx-pko-defs.h
arch/mips/include/asm/octeon/cvmx-pow-defs.h
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
arch/mips/include/asm/octeon/cvmx-sli-defs.h
arch/mips/include/asm/octeon/cvmx-smix-defs.h
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
arch/mips/include/asm/octeon/octeon-model.h
arch/mips/include/asm/octeon/octeon.h
arch/mips/include/asm/pgtable-bits.h
arch/mips/include/asm/pgtable.h
arch/mips/include/asm/thread_info.h
arch/mips/include/asm/uasm.h
arch/mips/include/asm/unistd.h
arch/mips/kernel/Makefile
arch/mips/kernel/cevt-r4k.c
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/entry.S
arch/mips/kernel/irq-gic.c
arch/mips/kernel/scall32-o32.S
arch/mips/kernel/scall64-64.S
arch/mips/kernel/scall64-n32.S
arch/mips/kernel/scall64-o32.S
arch/mips/kernel/signal.c
arch/mips/kernel/smp-mt.c
arch/mips/lantiq/Kconfig
arch/mips/lantiq/falcon/prom.c
arch/mips/lantiq/falcon/sysctrl.c
arch/mips/lantiq/irq.c
arch/mips/lantiq/xway/Makefile
arch/mips/lantiq/xway/gpio.c [deleted file]
arch/mips/lantiq/xway/gptu.c [new file with mode: 0644]
arch/mips/lantiq/xway/sysctrl.c
arch/mips/lib/Makefile
arch/mips/mipssim/Makefile [deleted file]
arch/mips/mipssim/Platform [deleted file]
arch/mips/mipssim/sim_console.c [deleted file]
arch/mips/mipssim/sim_int.c [deleted file]
arch/mips/mipssim/sim_mem.c [deleted file]
arch/mips/mipssim/sim_platform.c [deleted file]
arch/mips/mipssim/sim_setup.c [deleted file]
arch/mips/mipssim/sim_smtc.c [deleted file]
arch/mips/mipssim/sim_time.c [deleted file]
arch/mips/mm/Makefile
arch/mips/mm/c-r4k.c
arch/mips/mm/cache.c
arch/mips/mm/fault.c
arch/mips/mm/tlb-r4k.c
arch/mips/mm/tlbex.c
arch/mips/mm/uasm.c
arch/mips/mti-malta/malta-int.c
arch/mips/mti-sead3/Makefile [new file with mode: 0644]
arch/mips/mti-sead3/Platform [new file with mode: 0644]
arch/mips/mti-sead3/leds-sead3.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-cmdline.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-console.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-display.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-ehci.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-i2c-dev.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-i2c-drv.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-i2c.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-init.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-int.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-lcd.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-leds.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-memory.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-mtd.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-net.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-pic32-bus.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-pic32-i2c-drv.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-platform.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-reset.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-serial.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-setup.c [new file with mode: 0644]
arch/mips/mti-sead3/sead3-time.c [new file with mode: 0644]
arch/mips/netlogic/Kconfig
arch/mips/netlogic/Makefile
arch/mips/netlogic/dts/Makefile [new file with mode: 0644]
arch/mips/netlogic/dts/xlp_evp.dts [new file with mode: 0644]
arch/mips/netlogic/xlp/Makefile
arch/mips/netlogic/xlp/of.c [deleted file]
arch/mips/netlogic/xlp/platform.c [deleted file]
arch/mips/netlogic/xlp/setup.c
arch/mn10300/include/asm/Kbuild
arch/openrisc/include/asm/Kbuild
arch/parisc/include/asm/Kbuild
arch/powerpc/include/asm/Kbuild
arch/s390/include/asm/Kbuild
arch/score/include/asm/Kbuild
arch/sparc/include/asm/Kbuild
arch/tile/include/asm/Kbuild
arch/um/include/asm/Kbuild
arch/unicore32/include/asm/Kbuild
arch/x86/include/asm/Kbuild
arch/xtensa/Kconfig
arch/xtensa/Makefile
arch/xtensa/boot/Makefile
arch/xtensa/boot/boot-elf/Makefile
arch/xtensa/boot/boot-elf/boot.lds.S
arch/xtensa/boot/boot-redboot/Makefile
arch/xtensa/boot/boot-redboot/boot.ld
arch/xtensa/boot/boot-redboot/bootstrap.S
arch/xtensa/boot/ramdisk/Makefile [deleted file]
arch/xtensa/configs/s6105_defconfig
arch/xtensa/include/asm/Kbuild
arch/xtensa/include/asm/io.h
arch/xtensa/include/asm/ioctls.h
arch/xtensa/include/asm/regs.h
arch/xtensa/kernel/Makefile
arch/xtensa/kernel/io.c [deleted file]
arch/xtensa/kernel/irq.c
arch/xtensa/kernel/pci-dma.c
arch/xtensa/kernel/pci.c
arch/xtensa/kernel/platform.c
arch/xtensa/kernel/setup.c
arch/xtensa/kernel/vmlinux.lds.S
arch/xtensa/kernel/xtensa_ksyms.c
arch/xtensa/platforms/iss/Makefile
arch/xtensa/platforms/iss/console.c
arch/xtensa/platforms/iss/include/platform/serial.h [new file with mode: 0644]
arch/xtensa/platforms/iss/include/platform/simcall.h
arch/xtensa/platforms/iss/io.c [deleted file]
arch/xtensa/platforms/iss/network.c
arch/xtensa/platforms/iss/setup.c
drivers/gpio/gpio-stp-xway.c
drivers/isdn/hisax/Kconfig
drivers/net/ethernet/broadcom/bcm63xx_enet.h
drivers/net/ethernet/octeon/octeon_mgmt.c
drivers/parport/Kconfig
drivers/pinctrl/Kconfig
drivers/pinctrl/Makefile
drivers/pinctrl/pinctrl-falcon.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-lantiq.c [new file with mode: 0644]
drivers/pinctrl/pinctrl-lantiq.h [new file with mode: 0644]
drivers/pinctrl/pinctrl-xway.c [new file with mode: 0644]
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/spi-octeon.c [new file with mode: 0644]
drivers/usb/musb/musb_io.h
fs/exofs/ore_raid.c
fs/exofs/sys.c
fs/fcntl.c
include/asm-generic/Kbuild
include/asm-generic/bitsperlong.h
include/asm-generic/clkdev.h [new file with mode: 0644]
include/asm-generic/int-l64.h
include/asm-generic/int-ll64.h
include/asm-generic/ioctl.h
include/asm-generic/kvm_para.h
include/asm-generic/param.h
include/asm-generic/resource.h
include/asm-generic/siginfo.h
include/asm-generic/signal.h
include/asm-generic/statfs.h
include/asm-generic/termios.h
include/asm-generic/unistd.h
include/asm-generic/xor.h
include/linux/pnfs_osd_xdr.h
include/uapi/asm-generic/Kbuild
include/uapi/asm-generic/auxvec.h [moved from include/asm-generic/auxvec.h with 100% similarity]
include/uapi/asm-generic/bitsperlong.h [new file with mode: 0644]
include/uapi/asm-generic/errno-base.h [moved from include/asm-generic/errno-base.h with 100% similarity]
include/uapi/asm-generic/errno.h [moved from include/asm-generic/errno.h with 100% similarity]
include/uapi/asm-generic/fcntl.h [moved from include/asm-generic/fcntl.h with 100% similarity]
include/uapi/asm-generic/int-l64.h [new file with mode: 0644]
include/uapi/asm-generic/int-ll64.h [new file with mode: 0644]
include/uapi/asm-generic/ioctl.h [new file with mode: 0644]
include/uapi/asm-generic/ioctls.h [moved from include/asm-generic/ioctls.h with 100% similarity]
include/uapi/asm-generic/ipcbuf.h [moved from include/asm-generic/ipcbuf.h with 100% similarity]
include/uapi/asm-generic/kvm_para.h [new file with mode: 0644]
include/uapi/asm-generic/mman-common.h [moved from include/asm-generic/mman-common.h with 100% similarity]
include/uapi/asm-generic/mman.h [moved from include/asm-generic/mman.h with 100% similarity]
include/uapi/asm-generic/msgbuf.h [moved from include/asm-generic/msgbuf.h with 100% similarity]
include/uapi/asm-generic/param.h [new file with mode: 0644]
include/uapi/asm-generic/poll.h [moved from include/asm-generic/poll.h with 100% similarity]
include/uapi/asm-generic/posix_types.h [moved from include/asm-generic/posix_types.h with 100% similarity]
include/uapi/asm-generic/resource.h [new file with mode: 0644]
include/uapi/asm-generic/sembuf.h [moved from include/asm-generic/sembuf.h with 100% similarity]
include/uapi/asm-generic/setup.h [moved from include/asm-generic/setup.h with 100% similarity]
include/uapi/asm-generic/shmbuf.h [moved from include/asm-generic/shmbuf.h with 100% similarity]
include/uapi/asm-generic/shmparam.h [moved from include/asm-generic/shmparam.h with 100% similarity]
include/uapi/asm-generic/siginfo.h [new file with mode: 0644]
include/uapi/asm-generic/signal-defs.h [moved from include/asm-generic/signal-defs.h with 100% similarity]
include/uapi/asm-generic/signal.h [new file with mode: 0644]
include/uapi/asm-generic/socket.h [moved from include/asm-generic/socket.h with 100% similarity]
include/uapi/asm-generic/sockios.h [moved from include/asm-generic/sockios.h with 100% similarity]
include/uapi/asm-generic/stat.h [moved from include/asm-generic/stat.h with 100% similarity]
include/uapi/asm-generic/statfs.h [new file with mode: 0644]
include/uapi/asm-generic/swab.h [moved from include/asm-generic/swab.h with 100% similarity]
include/uapi/asm-generic/termbits.h [moved from include/asm-generic/termbits.h with 100% similarity]
include/uapi/asm-generic/termios.h [new file with mode: 0644]
include/uapi/asm-generic/types.h [moved from include/asm-generic/types.h with 100% similarity]
include/uapi/asm-generic/ucontext.h [moved from include/asm-generic/ucontext.h with 100% similarity]
include/uapi/asm-generic/unistd.h [new file with mode: 0644]
scripts/mod/modpost.c
security/apparmor/Makefile

diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
new file mode 100644 (file)
index 0000000..daa7689
--- /dev/null
@@ -0,0 +1,83 @@
+Lantiq FALCON pinmux controller
+
+Required properties:
+- compatible: "lantiq,pinctrl-falcon"
+- reg: Should contain the physical address and length of the gpio/pinmux
+  register range
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Lantiq's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those group(s), and two pin configuration parameters:
+pull-up and open-drain
+
+The name of each subnode is not important as long as it is unique; all subnodes
+should be enumerated and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+We support 2 types of nodes.
+
+Definition of mux function groups:
+
+Required subnode-properties:
+- lantiq,groups : An array of strings. Each string contains the name of a group.
+  Valid values for these names are listed below.
+- lantiq,function: A string containing the name of the function to mux to the
+  group. Valid values for function names are listed below.
+
+Valid values for group and function names:
+
+  mux groups:
+    por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
+    jtag, slic, pcm, asc1
+
+  functions:
+    rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
+
+
+Definition of pin configurations:
+
+Required subnode-properties:
+- lantiq,pins : An array of strings. Each string contains the name of a pin.
+  Valid values for these names are listed below.
+
+Optional subnode-properties:
+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down
+- lantiq,drive-current: Boolean, enables drive-current
+- lantiq,slew-rate: Boolean, enables slew-rate
+
+Example:
+       pinmux0 {
+               compatible = "lantiq,pinctrl-falcon";
+               pinctrl-names = "default";
+               pinctrl-0 = <&state_default>;
+
+               state_default: pinmux {
+                       asc0 {
+                               lantiq,groups = "asc0";
+                               lantiq,function = "asc";
+                       };
+                       ntr {
+                               lantiq,groups = "ntr8k";
+                               lantiq,function = "ntr";
+                       };
+                       i2c {
+                               lantiq,groups = "i2c";
+                               lantiq,function = "i2c";
+                       };
+                       hrst {
+                               lantiq,groups = "hrst";
+                               lantiq,function = "rst";
+                       };
+               };
+       };
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
new file mode 100644 (file)
index 0000000..b5469db
--- /dev/null
@@ -0,0 +1,97 @@
+Lantiq XWAY pinmux controller
+
+Required properties:
+- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
+- reg: Should contain the physical address and length of the gpio/pinmux
+  register range
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Lantiq's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those group(s), and two pin configuration parameters:
+pull-up and open-drain
+
+The name of each subnode is not important as long as it is unique; all subnodes
+should be enumerated and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+We support 2 types of nodes.
+
+Definition of mux function groups:
+
+Required subnode-properties:
+- lantiq,groups : An array of strings. Each string contains the name of a group.
+  Valid values for these names are listed below.
+- lantiq,function: A string containing the name of the function to mux to the
+  group. Valid values for function names are listed below.
+
+Valid values for group and function names:
+
+  mux groups:
+    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
+    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
+    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
+    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
+    req3
+
+  additional mux groups (XR9 only):
+    mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
+
+  functions:
+    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
+
+
+
+Definition of pin configurations:
+
+Required subnode-properties:
+- lantiq,pins : An array of strings. Each string contains the name of a pin.
+  Valid values for these names are listed below.
+
+Optional subnode-properties:
+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down, 2: up.
+- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
+
+Valid values for XWAY pin names:
+  Pinconf pins can be referenced via the names io0-io31.
+
+Valid values for XR9 pin names:
+  Pinconf pins can be referenced via the names io0-io55.
+
+Example:
+       gpio: pinmux@E100B10 {
+               compatible = "lantiq,pinctrl-xway";
+               pinctrl-names = "default";
+               pinctrl-0 = <&state_default>;
+
+               #gpio-cells = <2>;
+               gpio-controller;
+               reg = <0xE100B10 0xA0>;
+
+               state_default: pinmux {
+                       stp {
+                               lantiq,groups = "stp";
+                               lantiq,function = "stp";
+                       };
+                       pci {
+                               lantiq,groups = "gnt1";
+                               lantiq,function = "pci";
+                       };
+                       conf_out {
+                               lantiq,pins = "io4", "io5", "io6"; /* stp */
+                               lantiq,open-drain;
+                               lantiq,pull = <0>;
+                       };
+               };
+       };
+
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
new file mode 100644 (file)
index 0000000..431add1
--- /dev/null
@@ -0,0 +1,33 @@
+Cavium, Inc. OCTEON SOC SPI master controller.
+
+Required properties:
+- compatible : "cavium,octeon-3010-spi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+       spi@1070000001000 {
+               compatible = "cavium,octeon-3010-spi";
+               reg = <0x10700 0x00001000 0x0 0x100>;
+               interrupts = <0 58>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               eeprom@0 {
+                       compatible = "st,m95256", "atmel,at25";
+                       reg = <0>;
+                       spi-max-frequency = <5000000>;
+                       spi-cpha;
+                       spi-cpol;
+
+                       pagesize = <64>;
+                       size = <32768>;
+                       address-width = <16>;
+               };
+       };
+
index 3f1131b..eae3cd8 100644 (file)
@@ -7178,6 +7178,8 @@ F:        drivers/char/tlclk.c
 
 TENSILICA XTENSA PORT (xtensa)
 M:     Chris Zankel <chris@zankel.net>
+M:     Max Filippov <jcmvbkbc@gmail.com>
+L:     linux-xtensa@linux-xtensa.org
 S:     Maintained
 F:     arch/xtensa/
 
index e423def..d97d663 100644 (file)
@@ -1,5 +1,7 @@
 include include/asm-generic/Kbuild.asm
 
+generic-y += clkdev.h
+
 header-y += compiler.h
 header-y += console.h
 header-y += fpu.h
index 3136628..e3ba7bc 100644 (file)
@@ -1,3 +1,5 @@
 include include/asm-generic/Kbuild.asm
 
+generic-y      += clkdev.h
+
 header-y       += cachectl.h
index 2169889..ccd9193 100644 (file)
@@ -299,7 +299,7 @@ config BF_REV_0_3
 
 config BF_REV_0_4
        bool "0.4"
-       depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
+       depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 
 config BF_REV_0_5
        bool "0.5"
index 127f20d..16273a9 100644 (file)
@@ -52,10 +52,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
+CONFIG_MTD_ROM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PLATRAM=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
index f4b0235..13eb732 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -24,7 +25,6 @@ CONFIG_BF609=y
 CONFIG_PINT1_ASSIGN=0x01010000
 CONFIG_PINT2_ASSIGN=0x07000101
 CONFIG_PINT3_ASSIGN=0x02020303
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IP_CHECKSUM_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
@@ -116,9 +116,6 @@ CONFIG_SND_PCM_OSS=m
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=m
-CONFIG_SND_BF6XX_I2S=m
-CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
-CONFIG_SND_SOC_ALL_CODECS=m
 CONFIG_USB=y
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_BLACKFIN=m
@@ -136,7 +133,6 @@ CONFIG_VFAT_FS=y
 CONFIG_JFFS2_FS=m
 CONFIG_UBIFS_FS=m
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_DEBUG_FS=y
@@ -149,9 +145,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_ARC4=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_BFIN_CRC=y
+CONFIG_CRYPTO_DEV_BFIN_CRC=m
index 83139aa..ed978f1 100644 (file)
@@ -1265,8 +1265,8 @@ static __init int gpio_register_proc(void)
 {
        struct proc_dir_entry *proc_gpio;
 
-       proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops);
-       return proc_gpio != NULL;
+       proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
+       return proc_gpio == NULL;
 }
 __initcall(gpio_register_proc);
 #endif
index 5272e6e..c4f50a3 100644 (file)
@@ -86,7 +86,6 @@ void native_machine_restart(char *cmd)
 void machine_restart(char *cmd)
 {
        native_machine_restart(cmd);
-       local_irq_disable();
        if (smp_processor_id())
                smp_call_function((void *)bfin_reset, 0, 1);
        else
index 9408ab5..85e4fc9 100644 (file)
@@ -25,6 +25,7 @@
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -143,6 +144,71 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
 
+#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+
+/* SPORT SPI controller data */
+static struct bfin5xx_spi_master bfin_sport_spi0_info = {
+       .num_chipselect = MAX_BLACKFIN_GPIOS,
+       .enable_dma = 0,  /* master don't support DMA */
+       .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
+               P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
+};
+
+static struct resource bfin_sport_spi0_resource[] = {
+       [0] = {
+               .start = SPORT0_TCR1,
+               .end   = SPORT0_TCR1 + 0xFF,
+               .flags = IORESOURCE_MEM,
+               },
+       [1] = {
+               .start = IRQ_SPORT0_ERROR,
+               .end   = IRQ_SPORT0_ERROR,
+               .flags = IORESOURCE_IRQ,
+               },
+};
+
+static struct platform_device bfin_sport_spi0_device = {
+       .name = "bfin-sport-spi",
+       .id = 1, /* Bus number */
+       .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
+       .resource = bfin_sport_spi0_resource,
+       .dev = {
+               .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
+       },
+};
+
+static struct bfin5xx_spi_master bfin_sport_spi1_info = {
+       .num_chipselect = MAX_BLACKFIN_GPIOS,
+       .enable_dma = 0,  /* master don't support DMA */
+       .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
+               P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
+};
+
+static struct resource bfin_sport_spi1_resource[] = {
+       [0] = {
+               .start = SPORT1_TCR1,
+               .end   = SPORT1_TCR1 + 0xFF,
+               .flags = IORESOURCE_MEM,
+               },
+       [1] = {
+               .start = IRQ_SPORT1_ERROR,
+               .end   = IRQ_SPORT1_ERROR,
+               .flags = IORESOURCE_IRQ,
+               },
+};
+
+static struct platform_device bfin_sport_spi1_device = {
+       .name = "bfin-sport-spi",
+       .id = 2, /* Bus number */
+       .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
+       .resource = bfin_sport_spi1_resource,
+       .dev = {
+               .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
+       },
+};
+
+#endif  /* sport spi master and devices */
+
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
@@ -512,6 +578,13 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
 
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
+|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+unsigned short bfin_sport0_peripherals[] = {
+       P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+       P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+};
+#endif
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
@@ -532,11 +605,6 @@ static struct resource bfin_sport0_uart_resources[] = {
        },
 };
 
-static unsigned short bfin_sport0_peripherals[] = {
-       P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-       P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
 static struct platform_device bfin_sport0_uart_device = {
        .name = "bfin-sport-uart",
        .id = 0,
@@ -582,6 +650,49 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
 #endif
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+static struct resource bfin_sport0_resources[] = {
+       {
+               .start = SPORT0_TCR1,
+               .end = SPORT0_MRCS3+4,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = IRQ_SPORT0_RX,
+               .end = IRQ_SPORT0_RX+1,
+               .flags = IORESOURCE_IRQ,
+       },
+       {
+               .start = IRQ_SPORT0_TX,
+               .end = IRQ_SPORT0_TX+1,
+               .flags = IORESOURCE_IRQ,
+       },
+       {
+               .start = IRQ_SPORT0_ERROR,
+               .end = IRQ_SPORT0_ERROR,
+               .flags = IORESOURCE_IRQ,
+       },
+       {
+               .start = CH_SPORT0_TX,
+               .end = CH_SPORT0_TX,
+               .flags = IORESOURCE_DMA,
+       },
+       {
+               .start = CH_SPORT0_RX,
+               .end = CH_SPORT0_RX,
+               .flags = IORESOURCE_DMA,
+       },
+};
+static struct platform_device bfin_sport0_device = {
+       .name = "bfin_sport_raw",
+       .id = 0,
+       .num_resources = ARRAY_SIZE(bfin_sport0_resources),
+       .resource = bfin_sport0_resources,
+       .dev = {
+               .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
+       },
+};
+#endif
 
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 #include <linux/bfin_mac.h>
@@ -684,6 +795,10 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 
        &bfin_dpmc,
 
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+       &bfin_sport0_device,
+#endif
+
 #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
        &hitachi_fb_device,
 #endif
@@ -744,6 +859,11 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
        &bfin_spi0_device,
 #endif
 
+#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+       &bfin_sport_spi0_device,
+       &bfin_sport_spi1_device,
+#endif
+
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
        &bfin_pata_device,
 #endif
index 307bd7e..95114ed 100644 (file)
@@ -1525,7 +1525,7 @@ static struct platform_device bfin_sport_spi1_device = {
 
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
-       .name = "bf537-lq035",
+       .name = "bf537_lq035",
 };
 #endif
 
index 19690cc..8045ade 100644 (file)
 #include "defBF60x_base.h"
 
 /* The following are the #defines needed by ADSP-BF609 that are not in the common header */
+/* =========================
+       PIXC Registers
+   ========================= */
+
+/* =========================
+       PIXC0
+   ========================= */
+#define PIXC0_CTL                   0xFFC19000         /* PIXC0 Control Register */
+#define PIXC0_PPL                   0xFFC19004         /* PIXC0 Pixels Per Line Register */
+#define PIXC0_LPF                   0xFFC19008         /* PIXC0 Line Per Frame Register */
+#define PIXC0_HSTART_A              0xFFC1900C         /* PIXC0 Overlay A Horizontal Start Register */
+#define PIXC0_HEND_A                0xFFC19010         /* PIXC0 Overlay A Horizontal End Register */
+#define PIXC0_VSTART_A              0xFFC19014         /* PIXC0 Overlay A Vertical Start Register */
+#define PIXC0_VEND_A                0xFFC19018         /* PIXC0 Overlay A Vertical End Register */
+#define PIXC0_TRANSP_A              0xFFC1901C         /* PIXC0 Overlay A Transparency Ratio Register */
+#define PIXC0_HSTART_B              0xFFC19020         /* PIXC0 Overlay B Horizontal Start Register */
+#define PIXC0_HEND_B                0xFFC19024         /* PIXC0 Overlay B Horizontal End Register */
+#define PIXC0_VSTART_B              0xFFC19028         /* PIXC0 Overlay B Vertical Start Register */
+#define PIXC0_VEND_B                0xFFC1902C         /* PIXC0 Overlay B Vertical End Register */
+#define PIXC0_TRANSP_B              0xFFC19030         /* PIXC0 Overlay B Transparency Ratio Register */
+#define PIXC0_IRQSTAT               0xFFC1903C         /* PIXC0 Interrupt Status Register */
+#define PIXC0_CONRY                 0xFFC19040         /* PIXC0 RY Conversion Component Register */
+#define PIXC0_CONGU                 0xFFC19044         /* PIXC0 GU Conversion Component Register */
+#define PIXC0_CONBV                 0xFFC19048         /* PIXC0 BV Conversion Component Register */
+#define PIXC0_CCBIAS                0xFFC1904C         /* PIXC0 Conversion Bias Register */
+#define PIXC0_TC                    0xFFC19050         /* PIXC0 Transparency Register */
+#define PIXC0_REVID                 0xFFC19054         /* PIXC0 PIXC Revision Id */
+
+/* =========================
+       PVP Registers
+   ========================= */
+
+/* =========================
+       PVP0
+   ========================= */
+#define PVP0_REVID                  0xFFC1A000         /* PVP0 Revision ID */
+#define PVP0_CTL                    0xFFC1A004         /* PVP0 Control */
+#define PVP0_IMSK0                  0xFFC1A008         /* PVP0 INTn interrupt line masks */
+#define PVP0_IMSK1                  0xFFC1A00C         /* PVP0 INTn interrupt line masks */
+#define PVP0_STAT                   0xFFC1A010         /* PVP0 Status */
+#define PVP0_ILAT                   0xFFC1A014         /* PVP0 Latched status */
+#define PVP0_IREQ0                  0xFFC1A018         /* PVP0 INT0 masked latched status */
+#define PVP0_IREQ1                  0xFFC1A01C         /* PVP0 INT0 masked latched status */
+#define PVP0_OPF0_CFG               0xFFC1A020         /* PVP0 Config */
+#define PVP0_OPF1_CFG               0xFFC1A040         /* PVP0 Config */
+#define PVP0_OPF2_CFG               0xFFC1A060         /* PVP0 Config */
+#define PVP0_OPF0_CTL               0xFFC1A024         /* PVP0 Control */
+#define PVP0_OPF1_CTL               0xFFC1A044         /* PVP0 Control */
+#define PVP0_OPF2_CTL               0xFFC1A064         /* PVP0 Control */
+#define PVP0_OPF3_CFG               0xFFC1A080         /* PVP0 Config */
+#define PVP0_OPF3_CTL               0xFFC1A084         /* PVP0 Control */
+#define PVP0_PEC_CFG                0xFFC1A0A0         /* PVP0 Config */
+#define PVP0_PEC_CTL                0xFFC1A0A4         /* PVP0 Control */
+#define PVP0_PEC_D1TH0              0xFFC1A0A8         /* PVP0 Lower Hysteresis Threshold */
+#define PVP0_PEC_D1TH1              0xFFC1A0AC         /* PVP0 Upper Hysteresis Threshold */
+#define PVP0_PEC_D2TH0              0xFFC1A0B0         /* PVP0 Weak Zero Crossing Threshold */
+#define PVP0_PEC_D2TH1              0xFFC1A0B4         /* PVP0 Strong Zero Crossing Threshold */
+#define PVP0_IIM0_CFG               0xFFC1A0C0         /* PVP0 Config */
+#define PVP0_IIM1_CFG               0xFFC1A0E0         /* PVP0 Config */
+#define PVP0_IIM0_CTL               0xFFC1A0C4         /* PVP0 Control */
+#define PVP0_IIM1_CTL               0xFFC1A0E4         /* PVP0 Control */
+#define PVP0_IIM0_SCALE             0xFFC1A0C8         /* PVP0 Scaler Values */
+#define PVP0_IIM1_SCALE             0xFFC1A0E8         /* PVP0 Scaler Values */
+#define PVP0_IIM0_SOVF_STAT         0xFFC1A0CC         /* PVP0 Signed Overflow Status */
+#define PVP0_IIM1_SOVF_STAT         0xFFC1A0EC         /* PVP0 Signed Overflow Status */
+#define PVP0_IIM0_UOVF_STAT         0xFFC1A0D0         /* PVP0 Unsigned Overflow Status */
+#define PVP0_IIM1_UOVF_STAT         0xFFC1A0F0         /* PVP0 Unsigned Overflow Status */
+#define PVP0_ACU_CFG                0xFFC1A100         /* PVP0 ACU Configuration Register */
+#define PVP0_ACU_CTL                0xFFC1A104         /* PVP0 ACU Control Register */
+#define PVP0_ACU_OFFSET             0xFFC1A108         /* PVP0 SUM constant register */
+#define PVP0_ACU_FACTOR             0xFFC1A10C         /* PVP0 PROD constant register */
+#define PVP0_ACU_SHIFT              0xFFC1A110         /* PVP0 Shift constant register */
+#define PVP0_ACU_MIN                0xFFC1A114         /* PVP0 Lower saturation threshold set to MIN */
+#define PVP0_ACU_MAX                0xFFC1A118         /* PVP0 Upper saturation threshold set to MAX */
+#define PVP0_UDS_CFG                0xFFC1A140         /* PVP0 UDS Configuration Register */
+#define PVP0_UDS_CTL                0xFFC1A144         /* PVP0 UDS Control Register */
+#define PVP0_UDS_OHCNT              0xFFC1A148         /* PVP0 UDS Output H Dimension */
+#define PVP0_UDS_OVCNT              0xFFC1A14C         /* PVP0 UDS Output V Dimension */
+#define PVP0_UDS_HAVG               0xFFC1A150         /* PVP0 UDS H Taps */
+#define PVP0_UDS_VAVG               0xFFC1A154         /* PVP0 UDS V Taps */
+#define PVP0_IPF0_CFG               0xFFC1A180         /* PVP0 Configuration */
+#define PVP0_IPF0_PIPECTL           0xFFC1A184         /* PVP0 Pipe Control */
+#define PVP0_IPF1_PIPECTL           0xFFC1A1C4         /* PVP0 Pipe Control */
+#define PVP0_IPF0_CTL               0xFFC1A188         /* PVP0 Control */
+#define PVP0_IPF1_CTL               0xFFC1A1C8         /* PVP0 Control */
+#define PVP0_IPF0_TAG               0xFFC1A18C         /* PVP0 TAG Value */
+#define PVP0_IPF1_TAG               0xFFC1A1CC         /* PVP0 TAG Value */
+#define PVP0_IPF0_FCNT              0xFFC1A190         /* PVP0 Frame Count */
+#define PVP0_IPF1_FCNT              0xFFC1A1D0         /* PVP0 Frame Count */
+#define PVP0_IPF0_HCNT              0xFFC1A194         /* PVP0 Horizontal Count */
+#define PVP0_IPF1_HCNT              0xFFC1A1D4         /* PVP0 Horizontal Count */
+#define PVP0_IPF0_VCNT              0xFFC1A198         /* PVP0 Vertical Count */
+#define PVP0_IPF1_VCNT              0xFFC1A1D8         /* PVP0 Vertical Count */
+#define PVP0_IPF0_HPOS              0xFFC1A19C         /* PVP0 Horizontal Position */
+#define PVP0_IPF0_VPOS              0xFFC1A1A0         /* PVP0 Vertical Position */
+#define PVP0_IPF0_TAG_STAT          0xFFC1A1A4         /* PVP0 TAG Status */
+#define PVP0_IPF1_TAG_STAT          0xFFC1A1E4         /* PVP0 TAG Status */
+#define PVP0_IPF1_CFG               0xFFC1A1C0         /* PVP0 Configuration */
+#define PVP0_CNV0_CFG               0xFFC1A200         /* PVP0 Configuration */
+#define PVP0_CNV1_CFG               0xFFC1A280         /* PVP0 Configuration */
+#define PVP0_CNV2_CFG               0xFFC1A300         /* PVP0 Configuration */
+#define PVP0_CNV3_CFG               0xFFC1A380         /* PVP0 Configuration */
+#define PVP0_CNV0_CTL               0xFFC1A204         /* PVP0 Control */
+#define PVP0_CNV1_CTL               0xFFC1A284         /* PVP0 Control */
+#define PVP0_CNV2_CTL               0xFFC1A304         /* PVP0 Control */
+#define PVP0_CNV3_CTL               0xFFC1A384         /* PVP0 Control */
+#define PVP0_CNV0_C00C01            0xFFC1A208         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV1_C00C01            0xFFC1A288         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV2_C00C01            0xFFC1A308         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV3_C00C01            0xFFC1A388         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV0_C02C03            0xFFC1A20C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV1_C02C03            0xFFC1A28C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV2_C02C03            0xFFC1A30C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV3_C02C03            0xFFC1A38C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV0_C04               0xFFC1A210         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV1_C04               0xFFC1A290         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV2_C04               0xFFC1A310         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV3_C04               0xFFC1A390         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV0_C10C11            0xFFC1A214         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV1_C10C11            0xFFC1A294         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV2_C10C11            0xFFC1A314         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV3_C10C11            0xFFC1A394         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV0_C12C13            0xFFC1A218         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV1_C12C13            0xFFC1A298         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV2_C12C13            0xFFC1A318         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV3_C12C13            0xFFC1A398         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV0_C14               0xFFC1A21C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV1_C14               0xFFC1A29C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV2_C14               0xFFC1A31C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV3_C14               0xFFC1A39C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV0_C20C21            0xFFC1A220         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV1_C20C21            0xFFC1A2A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV2_C20C21            0xFFC1A320         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV3_C20C21            0xFFC1A3A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV0_C22C23            0xFFC1A224         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV1_C22C23            0xFFC1A2A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV2_C22C23            0xFFC1A324         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV3_C22C23            0xFFC1A3A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV0_C24               0xFFC1A228         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV1_C24               0xFFC1A2A8         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV2_C24               0xFFC1A328         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV3_C24               0xFFC1A3A8         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV0_C30C31            0xFFC1A22C         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV1_C30C31            0xFFC1A2AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV2_C30C31            0xFFC1A32C         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV3_C30C31            0xFFC1A3AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV0_C32C33            0xFFC1A230         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV1_C32C33            0xFFC1A2B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV2_C32C33            0xFFC1A330         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV3_C32C33            0xFFC1A3B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV0_C34               0xFFC1A234         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV1_C34               0xFFC1A2B4         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV2_C34               0xFFC1A334         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV3_C34               0xFFC1A3B4         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV0_C40C41            0xFFC1A238         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV1_C40C41            0xFFC1A2B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV2_C40C41            0xFFC1A338         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV3_C40C41            0xFFC1A3B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV0_C42C43            0xFFC1A23C         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV1_C42C43            0xFFC1A2BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV2_C42C43            0xFFC1A33C         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV3_C42C43            0xFFC1A3BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV0_C44               0xFFC1A240         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV1_C44               0xFFC1A2C0         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV2_C44               0xFFC1A340         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV3_C44               0xFFC1A3C0         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV0_SCALE             0xFFC1A244         /* PVP0 Scaling factor */
+#define PVP0_CNV1_SCALE             0xFFC1A2C4         /* PVP0 Scaling factor */
+#define PVP0_CNV2_SCALE             0xFFC1A344         /* PVP0 Scaling factor */
+#define PVP0_CNV3_SCALE             0xFFC1A3C4         /* PVP0 Scaling factor */
+#define PVP0_THC0_CFG               0xFFC1A400         /* PVP0 Configuration */
+#define PVP0_THC1_CFG               0xFFC1A500         /* PVP0 Configuration */
+#define PVP0_THC0_CTL               0xFFC1A404         /* PVP0 Control */
+#define PVP0_THC1_CTL               0xFFC1A504         /* PVP0 Control */
+#define PVP0_THC0_HFCNT             0xFFC1A408         /* PVP0 Number of frames */
+#define PVP0_THC1_HFCNT             0xFFC1A508         /* PVP0 Number of frames */
+#define PVP0_THC0_RMAXREP           0xFFC1A40C         /* PVP0 Maximum number of RLE reports */
+#define PVP0_THC1_RMAXREP           0xFFC1A50C         /* PVP0 Maximum number of RLE reports */
+#define PVP0_THC0_CMINVAL           0xFFC1A410         /* PVP0 Min clip value */
+#define PVP0_THC1_CMINVAL           0xFFC1A510         /* PVP0 Min clip value */
+#define PVP0_THC0_CMINTH            0xFFC1A414         /* PVP0 Clip Min Threshold */
+#define PVP0_THC1_CMINTH            0xFFC1A514         /* PVP0 Clip Min Threshold */
+#define PVP0_THC0_CMAXTH            0xFFC1A418         /* PVP0 Clip Max Threshold */
+#define PVP0_THC1_CMAXTH            0xFFC1A518         /* PVP0 Clip Max Threshold */
+#define PVP0_THC0_CMAXVAL           0xFFC1A41C         /* PVP0 Max clip value */
+#define PVP0_THC1_CMAXVAL           0xFFC1A51C         /* PVP0 Max clip value */
+#define PVP0_THC0_TH0               0xFFC1A420         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH0               0xFFC1A520         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH1               0xFFC1A424         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH1               0xFFC1A524         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH2               0xFFC1A428         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH2               0xFFC1A528         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH3               0xFFC1A42C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH3               0xFFC1A52C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH4               0xFFC1A430         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH4               0xFFC1A530         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH5               0xFFC1A434         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH5               0xFFC1A534         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH6               0xFFC1A438         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH6               0xFFC1A538         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH7               0xFFC1A43C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH7               0xFFC1A53C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH8               0xFFC1A440         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH8               0xFFC1A540         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH9               0xFFC1A444         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH9               0xFFC1A544         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH10              0xFFC1A448         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH10              0xFFC1A548         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH11              0xFFC1A44C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH11              0xFFC1A54C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH12              0xFFC1A450         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH12              0xFFC1A550         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH13              0xFFC1A454         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH13              0xFFC1A554         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH14              0xFFC1A458         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH14              0xFFC1A558         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH15              0xFFC1A45C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH15              0xFFC1A55C         /* PVP0 Threshold Value */
+#define PVP0_THC0_HHPOS             0xFFC1A460         /* PVP0 Window start X-coordinate */
+#define PVP0_THC1_HHPOS             0xFFC1A560         /* PVP0 Window start X-coordinate */
+#define PVP0_THC0_HVPOS             0xFFC1A464         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC1_HVPOS             0xFFC1A564         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC0_HHCNT             0xFFC1A468         /* PVP0 Window width in X dimension */
+#define PVP0_THC1_HHCNT             0xFFC1A568         /* PVP0 Window width in X dimension */
+#define PVP0_THC0_HVCNT             0xFFC1A46C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC1_HVCNT             0xFFC1A56C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC0_RHPOS             0xFFC1A470         /* PVP0 Window start X-coordinate */
+#define PVP0_THC1_RHPOS             0xFFC1A570         /* PVP0 Window start X-coordinate */
+#define PVP0_THC0_RVPOS             0xFFC1A474         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC1_RVPOS             0xFFC1A574         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC0_RHCNT             0xFFC1A478         /* PVP0 Window width in X dimension */
+#define PVP0_THC1_RHCNT             0xFFC1A578         /* PVP0 Window width in X dimension */
+#define PVP0_THC0_RVCNT             0xFFC1A47C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC1_RVCNT             0xFFC1A57C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC0_HFCNT_STAT        0xFFC1A480         /* PVP0 Current Frame counter */
+#define PVP0_THC1_HFCNT_STAT        0xFFC1A580         /* PVP0 Current Frame counter */
+#define PVP0_THC0_HCNT0_STAT        0xFFC1A484         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT0_STAT        0xFFC1A584         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT1_STAT        0xFFC1A488         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT1_STAT        0xFFC1A588         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT2_STAT        0xFFC1A48C         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT2_STAT        0xFFC1A58C         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT3_STAT        0xFFC1A490         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT3_STAT        0xFFC1A590         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT4_STAT        0xFFC1A494         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT4_STAT        0xFFC1A594         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT5_STAT        0xFFC1A498         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT5_STAT        0xFFC1A598         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT6_STAT        0xFFC1A49C         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT6_STAT        0xFFC1A59C         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT7_STAT        0xFFC1A4A0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT7_STAT        0xFFC1A5A0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT8_STAT        0xFFC1A4A4         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT8_STAT        0xFFC1A5A4         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT9_STAT        0xFFC1A4A8         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT9_STAT        0xFFC1A5A8         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT10_STAT       0xFFC1A4AC         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT10_STAT       0xFFC1A5AC         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT11_STAT       0xFFC1A4B0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT11_STAT       0xFFC1A5B0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT12_STAT       0xFFC1A4B4         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT12_STAT       0xFFC1A5B4         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT13_STAT       0xFFC1A4B8         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT13_STAT       0xFFC1A5B8         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT14_STAT       0xFFC1A4BC         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT14_STAT       0xFFC1A5BC         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT15_STAT       0xFFC1A4C0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT15_STAT       0xFFC1A5C0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_RREP_STAT         0xFFC1A4C4         /* PVP0 Number of RLE Reports */
+#define PVP0_THC1_RREP_STAT         0xFFC1A5C4         /* PVP0 Number of RLE Reports */
+#define PVP0_PMA_CFG                0xFFC1A600         /* PVP0 PMA Configuration Register */
 
 #endif /* _DEF_BF609_H */
index c854a27..d88bd31 100644 (file)
@@ -77,15 +77,14 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
        csel = bfin_read32(CGU0_DIV) & 0x1F;
 #endif
 
-       for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
+       for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
                bfin_freq_table[index].frequency = cclk >> index;
 #ifndef CONFIG_BF60x
                dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
-               dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
 #else
                dpm_state_table[index].csel = csel;
-               dpm_state_table[index].tscale =  TIME_SCALE >> index;
 #endif
+               dpm_state_table[index].tscale =  (TIME_SCALE >> index) - 1;
 
                pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
                                                 bfin_freq_table[index].frequency,
@@ -135,7 +134,7 @@ static int bfin_target(struct cpufreq_policy *poli,
        unsigned int plldiv;
 #endif
        unsigned int index, cpu;
-       unsigned long flags, cclk_hz;
+       unsigned long cclk_hz;
        struct cpufreq_freqs freqs;
        static unsigned long lpj_ref;
        static unsigned int  lpj_ref_freq;
@@ -166,7 +165,6 @@ static int bfin_target(struct cpufreq_policy *poli,
 
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
                if (cpu == CPUFREQ_CPU) {
-                       flags = hard_local_irq_save();
 #ifndef CONFIG_BF60x
                        plldiv = (bfin_read_PLL_DIV() & SSEL) |
                                                dpm_state_table[index].csel;
@@ -195,7 +193,6 @@ static int bfin_target(struct cpufreq_policy *poli,
                                loops_per_jiffy = cpufreq_scale(lpj_ref,
                                                lpj_ref_freq, freqs.new);
                        }
-                       hard_local_irq_restore(flags);
                }
                /* TODO: just test case for cycles clock source, remove later */
                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
index 7ca09ec..902bebc 100644 (file)
@@ -1441,7 +1441,6 @@ int __init init_arch_irq(void)
                IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
                IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
-       bfin_sti(bfin_irq_flags);
 
        /* This implicitly covers ANOMALY_05000171
         * Boot-ROM code modifies SICA_IWRx wakeup registers
index a401513..bb61ae4 100644 (file)
@@ -146,7 +146,7 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
        platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 
        bfin_ipi_data = &__get_cpu_var(bfin_ipi);
-
+       smp_mb();
        while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) {
                msg = 0;
                do {
@@ -195,7 +195,7 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
        unsigned long flags;
 
        local_irq_save(flags);
-
+       smp_mb();
        for_each_cpu(cpu, cpumask) {
                bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
                smp_mb();
index 04d02a5..a8eab26 100644 (file)
@@ -7,3 +7,5 @@ header-y += ethernet.h
 header-y += etraxgpio.h
 header-y += rs485.h
 header-y += sync_serial.h
+
+generic-y += clkdev.h
index 5be6663..13cd044 100644 (file)
@@ -2,3 +2,4 @@ include include/asm-generic/Kbuild.asm
 
 header-y += registers.h
 header-y += termios.h
+generic-y += clkdev.h
index c68e168..0e152a9 100644 (file)
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+
+generic-y      += clkdev.h
index 0690642..3364b69 100644 (file)
@@ -7,6 +7,7 @@ header-y += user.h
 generic-y += auxvec.h
 generic-y += bug.h
 generic-y += bugs.h
+generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += current.h
 generic-y += device.h
index d4eb938..58f3d14 100644 (file)
@@ -13,3 +13,4 @@ header-y += ptrace_offsets.h
 header-y += rse.h
 header-y += ucontext.h
 header-y += ustack.h
+generic-y += clkdev.h
index c68e168..0e152a9 100644 (file)
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+
+generic-y      += clkdev.h
index a74e5d9..bfe675f 100644 (file)
@@ -2,6 +2,7 @@ include include/asm-generic/Kbuild.asm
 header-y += cachectl.h
 
 generic-y += bitsperlong.h
+generic-y += clkdev.h
 generic-y += cputime.h
 generic-y += device.h
 generic-y += emergency-restart.h
index db5294c..48510f6 100644 (file)
@@ -1,3 +1,4 @@
 include include/asm-generic/Kbuild.asm
 
 header-y  += elf.h
+generic-y += clkdev.h
index d64786d..91b9d69 100644 (file)
@@ -15,8 +15,8 @@ platforms += lantiq
 platforms += lasat
 platforms += loongson
 platforms += loongson1
-platforms += mipssim
 platforms += mti-malta
+platforms += mti-sead3
 platforms += netlogic
 platforms += pmc-sierra
 platforms += pnx833x
index 335115e..35453ea 100644 (file)
@@ -243,6 +243,8 @@ config LANTIQ
        select HAVE_MACH_CLKDEV
        select CLKDEV_LOOKUP
        select USE_OF
+       select PINCTRL
+       select PINCTRL_LANTIQ
 
 config LASAT
        bool "LASAT Networks platforms"
@@ -321,24 +323,35 @@ config MIPS_MALTA
          This enables support for the MIPS Technologies Malta evaluation
          board.
 
-config MIPS_SIM
-       bool 'MIPS simulator (MIPSsim)'
+config MIPS_SEAD3
+       bool "MIPS SEAD3 board"
+       select BOOT_ELF32
+       select BOOT_RAW
        select CEVT_R4K
        select CSRC_R4K
+       select CPU_MIPSR2_IRQ_VI
+       select CPU_MIPSR2_IRQ_EI
        select DMA_NONCOHERENT
-       select SYS_HAS_EARLY_PRINTK
        select IRQ_CPU
-       select BOOT_RAW
+       select IRQ_GIC
+       select MIPS_BOARDS_GEN
+       select MIPS_CPU_SCACHE
+       select MIPS_MSC
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_HAS_CPU_MIPS32_R2
+       select SYS_HAS_CPU_MIPS64_R1
        select SYS_HAS_EARLY_PRINTK
        select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
-       select SYS_SUPPORTS_MULTITHREADING
        select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_SUPPORTS_SMARTMIPS
+       select USB_ARCH_HAS_EHCI
+       select USB_EHCI_BIG_ENDIAN_DESC
+       select USB_EHCI_BIG_ENDIAN_MMIO
        help
-         This option enables support for MIPS Technologies MIPSsim software
-         emulator.
+         This enables support for the MIPS Technologies SEAD3 evaluation
+         board.
 
 config NEC_MARKEINS
        bool "NEC EMMA2RH Mark-eins board"
@@ -832,6 +845,7 @@ config NLM_XLP_BOARD
        select ZONE_DMA if 64BIT
        select SYNC_R4K
        select SYS_HAS_EARLY_PRINTK
+       select USE_OF
        help
          This board is based on Netlogic XLP Processor.
          Say Y here if you have a XLP based board.
@@ -1750,7 +1764,6 @@ config HARDWARE_WATCHPOINTS
 menu "Kernel type"
 
 choice
-
        prompt "Kernel code model"
        help
          You should only select this option if you have a workload that
@@ -1881,6 +1894,18 @@ config SIBYTE_DMA_PAGEOPS
 config CPU_HAS_PREFETCH
        bool
 
+config CPU_GENERIC_DUMP_TLB
+       bool
+       default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
+
+config CPU_R4K_FPU
+       bool
+       default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+
+config CPU_R4K_CACHE_TLB
+       bool
+       default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+
 choice
        prompt "MIPS MT options"
 
@@ -1956,7 +1981,6 @@ config SCHED_SMT
 config SYS_SUPPORTS_SCHED_SMT
        bool
 
-
 config SYS_SUPPORTS_MULTITHREADING
        bool
 
@@ -2361,12 +2385,10 @@ config SECCOMP
          If unsure, say Y. Only embedded should say N here.
 
 config USE_OF
-       bool "Flattened Device Tree support"
+       bool
        select OF
        select OF_EARLY_FLATTREE
        select IRQ_DOMAIN
-       help
-         Include support for flattened device tree machine descriptions.
 
 endmenu
 
index b91ad3e..579f452 100644 (file)
@@ -17,6 +17,8 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 
+#include <asm/div64.h>
+
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
@@ -166,11 +168,34 @@ static void __init ar933x_clocks_init(void)
        ath79_uart_clk.rate = ath79_ref_clk.rate;
 }
 
+static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
+                                     u32 frac, u32 out_div)
+{
+       u64 t;
+       u32 ret;
+
+       t = ath79_ref_clk.rate;
+       t *= nint;
+       do_div(t, ref_div);
+       ret = t;
+
+       t = ath79_ref_clk.rate;
+       t *= nfrac;
+       do_div(t, ref_div * frac);
+       ret += t;
+
+       ret /= (1 << out_div);
+       return ret;
+}
+
 static void __init ar934x_clocks_init(void)
 {
-       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
+       u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
        u32 cpu_pll, ddr_pll;
        u32 bootstrap;
+       void __iomem *dpll_base;
+
+       dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
 
        bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
        if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
@@ -178,33 +203,59 @@ static void __init ar934x_clocks_init(void)
        else
                ath79_ref_clk.rate = 25 * 1000 * 1000;
 
-       pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
-       out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-                 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
-       ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-                 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
-       nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
-              AR934X_PLL_CPU_CONFIG_NINT_MASK;
-       frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-              AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
-
-       cpu_pll = nint * ath79_ref_clk.rate / ref_div;
-       cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
-       cpu_pll /= (1 << out_div);
-
-       pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
-       out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-                 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
-       ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-                 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
-       nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
-              AR934X_PLL_DDR_CONFIG_NINT_MASK;
-       frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-              AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
-
-       ddr_pll = nint * ath79_ref_clk.rate / ref_div;
-       ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
-       ddr_pll /= (1 << out_div);
+       pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
+       if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
+               out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
+                         AR934X_SRIF_DPLL2_OUTDIV_MASK;
+               pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
+               nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
+                      AR934X_SRIF_DPLL1_NINT_MASK;
+               nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
+               ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
+                         AR934X_SRIF_DPLL1_REFDIV_MASK;
+               frac = 1 << 18;
+       } else {
+               pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
+               out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+                       AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+               ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+                         AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
+               nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
+                      AR934X_PLL_CPU_CONFIG_NINT_MASK;
+               nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+                       AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+               frac = 1 << 6;
+       }
+
+       cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
+                                     nfrac, frac, out_div);
+
+       pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
+       if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
+               out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
+                         AR934X_SRIF_DPLL2_OUTDIV_MASK;
+               pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
+               nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
+                      AR934X_SRIF_DPLL1_NINT_MASK;
+               nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
+               ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
+                         AR934X_SRIF_DPLL1_REFDIV_MASK;
+               frac = 1 << 18;
+       } else {
+               pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
+               out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+                         AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+               ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+                          AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
+               nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
+                      AR934X_PLL_DDR_CONFIG_NINT_MASK;
+               nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+                       AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+               frac = 1 << 10;
+       }
+
+       ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
+                                     nfrac, frac, out_div);
 
        clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
 
@@ -240,6 +291,8 @@ static void __init ar934x_clocks_init(void)
 
        ath79_wdt_clk.rate = ath79_ref_clk.rate;
        ath79_uart_clk.rate = ath79_ref_clk.rate;
+
+       iounmap(dpll_base);
 }
 
 void __init ath79_clocks_init(void)
index b2a2311..072bb9b 100644 (file)
 #include "common.h"
 #include "dev-usb.h"
 
-static struct resource ath79_ohci_resources[] = {
-       [0] = {
-               /* .start and .end fields are filled dynamically */
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = ATH79_MISC_IRQ_OHCI,
-               .end    = ATH79_MISC_IRQ_OHCI,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
+static struct resource ath79_ohci_resources[2];
 
 static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
 
@@ -54,17 +44,7 @@ static struct platform_device ath79_ohci_device = {
        },
 };
 
-static struct resource ath79_ehci_resources[] = {
-       [0] = {
-               /* .start and .end fields are filled dynamically */
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = ATH79_CPU_IRQ_USB,
-               .end    = ATH79_CPU_IRQ_USB,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
+static struct resource ath79_ehci_resources[2];
 
 static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
 
@@ -90,6 +70,20 @@ static struct platform_device ath79_ehci_device = {
        },
 };
 
+static void __init ath79_usb_init_resource(struct resource res[2],
+                                          unsigned long base,
+                                          unsigned long size,
+                                          int irq)
+{
+       res[0].flags = IORESOURCE_MEM;
+       res[0].start = base;
+       res[0].end = base + size - 1;
+
+       res[1].flags = IORESOURCE_IRQ;
+       res[1].start = irq;
+       res[1].end = irq;
+}
+
 #define AR71XX_USB_RESET_MASK  (AR71XX_RESET_USB_HOST | \
                                 AR71XX_RESET_USB_PHY | \
                                 AR71XX_RESET_USB_OHCI_DLL)
@@ -114,12 +108,12 @@ static void __init ath79_usb_setup(void)
 
        mdelay(900);
 
-       ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
-       ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
+       ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
+                               AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
        platform_device_register(&ath79_ohci_device);
 
-       ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
-       ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
+       ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
+                               AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
        ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
        platform_device_register(&ath79_ehci_device);
 }
@@ -143,10 +137,8 @@ static void __init ar7240_usb_setup(void)
 
        iounmap(usb_ctrl_base);
 
-       ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
-       ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
-       ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB;
-       ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB;
+       ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
+                               AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
        platform_device_register(&ath79_ohci_device);
 }
 
@@ -161,8 +153,8 @@ static void __init ar724x_usb_setup(void)
        ath79_device_reset_clear(AR724X_RESET_USB_PHY);
        mdelay(10);
 
-       ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
-       ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
+       ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
+                               AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
        ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
        platform_device_register(&ath79_ehci_device);
 }
@@ -178,8 +170,8 @@ static void __init ar913x_usb_setup(void)
        ath79_device_reset_clear(AR913X_RESET_USB_PHY);
        mdelay(10);
 
-       ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
-       ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
+       ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
+                               AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
        ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
        platform_device_register(&ath79_ehci_device);
 }
@@ -195,8 +187,34 @@ static void __init ar933x_usb_setup(void)
        ath79_device_reset_clear(AR933X_RESET_USB_PHY);
        mdelay(10);
 
-       ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
-       ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
+       ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
+                               AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
+       ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
+       platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar934x_usb_setup(void)
+{
+       u32 bootstrap;
+
+       bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+       if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+               return;
+
+       ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
+       udelay(1000);
+
+       ath79_device_reset_clear(AR934X_RESET_USB_PHY);
+       udelay(1000);
+
+       ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
+       udelay(1000);
+
+       ath79_device_reset_clear(AR934X_RESET_USB_HOST);
+       udelay(1000);
+
+       ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
+                               AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
        ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
        platform_device_register(&ath79_ehci_device);
 }
@@ -213,6 +231,8 @@ void __init ath79_register_usb(void)
                ar913x_usb_setup();
        else if (soc_is_ar933x())
                ar933x_usb_setup();
+       else if (soc_is_ar934x())
+               ar934x_usb_setup();
        else
                BUG();
 }
index 1983e4d..42f540a 100644 (file)
@@ -25,6 +25,7 @@
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
+#include "dev-usb.h"
 #include "dev-wmac.h"
 #include "pci.h"
 
@@ -126,6 +127,7 @@ static void __init db120_setup(void)
                                        db120_gpio_keys);
        ath79_register_spi(&db120_spi_data, db120_spi_info,
                           ARRAY_SIZE(db120_spi_info));
+       ath79_register_usb();
        ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
        db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 }
index 833af72..9bbb30a 100644 (file)
@@ -1,6 +1,6 @@
 obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
                   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
-                  dev-spi.o dev-uart.o dev-wdt.o
+                  dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
 obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 
 obj-y          += boards/
index dd18e4b..1cd4d73 100644 (file)
@@ -24,6 +24,7 @@
 #include <bcm63xx_dev_flash.h>
 #include <bcm63xx_dev_pcmcia.h>
 #include <bcm63xx_dev_spi.h>
+#include <bcm63xx_dev_usb_usbd.h>
 #include <board_bcm963xx.h>
 
 #define PFX    "board_bcm963xx: "
@@ -42,6 +43,12 @@ static struct board_info __initdata board_96328avng = {
 
        .has_uart0                      = 1,
        .has_pci                        = 1,
+       .has_usbd                       = 0,
+
+       .usbd = {
+               .use_fullspeed          = 0,
+               .port_no                = 0,
+       },
 
        .leds = {
                {
@@ -713,7 +720,7 @@ const char *board_get_name(void)
  */
 static int board_get_mac_address(u8 *mac)
 {
-       u8 *p;
+       u8 *oui;
        int count;
 
        if (mac_addr_used >= nvram.mac_addr_count) {
@@ -722,21 +729,23 @@ static int board_get_mac_address(u8 *mac)
        }
 
        memcpy(mac, nvram.mac_addr_base, ETH_ALEN);
-       p = mac + ETH_ALEN - 1;
+       oui = mac + ETH_ALEN/2 - 1;
        count = mac_addr_used;
 
        while (count--) {
+               u8 *p = mac + ETH_ALEN - 1;
+
                do {
                        (*p)++;
                        if (*p != 0)
                                break;
                        p--;
-               } while (p != mac);
-       }
+               } while (p != oui);
 
-       if (p == mac) {
-               printk(KERN_ERR PFX "unable to fetch mac address\n");
-               return -ENODEV;
+               if (p == oui) {
+                       printk(KERN_ERR PFX "unable to fetch mac address\n");
+                       return -ENODEV;
+               }
        }
 
        mac_addr_used++;
@@ -888,6 +897,9 @@ int __init board_register_devices(void)
            !board_get_mac_address(board.enet1.mac_addr))
                bcm63xx_enet_register(1, &board.enet1);
 
+       if (board.has_usbd)
+               bcm63xx_usbd_register(&board.usbd);
+
        if (board.has_dsp)
                bcm63xx_dsp_register(&board.dsp);
 
index 1db48ad..dff79ab 100644 (file)
@@ -160,7 +160,9 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-       if (BCMCPU_IS_6348())
+       if (BCMCPU_IS_6328())
+               bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
+       else if (BCMCPU_IS_6348())
                bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
        else if (BCMCPU_IS_6368())
                bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
@@ -171,6 +173,21 @@ static struct clk clk_usbh = {
 };
 
 /*
+ * USB device clock
+ */
+static void usbd_set(struct clk *clk, int enable)
+{
+       if (BCMCPU_IS_6328())
+               bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
+       else if (BCMCPU_IS_6368())
+               bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
+}
+
+static struct clk clk_usbd = {
+       .set    = usbd_set,
+};
+
+/*
  * SPI clock
  */
 static void spi_set(struct clk *clk, int enable)
@@ -284,6 +301,8 @@ struct clk *clk_get(struct device *dev, const char *id)
                return &clk_ephy;
        if (!strcmp(id, "usbh"))
                return &clk_usbh;
+       if (!strcmp(id, "usbd"))
+               return &clk_usbd;
        if (!strcmp(id, "spi"))
                return &clk_spi;
        if (!strcmp(id, "xtm"))
diff --git a/arch/mips/bcm63xx/dev-usb-usbd.c b/arch/mips/bcm63xx/dev-usb-usbd.c
new file mode 100644 (file)
index 0000000..508bd9d
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
+ * Copyright (C) 2012 Broadcom Corporation
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_usb_usbd.h>
+
+#define NUM_MMIO               2
+#define NUM_IRQ                        7
+
+static struct resource usbd_resources[NUM_MMIO + NUM_IRQ];
+
+static u64 usbd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device bcm63xx_usbd_device = {
+       .name           = "bcm63xx_udc",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(usbd_resources),
+       .resource       = usbd_resources,
+       .dev            = {
+               .dma_mask               = &usbd_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+};
+
+int __init bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd)
+{
+       const int irq_list[NUM_IRQ] = { IRQ_USBD,
+               IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0,
+               IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1,
+               IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };
+       int i;
+
+       if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
+               return 0;
+
+       usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);
+       usbd_resources[0].end = usbd_resources[0].start + RSET_USBD_SIZE - 1;
+       usbd_resources[0].flags = IORESOURCE_MEM;
+
+       usbd_resources[1].start = bcm63xx_regset_address(RSET_USBDMA);
+       usbd_resources[1].end = usbd_resources[1].start + RSET_USBDMA_SIZE - 1;
+       usbd_resources[1].flags = IORESOURCE_MEM;
+
+       for (i = 0; i < NUM_IRQ; i++) {
+               struct resource *r = &usbd_resources[NUM_MMIO + i];
+
+               r->start = r->end = bcm63xx_get_irq_number(irq_list[i]);
+               r->flags = IORESOURCE_IRQ;
+       }
+
+       platform_device_add_data(&bcm63xx_usbd_device, pd, sizeof(*pd));
+
+       return platform_device_register(&bcm63xx_usbd_device);
+}
index 18e051a..da24c2b 100644 (file)
@@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 #define is_ext_irq_cascaded    0
 #define ext_irq_start          0
 #define ext_irq_end            0
-#define ext_irq_count          0
-#define ext_irq_cfg_reg1       0
+#define ext_irq_count          4
+#define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_6345
 #define ext_irq_cfg_reg2       0
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
@@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void)
                irq_stat_addr += PERF_IRQSTAT_6338_REG;
                irq_mask_addr += PERF_IRQMASK_6338_REG;
                irq_bits = 32;
+               ext_irq_count = 4;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
                break;
        case BCM6345_CPU_ID:
                irq_stat_addr += PERF_IRQSTAT_6345_REG;
                irq_mask_addr += PERF_IRQMASK_6345_REG;
                irq_bits = 32;
+               ext_irq_count = 4;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
                break;
        case BCM6348_CPU_ID:
                irq_stat_addr += PERF_IRQSTAT_6348_REG;
@@ -434,7 +438,8 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
        reg = bcm_perf_readl(regaddr);
        irq %= 4;
 
-       if (BCMCPU_IS_6348()) {
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6348_CPU_ID:
                if (levelsense)
                        reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
                else
@@ -447,9 +452,13 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
                        reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
                else
                        reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
-       }
+               break;
 
-       if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+       case BCM6328_CPU_ID:
+       case BCM6338_CPU_ID:
+       case BCM6345_CPU_ID:
+       case BCM6358_CPU_ID:
+       case BCM6368_CPU_ID:
                if (levelsense)
                        reg |= EXTIRQ_CFG_LEVELSENSE(irq);
                else
@@ -462,6 +471,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
                        reg |= EXTIRQ_CFG_BOTHEDGE(irq);
                else
                        reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+               break;
+       default:
+               BUG();
        }
 
        bcm_perf_writel(reg, regaddr);
index 0e74a13..314231b 100644 (file)
@@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void)
        case BCM6338_CPU_ID:
                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
                break;
+       case BCM6345_CPU_ID:
+               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345;
+               break;
        case BCM6348_CPU_ID:
                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
                break;
@@ -83,6 +86,9 @@ void bcm63xx_machine_reboot(void)
        }
 
        for (i = 0; i < 2; i++) {
+               if (!perf_regs[i])
+                       break;
+
                reg = bcm_perf_readl(perf_regs[i]);
                if (BCMCPU_IS_6348()) {
                        reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
index ce6483a..0219395 100644 (file)
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2007 by Ralf Baechle
- * Copyright (C) 2009, 2010 Cavium Networks, Inc.
+ * Copyright (C) 2009, 2012 Cavium, Inc.
  */
 #include <linux/clocksource.h>
 #include <linux/export.h>
 #include <asm/octeon/cvmx-ipd-defs.h>
 #include <asm/octeon/cvmx-mio-defs.h>
 
+
+static u64 f;
+static u64 rdiv;
+static u64 sdiv;
+static u64 octeon_udelay_factor;
+static u64 octeon_ndelay_factor;
+
+void __init octeon_setup_delays(void)
+{
+       octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
+       /*
+        * For __ndelay we divide by 2^16, so the factor is multiplied
+        * by the same amount.
+        */
+       octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
+
+       preset_lpj = octeon_get_clock_rate() / HZ;
+
+       if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
+               union cvmx_mio_rst_boot rst_boot;
+               rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+               rdiv = rst_boot.s.c_mul;        /* CPU clock */
+               sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
+               f = (0x8000000000000000ull / sdiv) * 2;
+       }
+}
+
 /*
  * Set the current core's cvmcount counter to the value of the
  * IPD_CLK_COUNT.  We do this on all cores as they are brought
@@ -30,17 +57,6 @@ void octeon_init_cvmcount(void)
 {
        unsigned long flags;
        unsigned loops = 2;
-       u64 f = 0;
-       u64 rdiv = 0;
-       u64 sdiv = 0;
-       if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
-               union cvmx_mio_rst_boot rst_boot;
-               rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
-               rdiv = rst_boot.s.c_mul;        /* CPU clock */
-               sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
-               f = (0x8000000000000000ull / sdiv) * 2;
-       }
-
 
        /* Clobber loops so GCC will not unroll the following while loop. */
        asm("" : "+r" (loops));
@@ -57,9 +73,9 @@ void octeon_init_cvmcount(void)
                        if (f != 0) {
                                asm("dmultu\t%[cnt],%[f]\n\t"
                                    "mfhi\t%[cnt]"
-                                   : [cnt] "+r" (ipd_clk_count),
-                                     [f] "=r" (f)
-                                   : : "hi", "lo");
+                                   : [cnt] "+r" (ipd_clk_count)
+                                   : [f] "r" (f)
+                                   : "hi", "lo");
                        }
                }
                write_c0_cvmcount(ipd_clk_count);
@@ -109,21 +125,6 @@ void __init plat_time_init(void)
        clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
 }
 
-static u64 octeon_udelay_factor;
-static u64 octeon_ndelay_factor;
-
-void __init octeon_setup_delays(void)
-{
-       octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
-       /*
-        * For __ndelay we divide by 2^16, so the factor is multiplied
-        * by the same amount.
-        */
-       octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
-
-       preset_lpj = octeon_get_clock_rate() / HZ;
-}
-
 void __udelay(unsigned long us)
 {
        u64 cur, end, inc;
@@ -163,3 +164,35 @@ void __delay(unsigned long loops)
                cur = read_c0_cvmcount();
 }
 EXPORT_SYMBOL(__delay);
+
+
+/**
+ * octeon_io_clk_delay - wait for a given number of io clock cycles to pass.
+ *
+ * We scale the wait by the clock ratio, and then wait for the
+ * corresponding number of core clocks.
+ *
+ * @count: The number of clocks to wait.
+ */
+void octeon_io_clk_delay(unsigned long count)
+{
+       u64 cur, end;
+
+       cur = read_c0_cvmcount();
+       if (rdiv != 0) {
+               end = count * rdiv;
+               if (f != 0) {
+                       asm("dmultu\t%[cnt],%[f]\n\t"
+                               "mfhi\t%[cnt]"
+                               : [cnt] "+r" (end)
+                               : [f] "r" (f)
+                               : "hi", "lo");
+               }
+               end = cur + end;
+       } else {
+               end = cur + count;
+       }
+       while (end > cur)
+               cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(octeon_io_clk_delay);
index bea7538..560e034 100644 (file)
@@ -130,7 +130,7 @@ void __cvmx_interrupt_gmxx_enable(int interface)
        if (num_ports) {
                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
                    || OCTEON_IS_MODEL(OCTEON_CN58XX))
-                       gmx_tx_int_en.s.ncb_nxa = 1;
+                       gmx_tx_int_en.cn38xx.ncb_nxa = 1;
                gmx_tx_int_en.s.pko_nxa = 1;
        }
        gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
index 274cd4f..02b15ee 100644 (file)
 #include <linux/of.h>
 
 #include <asm/octeon/octeon.h>
-
-static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
-static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
+#include <asm/octeon/cvmx-ciu2-defs.h>
 
 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
 static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
+static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
 
 static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
 
@@ -29,8 +28,9 @@ union octeon_ciu_chip_data {
        void *p;
        unsigned long l;
        struct {
-               unsigned int line:6;
-               unsigned int bit:6;
+               unsigned long line:6;
+               unsigned long bit:6;
+               unsigned long gpio_line:6;
        } s;
 };
 
@@ -45,7 +45,7 @@ struct octeon_core_chip_data {
 
 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
 
-static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
+static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
                                       struct irq_chip *chip,
                                       irq_flow_handler_t handler)
 {
@@ -56,6 +56,7 @@ static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
        cd.l = 0;
        cd.s.line = line;
        cd.s.bit = bit;
+       cd.s.gpio_line = gpio_line;
 
        irq_set_chip_data(irq, cd.p);
        octeon_irq_ciu_to_irq[line][bit] = irq;
@@ -231,22 +232,31 @@ static void octeon_irq_ciu_enable(struct irq_data *data)
        unsigned long *pen;
        unsigned long flags;
        union octeon_ciu_chip_data cd;
+       raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
 
        cd.p = irq_data_get_irq_chip_data(data);
 
+       raw_spin_lock_irqsave(lock, flags);
        if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
                pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
-               set_bit(cd.s.bit, pen);
+               __set_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
        } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
                pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
-               set_bit(cd.s.bit, pen);
+               __set_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
        }
+       raw_spin_unlock_irqrestore(lock, flags);
 }
 
 static void octeon_irq_ciu_enable_local(struct irq_data *data)
@@ -254,22 +264,31 @@ static void octeon_irq_ciu_enable_local(struct irq_data *data)
        unsigned long *pen;
        unsigned long flags;
        union octeon_ciu_chip_data cd;
+       raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock);
 
        cd.p = irq_data_get_irq_chip_data(data);
 
+       raw_spin_lock_irqsave(lock, flags);
        if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
                pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
-               set_bit(cd.s.bit, pen);
+               __set_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
        } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
                pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
-               set_bit(cd.s.bit, pen);
+               __set_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
        }
+       raw_spin_unlock_irqrestore(lock, flags);
 }
 
 static void octeon_irq_ciu_disable_local(struct irq_data *data)
@@ -277,22 +296,31 @@ static void octeon_irq_ciu_disable_local(struct irq_data *data)
        unsigned long *pen;
        unsigned long flags;
        union octeon_ciu_chip_data cd;
+       raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock);
 
        cd.p = irq_data_get_irq_chip_data(data);
 
+       raw_spin_lock_irqsave(lock, flags);
        if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
                pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
-               clear_bit(cd.s.bit, pen);
+               __clear_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
        } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
                pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
-               clear_bit(cd.s.bit, pen);
+               __clear_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
                cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
        }
+       raw_spin_unlock_irqrestore(lock, flags);
 }
 
 static void octeon_irq_ciu_disable_all(struct irq_data *data)
@@ -301,29 +329,30 @@ static void octeon_irq_ciu_disable_all(struct irq_data *data)
        unsigned long *pen;
        int cpu;
        union octeon_ciu_chip_data cd;
-
-       wmb(); /* Make sure flag changes arrive before register updates. */
+       raw_spinlock_t *lock;
 
        cd.p = irq_data_get_irq_chip_data(data);
 
-       if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
+       for_each_online_cpu(cpu) {
+               int coreid = octeon_coreid_for_cpu(cpu);
+               lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
+               if (cd.s.line == 0)
                        pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
-                       clear_bit(cd.s.bit, pen);
-                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
-               }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
-       } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
+               else
                        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
-                       clear_bit(cd.s.bit, pen);
+
+               raw_spin_lock_irqsave(lock, flags);
+               __clear_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
+               if (cd.s.line == 0)
+                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+               else
                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
-               }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+               raw_spin_unlock_irqrestore(lock, flags);
        }
 }
 
@@ -333,27 +362,30 @@ static void octeon_irq_ciu_enable_all(struct irq_data *data)
        unsigned long *pen;
        int cpu;
        union octeon_ciu_chip_data cd;
+       raw_spinlock_t *lock;
 
        cd.p = irq_data_get_irq_chip_data(data);
 
-       if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
+       for_each_online_cpu(cpu) {
+               int coreid = octeon_coreid_for_cpu(cpu);
+               lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
+               if (cd.s.line == 0)
                        pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
-                       set_bit(cd.s.bit, pen);
-                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
-               }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
-       } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
+               else
                        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
-                       set_bit(cd.s.bit, pen);
+
+               raw_spin_lock_irqsave(lock, flags);
+               __set_bit(cd.s.bit, pen);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
+               if (cd.s.line == 0)
+                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+               else
                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
-               }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+               raw_spin_unlock_irqrestore(lock, flags);
        }
 }
 
@@ -435,7 +467,7 @@ static void octeon_irq_ciu_ack(struct irq_data *data)
        u64 mask;
        union octeon_ciu_chip_data cd;
 
-       cd.p = data->chip_data;
+       cd.p = irq_data_get_irq_chip_data(data);
        mask = 1ull << (cd.s.bit);
 
        if (cd.s.line == 0) {
@@ -456,9 +488,7 @@ static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
        u64 mask;
        union octeon_ciu_chip_data cd;
 
-       wmb(); /* Make sure flag changes arrive before register updates. */
-
-       cd.p = data->chip_data;
+       cd.p = irq_data_get_irq_chip_data(data);
        mask = 1ull << (cd.s.bit);
 
        if (cd.s.line == 0) {
@@ -486,7 +516,7 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
        u64 mask;
        union octeon_ciu_chip_data cd;
 
-       cd.p = data->chip_data;
+       cd.p = irq_data_get_irq_chip_data(data);
        mask = 1ull << (cd.s.bit);
 
        if (cd.s.line == 0) {
@@ -521,7 +551,7 @@ static void octeon_irq_gpio_setup(struct irq_data *data)
        cfg.s.fil_cnt = 7;
        cfg.s.fil_sel = 3;
 
-       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64);
+       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), cfg.u64);
 }
 
 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
@@ -549,7 +579,7 @@ static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
        union octeon_ciu_chip_data cd;
 
        cd.p = irq_data_get_irq_chip_data(data);
-       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
+       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
 
        octeon_irq_ciu_disable_all_v2(data);
 }
@@ -559,7 +589,7 @@ static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
        union octeon_ciu_chip_data cd;
 
        cd.p = irq_data_get_irq_chip_data(data);
-       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
+       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
 
        octeon_irq_ciu_disable_all(data);
 }
@@ -570,7 +600,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
        u64 mask;
 
        cd.p = irq_data_get_irq_chip_data(data);
-       mask = 1ull << (cd.s.bit - 16);
+       mask = 1ull << (cd.s.gpio_line);
 
        cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
 }
@@ -615,8 +645,10 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data,
        bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
        unsigned long flags;
        union octeon_ciu_chip_data cd;
+       unsigned long *pen;
+       raw_spinlock_t *lock;
 
-       cd.p = data->chip_data;
+       cd.p = irq_data_get_irq_chip_data(data);
 
        /*
         * For non-v2 CIU, we will allow only single CPU affinity.
@@ -629,36 +661,36 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data,
        if (!enable_one)
                return 0;
 
-       if (cd.s.line == 0) {
-               raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
-                       unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
 
-                       if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                               enable_one = false;
-                               set_bit(cd.s.bit, pen);
-                       } else {
-                               clear_bit(cd.s.bit, pen);
-                       }
-                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+       for_each_online_cpu(cpu) {
+               int coreid = octeon_coreid_for_cpu(cpu);
+
+               lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
+               raw_spin_lock_irqsave(lock, flags);
+
+               if (cd.s.line == 0)
+                       pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+               else
+                       pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = 0;
+                       __set_bit(cd.s.bit, pen);
+               } else {
+                       __clear_bit(cd.s.bit, pen);
                }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
-       } else {
-               raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-               for_each_online_cpu(cpu) {
-                       int coreid = octeon_coreid_for_cpu(cpu);
-                       unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+               /*
+                * Must be visible to octeon_irq_ip{2,3}_ciu() before
+                * enabling the irq.
+                */
+               wmb();
 
-                       if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                               enable_one = false;
-                               set_bit(cd.s.bit, pen);
-                       } else {
-                               clear_bit(cd.s.bit, pen);
-                       }
+               if (cd.s.line == 0)
+                       cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+               else
                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
-               }
-               raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+
+               raw_spin_unlock_irqrestore(lock, flags);
        }
        return 0;
 }
@@ -679,7 +711,7 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
        if (!enable_one)
                return 0;
 
-       cd.p = data->chip_data;
+       cd.p = irq_data_get_irq_chip_data(data);
        mask = 1ull << cd.s.bit;
 
        if (cd.s.line == 0) {
@@ -714,14 +746,6 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
 #endif
 
 /*
- * The v1 CIU code already masks things, so supply a dummy version to
- * the core chip code.
- */
-static void octeon_irq_dummy_mask(struct irq_data *data)
-{
-}
-
-/*
  * Newer octeon chips have support for lockless CIU operation.
  */
 static struct irq_chip octeon_irq_chip_ciu_v2 = {
@@ -742,7 +766,8 @@ static struct irq_chip octeon_irq_chip_ciu = {
        .irq_enable = octeon_irq_ciu_enable,
        .irq_disable = octeon_irq_ciu_disable_all,
        .irq_ack = octeon_irq_ciu_ack,
-       .irq_mask = octeon_irq_dummy_mask,
+       .irq_mask = octeon_irq_ciu_disable_local,
+       .irq_unmask = octeon_irq_ciu_enable,
 #ifdef CONFIG_SMP
        .irq_set_affinity = octeon_irq_ciu_set_affinity,
        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
@@ -766,6 +791,8 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = {
        .name = "CIU-M",
        .irq_enable = octeon_irq_ciu_enable_all,
        .irq_disable = octeon_irq_ciu_disable_all,
+       .irq_ack = octeon_irq_ciu_disable_local,
+       .irq_eoi = octeon_irq_ciu_enable_local,
 
        .irq_cpu_online = octeon_irq_ciu_enable_local,
        .irq_cpu_offline = octeon_irq_ciu_disable_local,
@@ -790,7 +817,8 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
        .name = "CIU-GPIO",
        .irq_enable = octeon_irq_ciu_enable_gpio,
        .irq_disable = octeon_irq_ciu_disable_gpio,
-       .irq_mask = octeon_irq_dummy_mask,
+       .irq_mask = octeon_irq_ciu_disable_local,
+       .irq_unmask = octeon_irq_ciu_enable,
        .irq_ack = octeon_irq_ciu_gpio_ack,
        .irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
@@ -809,12 +837,18 @@ static void octeon_irq_ciu_wd_enable(struct irq_data *data)
        unsigned long *pen;
        int coreid = data->irq - OCTEON_IRQ_WDOG0;      /* Bit 0-63 of EN1 */
        int cpu = octeon_cpu_for_coreid(coreid);
+       raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
 
-       raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+       raw_spin_lock_irqsave(lock, flags);
        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
-       set_bit(coreid, pen);
+       __set_bit(coreid, pen);
+       /*
+        * Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
+        * the irq.
+        */
+       wmb();
        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
-       raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+       raw_spin_unlock_irqrestore(lock, flags);
 }
 
 /*
@@ -843,7 +877,8 @@ static struct irq_chip octeon_irq_chip_ciu_wd = {
        .name = "CIU-W",
        .irq_enable = octeon_irq_ciu_wd_enable,
        .irq_disable = octeon_irq_ciu_disable_all,
-       .irq_mask = octeon_irq_dummy_mask,
+       .irq_mask = octeon_irq_ciu_disable_local,
+       .irq_unmask = octeon_irq_ciu_enable_local,
 };
 
 static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
@@ -976,19 +1011,20 @@ static int octeon_irq_ciu_map(struct irq_domain *d,
                return -EINVAL;
 
        if (octeon_irq_ciu_is_edge(line, bit))
-               octeon_irq_set_ciu_mapping(virq, line, bit,
+               octeon_irq_set_ciu_mapping(virq, line, bit, 0,
                                           octeon_irq_ciu_chip,
                                           handle_edge_irq);
        else
-               octeon_irq_set_ciu_mapping(virq, line, bit,
+               octeon_irq_set_ciu_mapping(virq, line, bit, 0,
                                           octeon_irq_ciu_chip,
                                           handle_level_irq);
 
        return 0;
 }
 
-static int octeon_irq_gpio_map(struct irq_domain *d,
-                              unsigned int virq, irq_hw_number_t hw)
+static int octeon_irq_gpio_map_common(struct irq_domain *d,
+                                     unsigned int virq, irq_hw_number_t hw,
+                                     int line_limit, struct irq_chip *chip)
 {
        struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
        unsigned int line, bit;
@@ -999,15 +1035,20 @@ static int octeon_irq_gpio_map(struct irq_domain *d,
        hw += gpiod->base_hwirq;
        line = hw >> 6;
        bit = hw & 63;
-       if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
+       if (line > line_limit || octeon_irq_ciu_to_irq[line][bit] != 0)
                return -EINVAL;
 
-       octeon_irq_set_ciu_mapping(virq, line, bit,
-                                  octeon_irq_gpio_chip,
-                                  octeon_irq_handle_gpio);
+       octeon_irq_set_ciu_mapping(virq, line, bit, hw,
+                                  chip, octeon_irq_handle_gpio);
        return 0;
 }
 
+static int octeon_irq_gpio_map(struct irq_domain *d,
+                              unsigned int virq, irq_hw_number_t hw)
+{
+       return octeon_irq_gpio_map_common(d, virq, hw, 1, octeon_irq_gpio_chip);
+}
+
 static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
        .map = octeon_irq_ciu_map,
        .xlate = octeon_irq_ciu_xlat,
@@ -1018,13 +1059,12 @@ static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
        .xlate = octeon_irq_gpio_xlat,
 };
 
-static void octeon_irq_ip2_v1(void)
+static void octeon_irq_ip2_ciu(void)
 {
        const unsigned long core_id = cvmx_get_core_num();
        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
 
        ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
-       clear_c0_status(STATUSF_IP2);
        if (likely(ciu_sum)) {
                int bit = fls64(ciu_sum) - 1;
                int irq = octeon_irq_ciu_to_irq[0][bit];
@@ -1035,32 +1075,13 @@ static void octeon_irq_ip2_v1(void)
        } else {
                spurious_interrupt();
        }
-       set_c0_status(STATUSF_IP2);
 }
 
-static void octeon_irq_ip2_v2(void)
-{
-       const unsigned long core_id = cvmx_get_core_num();
-       u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
-
-       ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
-       if (likely(ciu_sum)) {
-               int bit = fls64(ciu_sum) - 1;
-               int irq = octeon_irq_ciu_to_irq[0][bit];
-               if (likely(irq))
-                       do_IRQ(irq);
-               else
-                       spurious_interrupt();
-       } else {
-               spurious_interrupt();
-       }
-}
-static void octeon_irq_ip3_v1(void)
+static void octeon_irq_ip3_ciu(void)
 {
        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
 
        ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
-       clear_c0_status(STATUSF_IP3);
        if (likely(ciu_sum)) {
                int bit = fls64(ciu_sum) - 1;
                int irq = octeon_irq_ciu_to_irq[1][bit];
@@ -1071,24 +1092,13 @@ static void octeon_irq_ip3_v1(void)
        } else {
                spurious_interrupt();
        }
-       set_c0_status(STATUSF_IP3);
 }
 
-static void octeon_irq_ip3_v2(void)
-{
-       u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
+static bool octeon_irq_use_ip4;
 
-       ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
-       if (likely(ciu_sum)) {
-               int bit = fls64(ciu_sum) - 1;
-               int irq = octeon_irq_ciu_to_irq[1][bit];
-               if (likely(irq))
-                       do_IRQ(irq);
-               else
-                       spurious_interrupt();
-       } else {
-               spurious_interrupt();
-       }
+static void __cpuinit octeon_irq_local_enable_ip4(void *arg)
+{
+       set_c0_status(STATUSF_IP4);
 }
 
 static void octeon_irq_ip4_mask(void)
@@ -1103,6 +1113,13 @@ static void (*octeon_irq_ip4)(void);
 
 void __cpuinitdata (*octeon_irq_setup_secondary)(void);
 
+void __cpuinit octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t h)
+{
+       octeon_irq_ip4 = h;
+       octeon_irq_use_ip4 = true;
+       on_each_cpu(octeon_irq_local_enable_ip4, NULL, 1);
+}
+
 static void __cpuinit octeon_irq_percpu_enable(void)
 {
        irq_cpu_online();
@@ -1111,6 +1128,12 @@ static void __cpuinit octeon_irq_percpu_enable(void)
 static void __cpuinit octeon_irq_init_ciu_percpu(void)
 {
        int coreid = cvmx_get_core_num();
+
+
+       __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
+       __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
+       wmb();
+       raw_spin_lock_init(&__get_cpu_var(octeon_irq_ciu_spinlock));
        /*
         * Disable All CIU Interrupts. The ones we need will be
         * enabled later.  Read the SUM register so we know the write
@@ -1123,12 +1146,30 @@ static void __cpuinit octeon_irq_init_ciu_percpu(void)
        cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
 }
 
-static void __cpuinit octeon_irq_setup_secondary_ciu(void)
+static void octeon_irq_init_ciu2_percpu(void)
 {
+       u64 regx, ipx;
+       int coreid = cvmx_get_core_num();
+       u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid);
 
-       __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
-       __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
+       /*
+        * Disable All CIU2 Interrupts. The ones we need will be
+        * enabled later.  Read the SUM register so we know the write
+        * completed.
+        *
+        * There are 9 registers and 3 IPX levels with strides 0x1000
+        * and 0x200 respectivly.  Use loops to clear them.
+        */
+       for (regx = 0; regx <= 0x8000; regx += 0x1000) {
+               for (ipx = 0; ipx <= 0x400; ipx += 0x200)
+                       cvmx_write_csr(base + regx + ipx, 0);
+       }
 
+       cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid));
+}
+
+static void __cpuinit octeon_irq_setup_secondary_ciu(void)
+{
        octeon_irq_init_ciu_percpu();
        octeon_irq_percpu_enable();
 
@@ -1137,6 +1178,19 @@ static void __cpuinit octeon_irq_setup_secondary_ciu(void)
        clear_c0_status(STATUSF_IP4);
 }
 
+static void octeon_irq_setup_secondary_ciu2(void)
+{
+       octeon_irq_init_ciu2_percpu();
+       octeon_irq_percpu_enable();
+
+       /* Enable the CIU lines */
+       set_c0_status(STATUSF_IP3 | STATUSF_IP2);
+       if (octeon_irq_use_ip4)
+               set_c0_status(STATUSF_IP4);
+       else
+               clear_c0_status(STATUSF_IP4);
+}
+
 static void __init octeon_irq_init_ciu(void)
 {
        unsigned int i;
@@ -1150,19 +1204,17 @@ static void __init octeon_irq_init_ciu(void)
        octeon_irq_init_ciu_percpu();
        octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
 
+       octeon_irq_ip2 = octeon_irq_ip2_ciu;
+       octeon_irq_ip3 = octeon_irq_ip3_ciu;
        if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
            OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
-               octeon_irq_ip2 = octeon_irq_ip2_v2;
-               octeon_irq_ip3 = octeon_irq_ip3_v2;
                chip = &octeon_irq_chip_ciu_v2;
                chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
                chip_wd = &octeon_irq_chip_ciu_wd_v2;
                octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
        } else {
-               octeon_irq_ip2 = octeon_irq_ip2_v1;
-               octeon_irq_ip3 = octeon_irq_ip3_v1;
                chip = &octeon_irq_chip_ciu;
                chip_mbox = &octeon_irq_chip_ciu_mbox;
                chip_wd = &octeon_irq_chip_ciu_wd;
@@ -1192,6 +1244,7 @@ static void __init octeon_irq_init_ciu(void)
        ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
        if (ciu_node) {
                ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
+               irq_set_default_host(ciu_domain);
                of_node_put(ciu_node);
        } else
                panic("Cannot find device node for cavium,octeon-3860-ciu.");
@@ -1200,8 +1253,8 @@ static void __init octeon_irq_init_ciu(void)
        for (i = 0; i < 16; i++)
                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
 
-       octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
-       octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
+       octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq);
+       octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
 
        for (i = 0; i < 4; i++)
                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
@@ -1217,7 +1270,7 @@ static void __init octeon_irq_init_ciu(void)
 
        /* CIU_1 */
        for (i = 0; i < 16; i++)
-               octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
+               octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, 0, chip_wd, handle_level_irq);
 
        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
 
@@ -1226,6 +1279,466 @@ static void __init octeon_irq_init_ciu(void)
        clear_c0_status(STATUSF_IP4);
 }
 
+/*
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu2_wd_enable(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = data->irq - OCTEON_IRQ_WDOG0;
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
+       cvmx_write_csr(en_addr, mask);
+
+}
+
+static void octeon_irq_ciu2_enable(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int cpu = next_cpu_for_irq(data);
+       int coreid = octeon_coreid_for_cpu(cpu);
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
+       cvmx_write_csr(en_addr, mask);
+}
+
+static void octeon_irq_ciu2_enable_local(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = cvmx_get_core_num();
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(coreid) + (0x1000ull * cd.s.line);
+       cvmx_write_csr(en_addr, mask);
+
+}
+
+static void octeon_irq_ciu2_disable_local(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = cvmx_get_core_num();
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(coreid) + (0x1000ull * cd.s.line);
+       cvmx_write_csr(en_addr, mask);
+
+}
+
+static void octeon_irq_ciu2_ack(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = cvmx_get_core_num();
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd.s.line);
+       cvmx_write_csr(en_addr, mask);
+
+}
+
+static void octeon_irq_ciu2_disable_all(struct irq_data *data)
+{
+       int cpu;
+       u64 mask;
+       union octeon_ciu_chip_data cd;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << (cd.s.bit);
+
+       for_each_online_cpu(cpu) {
+               u64 en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
+               cvmx_write_csr(en_addr, mask);
+       }
+}
+
+static void octeon_irq_ciu2_mbox_enable_all(struct irq_data *data)
+{
+       int cpu;
+       u64 mask;
+
+       mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
+
+       for_each_online_cpu(cpu) {
+               u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(octeon_coreid_for_cpu(cpu));
+               cvmx_write_csr(en_addr, mask);
+       }
+}
+
+static void octeon_irq_ciu2_mbox_disable_all(struct irq_data *data)
+{
+       int cpu;
+       u64 mask;
+
+       mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
+
+       for_each_online_cpu(cpu) {
+               u64 en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(octeon_coreid_for_cpu(cpu));
+               cvmx_write_csr(en_addr, mask);
+       }
+}
+
+static void octeon_irq_ciu2_mbox_enable_local(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = cvmx_get_core_num();
+
+       mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
+       en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(coreid);
+       cvmx_write_csr(en_addr, mask);
+}
+
+static void octeon_irq_ciu2_mbox_disable_local(struct irq_data *data)
+{
+       u64 mask;
+       u64 en_addr;
+       int coreid = cvmx_get_core_num();
+
+       mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0);
+       en_addr = CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(coreid);
+       cvmx_write_csr(en_addr, mask);
+}
+
+#ifdef CONFIG_SMP
+static int octeon_irq_ciu2_set_affinity(struct irq_data *data,
+                                       const struct cpumask *dest, bool force)
+{
+       int cpu;
+       bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
+       u64 mask;
+       union octeon_ciu_chip_data cd;
+
+       if (!enable_one)
+               return 0;
+
+       cd.p = irq_data_get_irq_chip_data(data);
+       mask = 1ull << cd.s.bit;
+
+       for_each_online_cpu(cpu) {
+               u64 en_addr;
+               if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                       enable_one = false;
+                       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
+               } else {
+                       en_addr = CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd.s.line);
+               }
+               cvmx_write_csr(en_addr, mask);
+       }
+
+       return 0;
+}
+#endif
+
+static void octeon_irq_ciu2_enable_gpio(struct irq_data *data)
+{
+       octeon_irq_gpio_setup(data);
+       octeon_irq_ciu2_enable(data);
+}
+
+static void octeon_irq_ciu2_disable_gpio(struct irq_data *data)
+{
+       union octeon_ciu_chip_data cd;
+       cd.p = irq_data_get_irq_chip_data(data);
+
+       cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.gpio_line), 0);
+
+       octeon_irq_ciu2_disable_all(data);
+}
+
+static struct irq_chip octeon_irq_chip_ciu2 = {
+       .name = "CIU2-E",
+       .irq_enable = octeon_irq_ciu2_enable,
+       .irq_disable = octeon_irq_ciu2_disable_all,
+       .irq_ack = octeon_irq_ciu2_ack,
+       .irq_mask = octeon_irq_ciu2_disable_local,
+       .irq_unmask = octeon_irq_ciu2_enable,
+#ifdef CONFIG_SMP
+       .irq_set_affinity = octeon_irq_ciu2_set_affinity,
+       .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
+#endif
+};
+
+static struct irq_chip octeon_irq_chip_ciu2_mbox = {
+       .name = "CIU2-M",
+       .irq_enable = octeon_irq_ciu2_mbox_enable_all,
+       .irq_disable = octeon_irq_ciu2_mbox_disable_all,
+       .irq_ack = octeon_irq_ciu2_mbox_disable_local,
+       .irq_eoi = octeon_irq_ciu2_mbox_enable_local,
+
+       .irq_cpu_online = octeon_irq_ciu2_mbox_enable_local,
+       .irq_cpu_offline = octeon_irq_ciu2_mbox_disable_local,
+       .flags = IRQCHIP_ONOFFLINE_ENABLED,
+};
+
+static struct irq_chip octeon_irq_chip_ciu2_wd = {
+       .name = "CIU2-W",
+       .irq_enable = octeon_irq_ciu2_wd_enable,
+       .irq_disable = octeon_irq_ciu2_disable_all,
+       .irq_mask = octeon_irq_ciu2_disable_local,
+       .irq_unmask = octeon_irq_ciu2_enable_local,
+};
+
+static struct irq_chip octeon_irq_chip_ciu2_gpio = {
+       .name = "CIU-GPIO",
+       .irq_enable = octeon_irq_ciu2_enable_gpio,
+       .irq_disable = octeon_irq_ciu2_disable_gpio,
+       .irq_ack = octeon_irq_ciu_gpio_ack,
+       .irq_mask = octeon_irq_ciu2_disable_local,
+       .irq_unmask = octeon_irq_ciu2_enable,
+       .irq_set_type = octeon_irq_ciu_gpio_set_type,
+#ifdef CONFIG_SMP
+       .irq_set_affinity = octeon_irq_ciu2_set_affinity,
+       .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
+#endif
+       .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static int octeon_irq_ciu2_xlat(struct irq_domain *d,
+                               struct device_node *node,
+                               const u32 *intspec,
+                               unsigned int intsize,
+                               unsigned long *out_hwirq,
+                               unsigned int *out_type)
+{
+       unsigned int ciu, bit;
+
+       ciu = intspec[0];
+       bit = intspec[1];
+
+       /* Line 7  are the GPIO lines */
+       if (ciu > 6 || bit > 63)
+               return -EINVAL;
+
+       *out_hwirq = (ciu << 6) | bit;
+       *out_type = 0;
+
+       return 0;
+}
+
+static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
+{
+       bool edge = false;
+
+       if (line == 3) /* MIO */
+               switch (bit) {
+               case 2:  /* IPD_DRP */
+               case 8 ... 11: /* Timers */
+               case 48: /* PTP */
+                       edge = true;
+                       break;
+               default:
+                       break;
+               }
+       else if (line == 6) /* PKT */
+               switch (bit) {
+               case 52 ... 53: /* ILK_DRP */
+               case 8 ... 12:  /* GMX_DRP */
+                       edge = true;
+                       break;
+               default:
+                       break;
+               }
+       return edge;
+}
+
+static int octeon_irq_ciu2_map(struct irq_domain *d,
+                              unsigned int virq, irq_hw_number_t hw)
+{
+       unsigned int line = hw >> 6;
+       unsigned int bit = hw & 63;
+
+       if (!octeon_irq_virq_in_range(virq))
+               return -EINVAL;
+
+       /* Line 7  are the GPIO lines */
+       if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0)
+               return -EINVAL;
+
+       if (octeon_irq_ciu2_is_edge(line, bit))
+               octeon_irq_set_ciu_mapping(virq, line, bit, 0,
+                                          &octeon_irq_chip_ciu2,
+                                          handle_edge_irq);
+       else
+               octeon_irq_set_ciu_mapping(virq, line, bit, 0,
+                                          &octeon_irq_chip_ciu2,
+                                          handle_level_irq);
+
+       return 0;
+}
+static int octeon_irq_ciu2_gpio_map(struct irq_domain *d,
+                                   unsigned int virq, irq_hw_number_t hw)
+{
+       return octeon_irq_gpio_map_common(d, virq, hw, 7, &octeon_irq_chip_ciu2_gpio);
+}
+
+static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
+       .map = octeon_irq_ciu2_map,
+       .xlate = octeon_irq_ciu2_xlat,
+};
+
+static struct irq_domain_ops octeon_irq_domain_ciu2_gpio_ops = {
+       .map = octeon_irq_ciu2_gpio_map,
+       .xlate = octeon_irq_gpio_xlat,
+};
+
+static void octeon_irq_ciu2(void)
+{
+       int line;
+       int bit;
+       int irq;
+       u64 src_reg, src, sum;
+       const unsigned long core_id = cvmx_get_core_num();
+
+       sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(core_id)) & 0xfful;
+
+       if (unlikely(!sum))
+               goto spurious;
+
+       line = fls64(sum) - 1;
+       src_reg = CVMX_CIU2_SRC_PPX_IP2_WRKQ(core_id) + (0x1000 * line);
+       src = cvmx_read_csr(src_reg);
+
+       if (unlikely(!src))
+               goto spurious;
+
+       bit = fls64(src) - 1;
+       irq = octeon_irq_ciu_to_irq[line][bit];
+       if (unlikely(!irq))
+               goto spurious;
+
+       do_IRQ(irq);
+       goto out;
+
+spurious:
+       spurious_interrupt();
+out:
+       /* CN68XX pass 1.x has an errata that accessing the ACK registers
+               can stop interrupts from propagating */
+       if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+               cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
+       else
+               cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP2(core_id));
+       return;
+}
+
+static void octeon_irq_ciu2_mbox(void)
+{
+       int line;
+
+       const unsigned long core_id = cvmx_get_core_num();
+       u64 sum = cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP3(core_id)) >> 60;
+
+       if (unlikely(!sum))
+               goto spurious;
+
+       line = fls64(sum) - 1;
+
+       do_IRQ(OCTEON_IRQ_MBOX0 + line);
+       goto out;
+
+spurious:
+       spurious_interrupt();
+out:
+       /* CN68XX pass 1.x has an errata that accessing the ACK registers
+               can stop interrupts from propagating */
+       if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+               cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
+       else
+               cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP3(core_id));
+       return;
+}
+
+static void __init octeon_irq_init_ciu2(void)
+{
+       unsigned int i;
+       struct device_node *gpio_node;
+       struct device_node *ciu_node;
+       struct irq_domain *ciu_domain = NULL;
+
+       octeon_irq_init_ciu2_percpu();
+       octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu2;
+
+       octeon_irq_ip2 = octeon_irq_ciu2;
+       octeon_irq_ip3 = octeon_irq_ciu2_mbox;
+       octeon_irq_ip4 = octeon_irq_ip4_mask;
+
+       /* Mips internal */
+       octeon_irq_init_core();
+
+       gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
+       if (gpio_node) {
+               struct octeon_irq_gpio_domain_data *gpiod;
+
+               gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
+               if (gpiod) {
+                       /* gpio domain host_data is the base hwirq number. */
+                       gpiod->base_hwirq = 7 << 6;
+                       irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_ciu2_gpio_ops, gpiod);
+                       of_node_put(gpio_node);
+               } else
+                       pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
+       } else
+               pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
+
+       ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-6880-ciu2");
+       if (ciu_node) {
+               ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu2_ops, NULL);
+               irq_set_default_host(ciu_domain);
+               of_node_put(ciu_node);
+       } else
+               panic("Cannot find device node for cavium,octeon-6880-ciu2.");
+
+       /* CUI2 */
+       for (i = 0; i < 64; i++)
+               octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i);
+
+       for (i = 0; i < 32; i++)
+               octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i, 0,
+                                          &octeon_irq_chip_ciu2_wd, handle_level_irq);
+
+       for (i = 0; i < 4; i++)
+               octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 3, i + 8);
+
+       octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 3, 44);
+
+       for (i = 0; i < 4; i++)
+               octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 4, i);
+
+       for (i = 0; i < 4; i++)
+               octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 4, i + 8);
+
+       irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
+       irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
+       irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
+       irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
+
+       /* Enable the CIU lines */
+       set_c0_status(STATUSF_IP3 | STATUSF_IP2);
+       clear_c0_status(STATUSF_IP4);
+}
+
 void __init arch_init_irq(void)
 {
 #ifdef CONFIG_SMP
@@ -1233,7 +1746,10 @@ void __init arch_init_irq(void)
        cpumask_clear(irq_default_affinity);
        cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 #endif
-       octeon_irq_init_ciu();
+       if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+               octeon_irq_init_ciu2();
+       else
+               octeon_irq_init_ciu();
 }
 
 asmlinkage void plat_irq_dispatch(void)
index 919b0fb..04dd8ff 100644 (file)
@@ -548,6 +548,8 @@ void __init prom_init(void)
        }
 #endif
 
+       octeon_setup_delays();
+
        /*
         * BIST should always be enabled when doing a soft reset. L2
         * Cache locking for instance is not cleared unless BIST is
@@ -611,7 +613,6 @@ void __init prom_init(void)
        mips_hpt_frequency = octeon_get_clock_rate();
 
        octeon_init_cvmcount();
-       octeon_setup_delays();
 
        _machine_restart = octeon_restart;
        _machine_halt = octeon_halt;
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
deleted file mode 100644 (file)
index b5ad738..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_MIPS_SIM=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MIPS_SIM_NET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
-# CONFIG_CRC32 is not set
index 84624b1..5468b1c 100644 (file)
@@ -1,14 +1,12 @@
 CONFIG_NLM_XLP_BOARD=y
 CONFIG_64BIT=y
+CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_HW_PERF_EVENTS is not set
 CONFIG_KSM=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_SMP=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 # CONFIG_SECCOMP is not set
-CONFIG_USE_OF=y
 CONFIG_EXPERIMENTAL=y
-CONFIG_CROSS_COMPILE=""
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -19,13 +17,13 @@ CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_CGROUPS=y
 CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_BZIP2=y
 CONFIG_RD_LZMA=y
-CONFIG_INITRAMFS_COMPRESSION_LZMA=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_EMBEDDED=y
 # CONFIG_COMPAT_BRK is not set
@@ -35,6 +33,29 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_SGI_PARTITION=y
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=y
 CONFIG_MIPS32_COMPAT=y
@@ -169,7 +190,6 @@ CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
@@ -185,7 +205,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -196,7 +215,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
@@ -247,9 +265,6 @@ CONFIG_IPDDP_ENCAP=y
 CONFIG_IPDDP_DECAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
 CONFIG_WAN_ROUTER=m
 CONFIG_PHONET=m
 CONFIG_IEEE802154=m
@@ -296,11 +311,21 @@ CONFIG_NET_ACT_SIMP=m
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_DCB=y
 CONFIG_NET_PKTGEN=m
-# CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
@@ -309,7 +334,6 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
 CONFIG_CDROM_PKTCDVD=y
 CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=y
 CONFIG_SCSI_TGT=m
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
@@ -336,6 +360,48 @@ CONFIG_SCSI_DH_EMC=m
 CONFIG_SCSI_DH_ALUA=m
 CONFIG_SCSI_OSD_INITIATOR=m
 CONFIG_SCSI_OSD_ULD=m
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000E=y
+# CONFIG_NET_VENDOR_I825XX is not set
+CONFIG_SKY2=y
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
@@ -359,16 +425,23 @@ CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_TIMERIOMEM=m
 CONFIG_RAW_DRIVER=m
-# CONFIG_HWMON is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_OCORES=y
+CONFIG_SENSORS_LM90=y
+CONFIG_THERMAL=y
 # CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1374=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV=m
 CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -380,15 +453,10 @@ CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
 CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
 CONFIG_BTRFS_FS=m
 CONFIG_BTRFS_FS_POSIX_ACL=y
 CONFIG_NILFS2_FS=m
 CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=y
 CONFIG_CUSE=m
@@ -414,6 +482,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_BEFS_FS=m
 CONFIG_BFS_FS=m
 CONFIG_EFS_FS=m
+CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
 CONFIG_VXFS_FS=m
@@ -426,7 +495,6 @@ CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_EXOFS_FS=m
 CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_NFS_FSCACHE=y
@@ -449,25 +517,6 @@ CONFIG_NCPFS_NLS=y
 CONFIG_NCPFS_EXTRAS=y
 CONFIG_CODA_FS=m
 CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="cp437"
 CONFIG_NLS_CODEPAGE_437=m
@@ -517,12 +566,10 @@ CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_SCHED_TRACER=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_KGDB=y
 CONFIG_SECURITY=y
-CONFIG_SECURITY_NETWORK=y
 CONFIG_LSM_MMAP_MIN_ADDR=0
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SELINUX_BOOTPARAM=y
diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig
new file mode 100644 (file)
index 0000000..e3eec68
--- /dev/null
@@ -0,0 +1,124 @@
+CONFIG_MIPS_SEAD3=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HZ_100=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=32
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_SPI=y
+CONFIG_SENSORS_ADT7475=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_SPI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_XFS_FS=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_QUOTA=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
index ca400f7..63002a2 100644 (file)
@@ -95,8 +95,8 @@
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
-#ifndef kernel_uses_smartmips_rixi
-#define kernel_uses_smartmips_rixi 0
+#ifndef cpu_has_rixi
+#define cpu_has_rixi           (cpu_data[0].options & MIPS_CPU_RIXI)
 #endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache    (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
index f21b7c0..554e2d2 100644 (file)
@@ -94,6 +94,7 @@
 #define PRID_IMP_24KE          0x9600
 #define PRID_IMP_74K           0x9700
 #define PRID_IMP_1004K         0x9900
+#define PRID_IMP_1074K         0x9a00
 #define PRID_IMP_M14KC         0x9c00
 
 /*
@@ -319,6 +320,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_VINT          0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC          0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 #define MIPS_CPU_ULRI          0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_RIXI          0x00400000 /* CPU has TLB Read/eXec Inhibit */
 
 /*
  * CPU ASE encodings
index 991b659..37620db 100644 (file)
        REG32(_gic_base + segment##_##SECTION_OFS + offset)
 
 #define GIC_ABS_REG(segment, offset) \
-       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 #define GIC_REG_ABS_ADDR(segment, offset) \
-       (_gic_base + segment##_##SECTION_OFS + offset)
+       (_gic_base + segment##_##SECTION_OFS + offset)
 
 #ifdef GICISBYTELITTLEENDIAN
-#define GICREAD(reg, data)     (data) = (reg), (data) = le32_to_cpu(data)
-#define GICWRITE(reg, data)    (reg) = cpu_to_le32(data)
+#define GICREAD(reg, data)     ((data) = (reg), (data) = le32_to_cpu(data))
+#define GICWRITE(reg, data)    ((reg) = cpu_to_le32(data))
 #define GICBIS(reg, bits)                      \
        ({unsigned int data;                    \
                GICREAD(reg, data);             \
@@ -48,9 +48,9 @@
        })
 
 #else
-#define GICREAD(reg, data)     (data) = (reg)
-#define GICWRITE(reg, data)    (reg) = (data)
-#define GICBIS(reg, bits)      (reg) |= (bits)
+#define GICREAD(reg, data)     ((data) = (reg))
+#define GICWRITE(reg, data)    ((reg) = (data))
+#define GICBIS(reg, bits)      ((reg) |= (bits))
 #endif
 
 
                 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
 
 struct gic_pcpu_mask {
-       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
+       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
 };
 
 struct gic_pending_regs {
-       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
+       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
 };
 
 struct gic_intrmask_regs {
-       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
+       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
 };
 
 /*
@@ -341,15 +341,44 @@ struct gic_shared_intr_map {
        unsigned int local_intr_mask;
 };
 
+/* GIC nomenclature for Core Interrupt Pins. */
+#define GIC_CPU_INT0           0 /* Core Interrupt 2 */
+#define GIC_CPU_INT1           1 /* .                */
+#define GIC_CPU_INT2           2 /* .                */
+#define GIC_CPU_INT3           3 /* .                */
+#define GIC_CPU_INT4           4 /* .                */
+#define GIC_CPU_INT5           5 /* Core Interrupt 5 */
+
+/* Local GIC interrupts. */
+#define GIC_INT_TMR            (GIC_CPU_INT5)
+#define GIC_INT_PERFCTR                (GIC_CPU_INT5)
+
+/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
+#define GIC_CPU_TO_VEC_OFFSET  (2)
+
+/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
+#define GIC_PIN_TO_VEC_OFFSET  (1)
+
+extern unsigned long _gic_base;
+extern unsigned int gic_irq_base;
+extern unsigned int gic_irq_flags[];
+extern struct gic_shared_intr_map gic_shared_intr_map[];
+
 extern void gic_init(unsigned long gic_base_addr,
        unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
        unsigned int intrmap_size, unsigned int irqbase);
 
+extern void gic_clocksource_init(unsigned int);
 extern unsigned int gic_get_int(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
 extern void gic_bind_eic_interrupt(int irq, int set);
 extern unsigned int gic_get_timer_pending(void);
+extern void gic_enable_interrupt(int irq_vec);
+extern void gic_disable_interrupt(int irq_vec);
+extern void gic_irq_ack(struct irq_data *d);
+extern void gic_finish_irq(struct irq_data *d);
+extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
 
 #endif /* _ASM_GICREGS_H */
index dde5044..a5e0f17 100644 (file)
 
 #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
 #define AR934X_WMAC_SIZE       0x20000
+#define AR934X_EHCI_BASE       0x1b000000
+#define AR934X_EHCI_SIZE       0x200
+#define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE       0x1000
 
 /*
  * DDR_CTRL block
 #define AR933X_RESET_USB_PHY           BIT(4)
 #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 
+#define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
+#define AR934X_RESET_USB_HOST          BIT(5)
+#define AR934X_RESET_USB_PHY           BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
+
 #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
 
 #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
 #define AR933X_GPIO_COUNT              30
 #define AR934X_GPIO_COUNT              23
 
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG      0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG      0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG      0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG      0x240
+#define AR934X_SRIF_DDR_DPLL2_REG      0x244
+#define AR934X_SRIF_DDR_DPLL3_REG      0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK  0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT   18
+#define AR934X_SRIF_DPLL1_NINT_MASK    0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK   0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL    BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
+
 #endif /* __ASM_MACH_AR71XX_REGS_H */
index e104ddb..dbd5b5a 100644 (file)
@@ -120,6 +120,8 @@ enum bcm63xx_regs_set {
        RSET_OHCI0,
        RSET_OHCI_PRIV,
        RSET_USBH_PRIV,
+       RSET_USBD,
+       RSET_USBDMA,
        RSET_MPI,
        RSET_PCMCIA,
        RSET_PCIE,
@@ -162,6 +164,8 @@ enum bcm63xx_regs_set {
 #define RSET_UDC_SIZE                  256
 #define RSET_OHCI_SIZE                 256
 #define RSET_EHCI_SIZE                 256
+#define RSET_USBD_SIZE                 256
+#define RSET_USBDMA_SIZE               1280
 #define RSET_PCMCIA_SIZE               12
 #define RSET_M2M_SIZE                  256
 #define RSET_ATM_SIZE                  4096
@@ -183,10 +187,11 @@ enum bcm63xx_regs_set {
 #define BCM_6328_GPIO_BASE             (0xb0000080)
 #define BCM_6328_SPI_BASE              (0xdeadbeef)
 #define BCM_6328_UDC0_BASE             (0xdeadbeef)
-#define BCM_6328_USBDMA_BASE           (0xdeadbeef)
-#define BCM_6328_OHCI0_BASE            (0xdeadbeef)
+#define BCM_6328_USBDMA_BASE           (0xb000c000)
+#define BCM_6328_OHCI0_BASE            (0xb0002600)
 #define BCM_6328_OHCI_PRIV_BASE                (0xdeadbeef)
-#define BCM_6328_USBH_PRIV_BASE                (0xdeadbeef)
+#define BCM_6328_USBH_PRIV_BASE                (0xb0002700)
+#define BCM_6328_USBD_BASE             (0xb0002400)
 #define BCM_6328_MPI_BASE              (0xdeadbeef)
 #define BCM_6328_PCMCIA_BASE           (0xdeadbeef)
 #define BCM_6328_PCIE_BASE             (0xb0e40000)
@@ -199,7 +204,7 @@ enum bcm63xx_regs_set {
 #define BCM_6328_ENETDMAC_BASE         (0xb000da00)
 #define BCM_6328_ENETDMAS_BASE         (0xb000dc00)
 #define BCM_6328_ENETSW_BASE           (0xb0e00000)
-#define BCM_6328_EHCI0_BASE            (0x10002500)
+#define BCM_6328_EHCI0_BASE            (0xb0002500)
 #define BCM_6328_SDRAM_BASE            (0xdeadbeef)
 #define BCM_6328_MEMC_BASE             (0xdeadbeef)
 #define BCM_6328_DDR_BASE              (0xb0003000)
@@ -232,6 +237,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_OHCI0_BASE            (0xdeadbeef)
 #define BCM_6338_OHCI_PRIV_BASE                (0xfffe3000)
 #define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)
+#define BCM_6338_USBD_BASE             (0xdeadbeef)
 #define BCM_6338_MPI_BASE              (0xfffe3160)
 #define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
 #define BCM_6338_PCIE_BASE             (0xdeadbeef)
@@ -286,6 +292,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_OHCI0_BASE            (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE                (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE                (0xdeadbeef)
+#define BCM_6345_USBD_BASE             (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE       (0xfffe2300)
 #define BCM_6345_DSL_BASE              (0xdeadbeef)
 #define BCM_6345_UBUS_BASE             (0xdeadbeef)
@@ -319,9 +326,11 @@ enum bcm63xx_regs_set {
 #define BCM_6348_GPIO_BASE             (0xfffe0400)
 #define BCM_6348_SPI_BASE              (0xfffe0c00)
 #define BCM_6348_UDC0_BASE             (0xfffe1000)
+#define BCM_6348_USBDMA_BASE           (0xdeadbeef)
 #define BCM_6348_OHCI0_BASE            (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE                (0xfffe1c00)
 #define BCM_6348_USBH_PRIV_BASE                (0xdeadbeef)
+#define BCM_6348_USBD_BASE             (0xdeadbeef)
 #define BCM_6348_MPI_BASE              (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE           (0xfffe2054)
 #define BCM_6348_PCIE_BASE             (0xdeadbeef)
@@ -362,9 +371,11 @@ enum bcm63xx_regs_set {
 #define BCM_6358_GPIO_BASE             (0xfffe0080)
 #define BCM_6358_SPI_BASE              (0xfffe0800)
 #define BCM_6358_UDC0_BASE             (0xfffe0800)
+#define BCM_6358_USBDMA_BASE           (0xdeadbeef)
 #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
+#define BCM_6358_USBD_BASE             (0xdeadbeef)
 #define BCM_6358_MPI_BASE              (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE           (0xfffe1054)
 #define BCM_6358_PCIE_BASE             (0xdeadbeef)
@@ -406,9 +417,11 @@ enum bcm63xx_regs_set {
 #define BCM_6368_GPIO_BASE             (0xb0000080)
 #define BCM_6368_SPI_BASE              (0xb0000800)
 #define BCM_6368_UDC0_BASE             (0xdeadbeef)
+#define BCM_6368_USBDMA_BASE           (0xb0004800)
 #define BCM_6368_OHCI0_BASE            (0xb0001600)
 #define BCM_6368_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6368_USBH_PRIV_BASE                (0xb0001700)
+#define BCM_6368_USBD_BASE             (0xb0001400)
 #define BCM_6368_MPI_BASE              (0xb0001000)
 #define BCM_6368_PCMCIA_BASE           (0xb0001054)
 #define BCM_6368_PCIE_BASE             (0xdeadbeef)
@@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base;
        __GEN_RSET_BASE(__cpu, OHCI0)                                   \
        __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
        __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
+       __GEN_RSET_BASE(__cpu, USBD)                                    \
+       __GEN_RSET_BASE(__cpu, USBDMA)                                  \
        __GEN_RSET_BASE(__cpu, MPI)                                     \
        __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
        __GEN_RSET_BASE(__cpu, PCIE)                                    \
@@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base;
        [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
        [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
        [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
+       [RSET_USBD]             = BCM_## __cpu ##_USBD_BASE,            \
+       [RSET_USBDMA]           = BCM_## __cpu ##_USBDMA_BASE,          \
        [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
        [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
        [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
@@ -569,6 +586,13 @@ enum bcm63xx_irq {
        IRQ_ENET_PHY,
        IRQ_OHCI0,
        IRQ_EHCI0,
+       IRQ_USBD,
+       IRQ_USBD_RXDMA0,
+       IRQ_USBD_TXDMA0,
+       IRQ_USBD_RXDMA1,
+       IRQ_USBD_TXDMA1,
+       IRQ_USBD_RXDMA2,
+       IRQ_USBD_TXDMA2,
        IRQ_ENET0_RXDMA,
        IRQ_ENET0_TXDMA,
        IRQ_ENET1_RXDMA,
@@ -602,8 +626,15 @@ enum bcm63xx_irq {
 #define BCM_6328_ENET0_IRQ             0
 #define BCM_6328_ENET1_IRQ             0
 #define BCM_6328_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 12)
-#define BCM_6328_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 9)
-#define BCM_6328_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 10)
+#define BCM_6328_OHCI0_IRQ             (BCM_6328_HIGH_IRQ_BASE + 9)
+#define BCM_6328_EHCI0_IRQ             (BCM_6328_HIGH_IRQ_BASE + 10)
+#define BCM_6328_USBD_IRQ              (IRQ_INTERNAL_BASE + 4)
+#define BCM_6328_USBD_RXDMA0_IRQ       (IRQ_INTERNAL_BASE + 5)
+#define BCM_6328_USBD_TXDMA0_IRQ       (IRQ_INTERNAL_BASE + 6)
+#define BCM_6328_USBD_RXDMA1_IRQ       (IRQ_INTERNAL_BASE + 7)
+#define BCM_6328_USBD_TXDMA1_IRQ       (IRQ_INTERNAL_BASE + 8)
+#define BCM_6328_USBD_RXDMA2_IRQ       (IRQ_INTERNAL_BASE + 9)
+#define BCM_6328_USBD_TXDMA2_IRQ       (IRQ_INTERNAL_BASE + 10)
 #define BCM_6328_PCMCIA_IRQ            0
 #define BCM_6328_ENET0_RXDMA_IRQ       0
 #define BCM_6328_ENET0_TXDMA_IRQ       0
@@ -615,10 +646,10 @@ enum bcm63xx_irq {
 #define BCM_6328_ENETSW_RXDMA1_IRQ     (BCM_6328_HIGH_IRQ_BASE + 1)
 #define BCM_6328_ENETSW_RXDMA2_IRQ     (BCM_6328_HIGH_IRQ_BASE + 2)
 #define BCM_6328_ENETSW_RXDMA3_IRQ     (BCM_6328_HIGH_IRQ_BASE + 3)
-#define BCM_6328_ENETSW_TXDMA0_IRQ     (BCM_6328_HIGH_IRQ_BASE + 4)
-#define BCM_6328_ENETSW_TXDMA1_IRQ     (BCM_6328_HIGH_IRQ_BASE + 5)
-#define BCM_6328_ENETSW_TXDMA2_IRQ     (BCM_6328_HIGH_IRQ_BASE + 6)
-#define BCM_6328_ENETSW_TXDMA3_IRQ     (BCM_6328_HIGH_IRQ_BASE + 7)
+#define BCM_6328_ENETSW_TXDMA0_IRQ     0
+#define BCM_6328_ENETSW_TXDMA1_IRQ     0
+#define BCM_6328_ENETSW_TXDMA2_IRQ     0
+#define BCM_6328_ENETSW_TXDMA3_IRQ     0
 #define BCM_6328_XTM_IRQ               (BCM_6328_HIGH_IRQ_BASE + 31)
 #define BCM_6328_XTM_DMA0_IRQ          (BCM_6328_HIGH_IRQ_BASE + 11)
 
@@ -642,6 +673,13 @@ enum bcm63xx_irq {
 #define BCM_6338_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 #define BCM_6338_OHCI0_IRQ             0
 #define BCM_6338_EHCI0_IRQ             0
+#define BCM_6338_USBD_IRQ              0
+#define BCM_6338_USBD_RXDMA0_IRQ       0
+#define BCM_6338_USBD_TXDMA0_IRQ       0
+#define BCM_6338_USBD_RXDMA1_IRQ       0
+#define BCM_6338_USBD_TXDMA1_IRQ       0
+#define BCM_6338_USBD_RXDMA2_IRQ       0
+#define BCM_6338_USBD_TXDMA2_IRQ       0
 #define BCM_6338_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
 #define BCM_6338_ENET1_RXDMA_IRQ       0
@@ -673,6 +711,13 @@ enum bcm63xx_irq {
 #define BCM_6345_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 12)
 #define BCM_6345_OHCI0_IRQ             0
 #define BCM_6345_EHCI0_IRQ             0
+#define BCM_6345_USBD_IRQ              0
+#define BCM_6345_USBD_RXDMA0_IRQ       0
+#define BCM_6345_USBD_TXDMA0_IRQ       0
+#define BCM_6345_USBD_RXDMA1_IRQ       0
+#define BCM_6345_USBD_TXDMA1_IRQ       0
+#define BCM_6345_USBD_RXDMA2_IRQ       0
+#define BCM_6345_USBD_TXDMA2_IRQ       0
 #define BCM_6345_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 13 + 2)
 #define BCM_6345_ENET1_RXDMA_IRQ       0
@@ -704,6 +749,13 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 12)
 #define BCM_6348_EHCI0_IRQ             0
+#define BCM_6348_USBD_IRQ              0
+#define BCM_6348_USBD_RXDMA0_IRQ       0
+#define BCM_6348_USBD_TXDMA0_IRQ       0
+#define BCM_6348_USBD_RXDMA1_IRQ       0
+#define BCM_6348_USBD_TXDMA1_IRQ       0
+#define BCM_6348_USBD_RXDMA2_IRQ       0
+#define BCM_6348_USBD_TXDMA2_IRQ       0
 #define BCM_6348_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 22)
@@ -735,6 +787,13 @@ enum bcm63xx_irq {
 #define BCM_6358_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
 #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 10)
+#define BCM_6358_USBD_IRQ              0
+#define BCM_6358_USBD_RXDMA0_IRQ       0
+#define BCM_6358_USBD_TXDMA0_IRQ       0
+#define BCM_6358_USBD_RXDMA1_IRQ       0
+#define BCM_6358_USBD_TXDMA1_IRQ       0
+#define BCM_6358_USBD_RXDMA2_IRQ       0
+#define BCM_6358_USBD_TXDMA2_IRQ       0
 #define BCM_6358_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 17)
@@ -775,6 +834,13 @@ enum bcm63xx_irq {
 #define BCM_6368_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 15)
 #define BCM_6368_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 #define BCM_6368_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_USBD_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6368_USBD_RXDMA0_IRQ       (IRQ_INTERNAL_BASE + 26)
+#define BCM_6368_USBD_TXDMA0_IRQ       (IRQ_INTERNAL_BASE + 27)
+#define BCM_6368_USBD_RXDMA1_IRQ       (IRQ_INTERNAL_BASE + 28)
+#define BCM_6368_USBD_TXDMA1_IRQ       (IRQ_INTERNAL_BASE + 29)
+#define BCM_6368_USBD_RXDMA2_IRQ       (IRQ_INTERNAL_BASE + 30)
+#define BCM_6368_USBD_TXDMA2_IRQ       (IRQ_INTERNAL_BASE + 31)
 #define BCM_6368_PCMCIA_IRQ            0
 #define BCM_6368_ENET0_RXDMA_IRQ       0
 #define BCM_6368_ENET0_TXDMA_IRQ       0
@@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs;
        [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
        [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
        [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+       [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
+       [IRQ_USBD_RXDMA0]       = BCM_## __cpu ##_USBD_RXDMA0_IRQ,      \
+       [IRQ_USBD_TXDMA0]       = BCM_## __cpu ##_USBD_TXDMA0_IRQ,      \
+       [IRQ_USBD_RXDMA1]       = BCM_## __cpu ##_USBD_RXDMA1_IRQ,      \
+       [IRQ_USBD_TXDMA1]       = BCM_## __cpu ##_USBD_TXDMA1_IRQ,      \
+       [IRQ_USBD_RXDMA2]       = BCM_## __cpu ##_USBD_RXDMA2_IRQ,      \
+       [IRQ_USBD_TXDMA2]       = BCM_## __cpu ##_USBD_TXDMA2_IRQ,      \
        [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
        [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
        [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
new file mode 100644 (file)
index 0000000..5d6d698
--- /dev/null
@@ -0,0 +1,17 @@
+#ifndef BCM63XX_DEV_USB_USBD_H_
+#define BCM63XX_DEV_USB_USBD_H_
+
+/*
+ * usb device platform data
+ */
+struct bcm63xx_usbd_platform_data {
+       /* board can only support full speed (USB 1.1) */
+       int use_fullspeed;
+
+       /* 0-based port index, for chips with >1 USB PHY */
+       int port_no;
+};
+
+int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd);
+
+#endif /* BCM63XX_DEV_USB_USBD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
new file mode 100644 (file)
index 0000000..a5bbff3
--- /dev/null
@@ -0,0 +1,38 @@
+#ifndef BCM63XX_IUDMA_H_
+#define BCM63XX_IUDMA_H_
+
+#include <linux/types.h>
+
+/*
+ * rx/tx dma descriptor
+ */
+struct bcm_enet_desc {
+       u32 len_stat;
+       u32 address;
+};
+
+/* control */
+#define DMADESC_LENGTH_SHIFT   16
+#define DMADESC_LENGTH_MASK    (0xfff << DMADESC_LENGTH_SHIFT)
+#define DMADESC_OWNER_MASK     (1 << 15)
+#define DMADESC_EOP_MASK       (1 << 14)
+#define DMADESC_SOP_MASK       (1 << 13)
+#define DMADESC_ESOP_MASK      (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
+#define DMADESC_WRAP_MASK      (1 << 12)
+#define DMADESC_USB_NOZERO_MASK        (1 << 1)
+#define DMADESC_USB_ZERO_MASK  (1 << 0)
+
+/* status */
+#define DMADESC_UNDER_MASK     (1 << 9)
+#define DMADESC_APPEND_CRC     (1 << 8)
+#define DMADESC_OVSIZE_MASK    (1 << 4)
+#define DMADESC_RXER_MASK      (1 << 2)
+#define DMADESC_CRC_MASK       (1 << 1)
+#define DMADESC_OV_MASK                (1 << 0)
+#define DMADESC_ERR_MASK       (DMADESC_UNDER_MASK | \
+                               DMADESC_OVSIZE_MASK | \
+                               DMADESC_RXER_MASK | \
+                               DMADESC_CRC_MASK | \
+                               DMADESC_OV_MASK)
+
+#endif /* ! BCM63XX_IUDMA_H_ */
index 61f2a2a..12963d0 100644 (file)
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG_6328       0x18
 #define PERF_EXTIRQ_CFG_REG_6338       0x14
+#define PERF_EXTIRQ_CFG_REG_6345       0x14
 #define PERF_EXTIRQ_CFG_REG_6348       0x14
 #define PERF_EXTIRQ_CFG_REG_6358       0x14
 #define PERF_EXTIRQ_CFG_REG_6368       0x18
 #define GPIO_MODE_6368_SPI_SSN5                (1 << 31)
 
 
+#define GPIO_PINMUX_OTHR_REG           0x24
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT        12
+#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+#define GPIO_PINMUX_OTHR_6328_USB_DEV  (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
+
 #define GPIO_BASEMODE_6368_REG         0x38
 #define GPIO_BASEMODE_6368_UART2       0x1
 #define GPIO_BASEMODE_6368_GPIO                0x0
 #define ENETDMA_BUFALLOC_FORCE_SHIFT   31
 #define ENETDMA_BUFALLOC_FORCE_MASK    (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
 
+/* Global interrupt status */
+#define ENETDMA_GLB_IRQSTAT_REG                (0x40)
+
+/* Global interrupt mask */
+#define ENETDMA_GLB_IRQMASK_REG                (0x44)
+
 /* Channel Configuration register */
 #define ENETDMA_CHANCFG_REG(x)         (0x100 + (x) * 0x10)
 #define ENETDMA_CHANCFG_EN_SHIFT       0
 /* Channel Configuration register */
 #define ENETDMAC_CHANCFG_REG(x)                ((x) * 0x10)
 #define ENETDMAC_CHANCFG_EN_SHIFT      0
-#define ENETDMAC_CHANCFG_EN_MASK       (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_EN_MASK       (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
-#define ENETDMAC_CHANCFG_PKTHALT_MASK  (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_MASK  (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
+#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
+#define ENETDMAC_CHANCFG_BUFHALT_MASK  (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 
 /* Interrupt Control/Status register */
 #define ENETDMAC_IR_REG(x)             (0x4 + (x) * 0x10)
 #define USBH_PRIV_SWAP_6358_REG                0x0
 #define USBH_PRIV_SWAP_6368_REG                0x1c
 
+#define USBH_PRIV_SWAP_USBD_SHIFT      6
+#define USBH_PRIV_SWAP_USBD_MASK       (1 << USBH_PRIV_SWAP_USBD_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK  (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK  (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
+#define USBH_PRIV_UTMI_CTL_6368_REG    0x10
+#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT        12
+#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
+#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
+#define USBH_PRIV_UTMI_CTL_HOSTB_MASK  (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
+
 #define USBH_PRIV_TEST_6358_REG                0x24
 #define USBH_PRIV_TEST_6368_REG                0x14
 
 #define USBH_PRIV_SETUP_IOC_MASK       (1 << USBH_PRIV_SETUP_IOC_SHIFT)
 
 
+/*************************************************************************
+ * _REG relative to RSET_USBD
+ *************************************************************************/
+
+/* General control */
+#define USBD_CONTROL_REG               0x00
+#define USBD_CONTROL_TXZLENINS_SHIFT   14
+#define USBD_CONTROL_TXZLENINS_MASK    (1 << USBD_CONTROL_TXZLENINS_SHIFT)
+#define USBD_CONTROL_AUTO_CSRS_SHIFT   13
+#define USBD_CONTROL_AUTO_CSRS_MASK    (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
+#define USBD_CONTROL_RXZSCFG_SHIFT     12
+#define USBD_CONTROL_RXZSCFG_MASK      (1 << USBD_CONTROL_RXZSCFG_SHIFT)
+#define USBD_CONTROL_INIT_SEL_SHIFT    8
+#define USBD_CONTROL_INIT_SEL_MASK     (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
+#define USBD_CONTROL_FIFO_RESET_SHIFT  6
+#define USBD_CONTROL_FIFO_RESET_MASK   (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
+#define USBD_CONTROL_SETUPERRLOCK_SHIFT        5
+#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
+#define USBD_CONTROL_DONE_CSRS_SHIFT   0
+#define USBD_CONTROL_DONE_CSRS_MASK    (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
+
+/* Strap options */
+#define USBD_STRAPS_REG                        0x04
+#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
+#define USBD_STRAPS_APP_SELF_PWR_MASK  (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
+#define USBD_STRAPS_APP_DISCON_SHIFT   9
+#define USBD_STRAPS_APP_DISCON_MASK    (1 << USBD_STRAPS_APP_DISCON_SHIFT)
+#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT        8
+#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
+#define USBD_STRAPS_APP_RMTWKUP_SHIFT  6
+#define USBD_STRAPS_APP_RMTWKUP_MASK   (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
+#define USBD_STRAPS_APP_RAM_IF_SHIFT   7
+#define USBD_STRAPS_APP_RAM_IF_MASK    (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
+#define USBD_STRAPS_APP_8BITPHY_SHIFT  2
+#define USBD_STRAPS_APP_8BITPHY_MASK   (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
+#define USBD_STRAPS_SPEED_SHIFT                0
+#define USBD_STRAPS_SPEED_MASK         (3 << USBD_STRAPS_SPEED_SHIFT)
+
+/* Stall control */
+#define USBD_STALL_REG                 0x08
+#define USBD_STALL_UPDATE_SHIFT                7
+#define USBD_STALL_UPDATE_MASK         (1 << USBD_STALL_UPDATE_SHIFT)
+#define USBD_STALL_ENABLE_SHIFT                6
+#define USBD_STALL_ENABLE_MASK         (1 << USBD_STALL_ENABLE_SHIFT)
+#define USBD_STALL_EPNUM_SHIFT         0
+#define USBD_STALL_EPNUM_MASK          (0xf << USBD_STALL_EPNUM_SHIFT)
+
+/* General status */
+#define USBD_STATUS_REG                        0x0c
+#define USBD_STATUS_SOF_SHIFT          16
+#define USBD_STATUS_SOF_MASK           (0x7ff << USBD_STATUS_SOF_SHIFT)
+#define USBD_STATUS_SPD_SHIFT          12
+#define USBD_STATUS_SPD_MASK           (3 << USBD_STATUS_SPD_SHIFT)
+#define USBD_STATUS_ALTINTF_SHIFT      8
+#define USBD_STATUS_ALTINTF_MASK       (0xf << USBD_STATUS_ALTINTF_SHIFT)
+#define USBD_STATUS_INTF_SHIFT         4
+#define USBD_STATUS_INTF_MASK          (0xf << USBD_STATUS_INTF_SHIFT)
+#define USBD_STATUS_CFG_SHIFT          0
+#define USBD_STATUS_CFG_MASK           (0xf << USBD_STATUS_CFG_SHIFT)
+
+/* Other events */
+#define USBD_EVENTS_REG                        0x10
+#define USBD_EVENTS_USB_LINK_SHIFT     10
+#define USBD_EVENTS_USB_LINK_MASK      (1 << USBD_EVENTS_USB_LINK_SHIFT)
+
+/* IRQ status */
+#define USBD_EVENT_IRQ_STATUS_REG      0x14
+
+/* IRQ level (2 bits per IRQ event) */
+#define USBD_EVENT_IRQ_CFG_HI_REG      0x18
+
+#define USBD_EVENT_IRQ_CFG_LO_REG      0x1c
+
+#define USBD_EVENT_IRQ_CFG_SHIFT(x)    ((x & 0xf) << 1)
+#define USBD_EVENT_IRQ_CFG_MASK(x)     (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_RISING(x)   (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+#define USBD_EVENT_IRQ_CFG_FALLING(x)  (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
+
+/* IRQ mask (1=unmasked) */
+#define USBD_EVENT_IRQ_MASK_REG                0x20
+
+/* IRQ bits */
+#define USBD_EVENT_IRQ_USB_LINK                10
+#define USBD_EVENT_IRQ_SETCFG          9
+#define USBD_EVENT_IRQ_SETINTF         8
+#define USBD_EVENT_IRQ_ERRATIC_ERR     7
+#define USBD_EVENT_IRQ_SET_CSRS                6
+#define USBD_EVENT_IRQ_SUSPEND         5
+#define USBD_EVENT_IRQ_EARLY_SUSPEND   4
+#define USBD_EVENT_IRQ_SOF             3
+#define USBD_EVENT_IRQ_ENUM_ON         2
+#define USBD_EVENT_IRQ_SETUP           1
+#define USBD_EVENT_IRQ_USB_RESET       0
+
+/* TX FIFO partitioning */
+#define USBD_TXFIFO_CONFIG_REG         0x40
+#define USBD_TXFIFO_CONFIG_END_SHIFT   16
+#define USBD_TXFIFO_CONFIG_END_MASK    (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_TXFIFO_CONFIG_START_SHIFT 0
+#define USBD_TXFIFO_CONFIG_START_MASK  (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* RX FIFO partitioning */
+#define USBD_RXFIFO_CONFIG_REG         0x44
+#define USBD_RXFIFO_CONFIG_END_SHIFT   16
+#define USBD_RXFIFO_CONFIG_END_MASK    (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
+#define USBD_RXFIFO_CONFIG_START_SHIFT 0
+#define USBD_RXFIFO_CONFIG_START_MASK  (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
+
+/* TX FIFO/endpoint configuration */
+#define USBD_TXFIFO_EPSIZE_REG         0x48
+
+/* RX FIFO/endpoint configuration */
+#define USBD_RXFIFO_EPSIZE_REG         0x4c
+
+/* Endpoint<->DMA mappings */
+#define USBD_EPNUM_TYPEMAP_REG         0x50
+#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT  8
+#define USBD_EPNUM_TYPEMAP_TYPE_MASK   (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
+#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT        0
+#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
+
+/* Misc per-endpoint settings */
+#define USBD_CSR_SETUPADDR_REG         0x80
+#define USBD_CSR_SETUPADDR_DEF         0xb550
+
+#define USBD_CSR_EP_REG(x)             (0x84 + (x) * 4)
+#define USBD_CSR_EP_MAXPKT_SHIFT       19
+#define USBD_CSR_EP_MAXPKT_MASK                (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
+#define USBD_CSR_EP_ALTIFACE_SHIFT     15
+#define USBD_CSR_EP_ALTIFACE_MASK      (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
+#define USBD_CSR_EP_IFACE_SHIFT                11
+#define USBD_CSR_EP_IFACE_MASK         (0xf << USBD_CSR_EP_IFACE_SHIFT)
+#define USBD_CSR_EP_CFG_SHIFT          7
+#define USBD_CSR_EP_CFG_MASK           (0xf << USBD_CSR_EP_CFG_SHIFT)
+#define USBD_CSR_EP_TYPE_SHIFT         5
+#define USBD_CSR_EP_TYPE_MASK          (3 << USBD_CSR_EP_TYPE_SHIFT)
+#define USBD_CSR_EP_DIR_SHIFT          4
+#define USBD_CSR_EP_DIR_MASK           (1 << USBD_CSR_EP_DIR_SHIFT)
+#define USBD_CSR_EP_LOG_SHIFT          0
+#define USBD_CSR_EP_LOG_MASK           (0xf << USBD_CSR_EP_LOG_SHIFT)
+
 
 /*************************************************************************
  * _REG relative to RSET_MPI
index 474daaa..b0dd4bb 100644 (file)
@@ -5,6 +5,7 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <bcm63xx_dev_enet.h>
+#include <bcm63xx_dev_usb_usbd.h>
 #include <bcm63xx_dev_dsp.h>
 
 /*
@@ -44,6 +45,7 @@ struct board_info {
        unsigned int    has_pccard:1;
        unsigned int    has_ohci0:1;
        unsigned int    has_ehci0:1;
+       unsigned int    has_usbd:1;
        unsigned int    has_dsp:1;
        unsigned int    has_uart0:1;
        unsigned int    has_uart1:1;
@@ -52,6 +54,9 @@ struct board_info {
        struct bcm63xx_enet_platform_data enet0;
        struct bcm63xx_enet_platform_data enet1;
 
+       /* USB config */
+       struct bcm63xx_usbd_platform_data usbd;
+
        /* DSP config */
        struct bcm63xx_dsp_platform_data dsp;
 
index a58addb..375ad0c 100644 (file)
@@ -58,7 +58,7 @@
 #define cpu_has_veic           0
 #define cpu_hwrena_impl_bits   0xc0000000
 
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
+#define cpu_has_rixi           (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
 
 #define ARCH_HAS_IRQ_PER_CPU   1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
index c22a307..ff0d490 100644 (file)
@@ -21,10 +21,11 @@ enum octeon_irq {
        OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
        OCTEON_IRQ_WORKQ0,
-       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
-       OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
-       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
+       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
+       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
        OCTEON_IRQ_MBOX1,
+       OCTEON_IRQ_MBOX2,
+       OCTEON_IRQ_MBOX3,
        OCTEON_IRQ_PCI_INT0,
        OCTEON_IRQ_PCI_INT1,
        OCTEON_IRQ_PCI_INT2,
index 318f982..c6b63a4 100644 (file)
@@ -20,4 +20,6 @@
 
 #define MIPS_CPU_TIMER_IRQ                     7
 
+#define MAX_IM                 5
+
 #endif /* _FALCON_IRQ__ */
index b385252..fccac35 100644 (file)
@@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase;
 #define ltq_sys1_w32_mask(clear, set, reg)   \
        ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
 
+/* allow the gpio and pinctrl drivers to talk to eachother */
+extern int pinctrl_falcon_get_range_size(int id);
+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
+
 /*
  * to keep the irq code generic we need to define this to 0 as falcon
  * has no EIU/EBU
index f79505b..9ba1cae 100644 (file)
@@ -1,10 +1,7 @@
 #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
 #define __ASM_MIPS_MACH_LANTIQ_GPIO_H
 
-static inline int gpio_to_irq(unsigned int gpio)
-{
-       return -1;
-}
+#define gpio_to_irq __gpio_to_irq
 
 #define gpio_get_value __gpio_get_value
 #define gpio_set_value __gpio_set_value
index aa0b3b8..5eadfe5 100644 (file)
@@ -21,4 +21,6 @@
 
 #define MIPS_CPU_TIMER_IRQ     7
 
+#define MAX_IM                 5
+
 #endif
@@ -4,9 +4,10 @@
  * for more details.
  *
  * Copyright (C) 2003, 2004 Chris Dearman
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  */
-#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
 
 
 /*
@@ -16,7 +17,7 @@
 #define cpu_has_tlb            1
 #define cpu_has_4kex           1
 #define cpu_has_4k_cache       1
-#define cpu_has_fpu            0
+/* #define cpu_has_fpu         ? */
 /* #define cpu_has_32fpr       ? */
 #define cpu_has_counter                1
 /* #define cpu_has_watch       ? */
 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */
+#ifdef CONFIG_CPU_HAS_LLSC
 #define cpu_has_llsc           1
+#else
+#define cpu_has_llsc           0
+#endif
 /* #define cpu_has_vtag_icache ? */
 /* #define cpu_has_dc_aliases  ? */
 /* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_clo_clz                1
 #define cpu_has_nofpuex                0
 /* #define cpu_has_64bits      ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 
 #ifdef CONFIG_CPU_MIPS64
 /* #define cpu_has_vtag_icache ? */
 /* #define cpu_has_dc_aliases  ? */
 /* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_clo_clz                1
 #define cpu_has_nofpuex                0
 /* #define cpu_has_64bits      ? */
 /* #define cpu_has_64bit_zero_reg ? */
 /* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
 #endif
 
 #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
new file mode 100644 (file)
index 0000000..652ea4c
--- /dev/null
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
+#define NR_IRQS        256
+
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
new file mode 100644 (file)
index 0000000..3dfbd8e
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+
+       .macro  kernel_entry_setup
+#ifdef CONFIG_MIPS_MT_SMTC
+       mfc0    t0, CP0_CONFIG
+       bgez    t0, 9f
+       mfc0    t0, CP0_CONFIG, 1
+       bgez    t0, 9f
+       mfc0    t0, CP0_CONFIG, 2
+       bgez    t0, 9f
+       mfc0    t0, CP0_CONFIG, 3
+       and     t0, 1<<2
+       bnez    t0, 0f
+9 :
+       /* Assume we came from YAMON... */
+       PTR_LA  v0, 0x9fc00534  /* YAMON print */
+       lw      v0, (v0)
+       move    a0, zero
+       PTR_LA  a1, nonmt_processor
+       jal     v0
+
+       PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+       lw      v0, (v0)
+       li      a0, 1
+       jal     v0
+
+1 :    b       1b
+
+       __INITDATA
+nonmt_processor :
+       .asciz  "SMTC kernel requires the MT ASE to run\n"
+       __FINIT
+0 :
+#endif
+       .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+       .macro  smp_slave_setup
+       .endm
+
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
similarity index 72%
rename from arch/mips/include/asm/mach-mipssim/war.h
rename to arch/mips/include/asm/mach-sead3/war.h
index c8a74a3..7c6931d 100644 (file)
@@ -5,8 +5,8 @@
  *
  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
  */
-#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
-#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
 
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
+#define MIPS4K_ICACHE_REFILL_WAR       1
+#define MIPS_CACHE_SYNC_WAR            1
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define RM9000_CDEX_SMP_WAR            0
-#define ICACHE_REFILLS_WORKAROUND_WAR  0
+#define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
-#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
index 5447d9f..6692448 100644 (file)
@@ -1,31 +1,16 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines for the Malta interrupt controller.
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
+ * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
+ *      Carsten Langgaard <carstenl@mips.com>
+ *      Steven J. Hill <sjhill@mips.com>
  */
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-#include <irq.h>
+#define MIPS_GIC_IRQ_BASE      (MIPS_CPU_IRQ_BASE + 8)
 
 /*
  * Interrupts 0..15 are used for Malta ISA compatible interrupts
 #define MSC01E_INT_PERFCTR     10
 #define MSC01E_INT_CPUCTR      11
 
-/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
-#define GIC_CPU_INT0           0 /* Core Interrupt 2   */
-#define GIC_CPU_INT1           1 /* .                  */
-#define GIC_CPU_INT2           2 /* .                  */
-#define GIC_CPU_INT3           3 /* .                  */
-#define GIC_CPU_INT4           4 /* .                  */
-#define GIC_CPU_INT5           5 /* Core Interrupt 5   */
-
-/* MALTA GIC local interrupts */
-#define GIC_INT_TMR             (GIC_CPU_INT5)
-#define GIC_INT_PERFCTR         (GIC_CPU_INT5)
-
-/* GIC constants */
-/* Add 2 to convert non-eic hw int # to eic vector # */
-#define GIC_CPU_TO_VEC_OFFSET   (2)
-/* If we map an intr to pin X, GIC will actually generate vector X+1 */
-#define GIC_PIN_TO_VEC_OFFSET   (1)
-
-#define GIC_EXT_INTR(x)                x
-
 /* External Interrupts used for IPI */
 #define GIC_IPI_EXT_INTR_RESCHED_VPE0  16
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0  17
 #define GIC_IPI_EXT_INTR_RESCHED_VPE3  22
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3  23
 
-#define MIPS_GIC_IRQ_BASE      (MIPS_CPU_IRQ_BASE + 8)
-
-#ifndef __ASSEMBLY__
-extern void maltaint_init(void);
-#endif
-
 #endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
new file mode 100644 (file)
index 0000000..d634d9a
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
+ *      Douglas Leung <douglas@mips.com>
+ *      Steven J. Hill <sjhill@mips.com>
+ */
+#ifndef _MIPS_SEAD3INT_H
+#define _MIPS_SEAD3INT_H
+
+/* SEAD-3 GIC address space definitions. */
+#define GIC_BASE_ADDR          0x1b1c0000
+#define GIC_ADDRSPACE_SZ       (128 * 1024)
+
+#define MIPS_GIC_IRQ_BASE      (MIPS_CPU_IRQ_BASE + 0)
+
+#endif /* !(_MIPS_SEAD3INT_H) */
diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h
deleted file mode 100644 (file)
index 8ef6db7..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef _MIPS_SIMINT_H
-#define _MIPS_SIMINT_H
-
-#include <irq.h>
-
-#define SIM_INT_BASE           0
-#define MIPSCPU_INT_MB0                2
-#define MIPS_CPU_TIMER_IRQ     7
-
-
-#define MSC01E_INT_BASE                64
-
-#define MSC01E_INT_CPUCTR      11
-
-#endif
index 7f87d82..528fda1 100644 (file)
 #define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
+#define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
 
 #define MIPS_CONF4_MMUSIZEEXT  (_ULCAST_(255) << 0)
 #define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 
+#define MIPS_CONF6_SYND                (_ULCAST_(1) << 13)
+
 #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
index 30d68f2..542ee09 100644 (file)
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
 union cvmx_agl_gmx_bad_reg {
        uint64_t u64;
        struct cvmx_agl_gmx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_38_63:26;
                uint64_t txpsh1:1;
                uint64_t txpop1:1;
@@ -120,8 +121,25 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_4_21:18;
                uint64_t out_ovr:2;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:2;
+               uint64_t reserved_4_21:18;
+               uint64_t loststat:2;
+               uint64_t reserved_24_25:2;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t ovrflw1:1;
+               uint64_t txpop1:1;
+               uint64_t txpsh1:1;
+               uint64_t reserved_38_63:26;
+#endif
        } s;
        struct cvmx_agl_gmx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_38_63:26;
                uint64_t txpsh1:1;
                uint64_t txpop1:1;
@@ -136,9 +154,26 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_4_21:18;
                uint64_t out_ovr:2;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:2;
+               uint64_t reserved_4_21:18;
+               uint64_t loststat:1;
+               uint64_t reserved_23_25:3;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t ovrflw1:1;
+               uint64_t txpop1:1;
+               uint64_t txpsh1:1;
+               uint64_t reserved_38_63:26;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_bad_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_35_63:29;
                uint64_t txpsh:1;
                uint64_t txpop:1;
@@ -150,32 +185,64 @@ union cvmx_agl_gmx_bad_reg {
                uint64_t reserved_3_21:19;
                uint64_t out_ovr:1;
                uint64_t reserved_0_1:2;
+#else
+               uint64_t reserved_0_1:2;
+               uint64_t out_ovr:1;
+               uint64_t reserved_3_21:19;
+               uint64_t loststat:1;
+               uint64_t reserved_23_25:3;
+               uint64_t statovr:1;
+               uint64_t reserved_27_31:5;
+               uint64_t ovrflw:1;
+               uint64_t txpop:1;
+               uint64_t txpsh:1;
+               uint64_t reserved_35_63:29;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_bad_reg_s cn61xx;
        struct cvmx_agl_gmx_bad_reg_s cn63xx;
        struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
+       struct cvmx_agl_gmx_bad_reg_s cn66xx;
+       struct cvmx_agl_gmx_bad_reg_s cn68xx;
+       struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_bist {
        uint64_t u64;
        struct cvmx_agl_gmx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_25_63:39;
                uint64_t status:25;
+#else
+               uint64_t status:25;
+               uint64_t reserved_25_63:39;
+#endif
        } s;
        struct cvmx_agl_gmx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t status:10;
+#else
+               uint64_t status:10;
+               uint64_t reserved_10_63:54;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_bist_cn52xx cn56xx;
        struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_bist_s cn61xx;
        struct cvmx_agl_gmx_bist_s cn63xx;
        struct cvmx_agl_gmx_bist_s cn63xxp1;
+       struct cvmx_agl_gmx_bist_s cn66xx;
+       struct cvmx_agl_gmx_bist_s cn68xx;
+       struct cvmx_agl_gmx_bist_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_drv_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_49_63:15;
                uint64_t byp_en1:1;
                uint64_t reserved_45_47:3;
@@ -188,16 +255,39 @@ union cvmx_agl_gmx_drv_ctl {
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_15:3;
+               uint64_t byp_en:1;
+               uint64_t reserved_17_31:15;
+               uint64_t nctl1:5;
+               uint64_t reserved_37_39:3;
+               uint64_t pctl1:5;
+               uint64_t reserved_45_47:3;
+               uint64_t byp_en1:1;
+               uint64_t reserved_49_63:15;
+#endif
        } s;
        struct cvmx_agl_gmx_drv_ctl_s cn52xx;
        struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t byp_en:1;
                uint64_t reserved_13_15:3;
                uint64_t pctl:5;
                uint64_t reserved_5_7:3;
                uint64_t nctl:5;
+#else
+               uint64_t nctl:5;
+               uint64_t reserved_5_7:3;
+               uint64_t pctl:5;
+               uint64_t reserved_13_15:3;
+               uint64_t byp_en:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
 };
@@ -205,9 +295,15 @@ union cvmx_agl_gmx_drv_ctl {
 union cvmx_agl_gmx_inf_mode {
        uint64_t u64;
        struct cvmx_agl_gmx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_2_63:62;
                uint64_t en:1;
                uint64_t reserved_0_0:1;
+#else
+               uint64_t reserved_0_0:1;
+               uint64_t en:1;
+               uint64_t reserved_2_63:62;
+#endif
        } s;
        struct cvmx_agl_gmx_inf_mode_s cn52xx;
        struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
@@ -218,6 +314,7 @@ union cvmx_agl_gmx_inf_mode {
 union cvmx_agl_gmx_prtx_cfg {
        uint64_t u64;
        struct cvmx_agl_gmx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_14_63:50;
                uint64_t tx_idle:1;
                uint64_t rx_idle:1;
@@ -231,8 +328,24 @@ union cvmx_agl_gmx_prtx_cfg {
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t rx_en:1;
+               uint64_t tx_en:1;
+               uint64_t burst:1;
+               uint64_t reserved_7_7:1;
+               uint64_t speed_msb:1;
+               uint64_t reserved_9_11:3;
+               uint64_t rx_idle:1;
+               uint64_t tx_idle:1;
+               uint64_t reserved_14_63:50;
+#endif
        } s;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t tx_en:1;
                uint64_t rx_en:1;
@@ -240,139 +353,230 @@ union cvmx_agl_gmx_prtx_cfg {
                uint64_t duplex:1;
                uint64_t speed:1;
                uint64_t en:1;
+#else
+               uint64_t en:1;
+               uint64_t speed:1;
+               uint64_t duplex:1;
+               uint64_t slottime:1;
+               uint64_t rx_en:1;
+               uint64_t tx_en:1;
+               uint64_t reserved_6_63:58;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
        struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
        struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
+       struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
+       struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
+       struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam0 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam1 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam2 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam3 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam4 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t adr:64;
+#else
+               uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam5 {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+               uint64_t adr:64;
+#else
                uint64_t adr:64;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam_en {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_8_63:56;
                uint64_t en:8;
+#else
+               uint64_t en:8;
+               uint64_t reserved_8_63:56;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t cam_mode:1;
                uint64_t mcst:2;
                uint64_t bcst:1;
+#else
+               uint64_t bcst:1;
+               uint64_t mcst:2;
+               uint64_t cam_mode:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_decision {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_5_63:59;
                uint64_t cnt:5;
+#else
+               uint64_t cnt:5;
+               uint64_t reserved_5_63:59;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_decision_s cn52xx;
        struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_decision_s cn56xx;
        struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_decision_s cn61xx;
        struct cvmx_agl_gmx_rxx_decision_s cn63xx;
        struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_decision_s cn66xx;
+       struct cvmx_agl_gmx_rxx_decision_s cn68xx;
+       struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_chk {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t niberr:1;
                uint64_t skperr:1;
@@ -384,8 +588,22 @@ union cvmx_agl_gmx_rxx_frm_chk {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t reserved_10_63:54;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t skperr:1;
                uint64_t rcverr:1;
@@ -396,17 +614,34 @@ union cvmx_agl_gmx_rxx_frm_chk {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_63:55;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_13_63:51;
                uint64_t ptp_mode:1;
                uint64_t reserved_11_11:1;
@@ -421,8 +656,25 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t null_dis:1;
+               uint64_t reserved_11_11:1;
+               uint64_t ptp_mode:1;
+               uint64_t reserved_13_63:51;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_10_63:54;
                uint64_t pre_align:1;
                uint64_t pad_len:1;
@@ -434,59 +686,104 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                uint64_t ctl_drp:1;
                uint64_t pre_strp:1;
                uint64_t pre_chk:1;
+#else
+               uint64_t pre_chk:1;
+               uint64_t pre_strp:1;
+               uint64_t ctl_drp:1;
+               uint64_t ctl_bck:1;
+               uint64_t ctl_mcst:1;
+               uint64_t ctl_smac:1;
+               uint64_t pre_free:1;
+               uint64_t vlan_len:1;
+               uint64_t pad_len:1;
+               uint64_t pre_align:1;
+               uint64_t reserved_10_63:54;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_max {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_min {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t len:16;
+#else
+               uint64_t len:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
        struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
+       struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_ifg {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t ifg:4;
+#else
+               uint64_t ifg:4;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
        struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
+       struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
+       struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_en {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -508,8 +805,32 @@ union cvmx_agl_gmx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t reserved_16_18:3;
@@ -529,17 +850,43 @@ union cvmx_agl_gmx_rxx_int_en {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
        struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
        struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
+       struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
+       struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_reg {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t phy_dupx:1;
@@ -561,8 +908,32 @@ union cvmx_agl_gmx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t carext:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t carext:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t niberr:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t phy_link:1;
+               uint64_t phy_spd:1;
+               uint64_t phy_dupx:1;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_20_63:44;
                uint64_t pause_drp:1;
                uint64_t reserved_16_18:3;
@@ -582,666 +953,1130 @@ union cvmx_agl_gmx_rxx_int_reg {
                uint64_t maxerr:1;
                uint64_t reserved_1_1:1;
                uint64_t minerr:1;
+#else
+               uint64_t minerr:1;
+               uint64_t reserved_1_1:1;
+               uint64_t maxerr:1;
+               uint64_t jabber:1;
+               uint64_t fcserr:1;
+               uint64_t alnerr:1;
+               uint64_t lenerr:1;
+               uint64_t rcverr:1;
+               uint64_t skperr:1;
+               uint64_t reserved_9_9:1;
+               uint64_t ovrerr:1;
+               uint64_t pcterr:1;
+               uint64_t rsverr:1;
+               uint64_t falerr:1;
+               uint64_t coldet:1;
+               uint64_t ifgerr:1;
+               uint64_t reserved_16_18:3;
+               uint64_t pause_drp:1;
+               uint64_t reserved_20_63:44;
+#endif
        } cn52xx;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
        struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
        struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
+       struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_jabber {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t cnt:16;
+#else
+               uint64_t cnt:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
        struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
+       struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
+       struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_pause_drop_time {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_16_63:48;
                uint64_t status:16;
+#else
+               uint64_t status:16;
+               uint64_t reserved_16_63:48;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
+       struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_rx_inbnd {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_4_63:60;
                uint64_t duplex:1;
                uint64_t speed:2;
                uint64_t status:1;
+#else
+               uint64_t status:1;
+               uint64_t speed:2;
+               uint64_t duplex:1;
+               uint64_t reserved_4_63:60;
+#endif
        } s;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
+       struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_1_63:63;
                uint64_t rd_clr:1;
+#else
+               uint64_t rd_clr:1;
+               uint64_t reserved_1_63:63;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_dmac {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_drp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_48_63:16;
                uint64_t cnt:48;
+#else
+               uint64_t cnt:48;
+               uint64_t reserved_48_63:16;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_bad {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_drp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_32_63:32;
                uint64_t cnt:32;
+#else
+               uint64_t cnt:32;
+               uint64_t reserved_32_63:32;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_udd_skp {
        uint64_t u64;
        struct cvmx_agl_gmx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t fcssel:1;
                uint64_t reserved_7_7:1;
                uint64_t len:7;
+#else
+               uint64_t len:7;
+               uint64_t reserved_7_7:1;
+               uint64_t fcssel:1;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
+       struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_dropx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t mark:6;
+#else
+               uint64_t mark:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_offx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_6_63:58;
                uint64_t mark:6;
+#else
+               uint64_t mark:6;
+               uint64_t reserved_6_63:58;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_onx {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_9_63:55;
                uint64_t mark:9;
+#else
+               uint64_t mark:9;
+               uint64_t reserved_9_63:55;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
        struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
        struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
+       struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_prt_info {
        uint64_t u64;
        struct cvmx_agl_gmx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_18_63:46;
                uint64_t drop:2;
                uint64_t reserved_2_15:14;
                uint64_t commit:2;
+#else
+               uint64_t commit:2;
+               uint64_t reserved_2_15:14;
+               uint64_t drop:2;
+               uint64_t reserved_18_63:46;
+#endif
        } s;
        struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
        struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_17_63:47;
                uint64_t drop:1;
                uint64_t reserved_1_15:15;
                uint64_t commit:1;
+#else
+               uint64_t commit:1;
+               uint64_t reserved_1_15:15;
+               uint64_t drop:1;
+               uint64_t reserved_17_63:47;
+#endif
        } cn56xx;
        struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+       struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
        struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
+       struct cvmx_agl_gmx_rx_prt_info_s cn66xx;