video: tegra: dc: Fix the false alarm of pixel clock on FPGA.
Kevin Huang [Fri, 20 Apr 2012 06:41:38 +0000 (23:41 -0700)]
Bug 971127

Change-Id: Ia4cc51aaa41338ffd9bf1182c1a34587b62687fc
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/97829
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra354013427eedec0aa01a22ece1075ea1069144b

drivers/video/tegra/dc/dc.c

index 0cb00ef..e47001a 100644 (file)
@@ -1531,7 +1531,7 @@ static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
        return clk_get_rate(dc->clk);
 #else
-       return 27000000;
+       return dc->mode.pclk;
 #endif
 }