video: tegra: hdmi: choose clk rate above 100MHz
Naveen Kumar S [Wed, 20 Jul 2016 11:17:05 +0000 (16:17 +0530)]
pll_d2 runs at a minimum of 100MHz on T124. Update logic
to choose parent clock rate more than 100MHz.
e.g.: A mode with 32MHz pclk chooses parent clock of
96MHz with a divider of 3.0, which fails as pll_d
can't be pulled below 100MHz.

bug 1785365

Change-Id: I12400549a3ed42295ddd46adcb6493232f2d896a
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/1184235
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>

drivers/video/tegra/dc/hdmi.c

index cb1a6c8..eb8cf5d 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2010 Google, Inc.
  * Author: Erik Gilling <konkers@android.com>
  *
- * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -2219,6 +2219,10 @@ static unsigned long  tegra12x_hdmi_determine_parent(
                f = m % 1000;  /* fractional parts */
                f = (0 == f) ? f : (1000 - f);  /* round-up */
                if (0 == f) {  /* exact match */
+                       if ((ref / 2 * b) < 100000000) {
+                               /* parent clock runs at a minumum of 100MHz */
+                               continue;
+                       }
                        b = n;
                        fr = f;
                        break;