blackfin: bf60x: add clock support
Steven Miao [Wed, 16 May 2012 09:49:52 +0000 (17:49 +0800)]
Add clock support for bf60x.

Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>

arch/blackfin/include/asm/clkdev.h [new file with mode: 0644]
arch/blackfin/include/asm/clocks.h
arch/blackfin/mach-bf609/clock.c [new file with mode: 0644]
arch/blackfin/mach-common/clock.h [new file with mode: 0644]
arch/blackfin/mach-common/clocks-init.c
arch/blackfin/mach-common/cpufreq.c

diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
new file mode 100644 (file)
index 0000000..9053bed
--- /dev/null
@@ -0,0 +1,14 @@
+#ifndef __ASM_CLKDEV__H_
+#define __ASM_CLKDEV__H_
+
+#include <linux/slab.h>
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+       return kzalloc(size, GFP_KERNEL);
+}
+
+#define __clk_put(clk)
+#define __clk_get(clk) ({ 1; })
+
+#endif
index 6f0b618..9b3c85b 100644 (file)
 # define CONFIG_VCO_MULT 0
 #endif
 
+#include <linux/clk.h>
+
+struct clk_ops {
+       unsigned long (*get_rate)(struct clk *clk);
+       unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+       int (*set_rate)(struct clk *clk, unsigned long rate);
+       int (*enable)(struct clk *clk);
+       int (*disable)(struct clk *clk);
+};
+
+struct clk {
+       struct clk              *parent;
+       const char              *name;
+       unsigned long           rate;
+       spinlock_t              lock;
+       u32                     flags;
+       const struct clk_ops    *ops;
+       void __iomem            *reg;
+       u32                     mask;
+       u32                     shift;
+};
+
+int clk_init(void);
 #endif
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
new file mode 100644 (file)
index 0000000..b50412c
--- /dev/null
@@ -0,0 +1,390 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/io.h>
+#include <linux/seq_file.h>
+#include <linux/clkdev.h>
+
+#include <asm/clocks.h>
+
+#define CGU0_CTL_DF (1 << 0)
+
+#define CGU0_CTL_MSEL_SHIFT 8
+#define CGU0_CTL_MSEL_MASK (0x7f << 8)
+
+#define CGU0_STAT_PLLEN (1 << 0)
+#define CGU0_STAT_PLLBP (1 << 1)
+#define CGU0_STAT_PLLLK (1 << 2)
+#define CGU0_STAT_CLKSALGN (1 << 3)
+#define CGU0_STAT_CCBF0 (1 << 4)
+#define CGU0_STAT_CCBF1 (1 << 5)
+#define CGU0_STAT_SCBF0 (1 << 6)
+#define CGU0_STAT_SCBF1 (1 << 7)
+#define CGU0_STAT_DCBF (1 << 8)
+#define CGU0_STAT_OCBF (1 << 9)
+#define CGU0_STAT_ADDRERR (1 << 16)
+#define CGU0_STAT_LWERR (1 << 17)
+#define CGU0_STAT_DIVERR (1 << 18)
+#define CGU0_STAT_WDFMSERR (1 << 19)
+#define CGU0_STAT_WDIVERR (1 << 20)
+#define CGU0_STAT_PLOCKERR (1 << 21)
+
+#define CGU0_DIV_CSEL_SHIFT 0
+#define CGU0_DIV_CSEL_MASK 0x0000001F
+#define CGU0_DIV_S0SEL_SHIFT 5
+#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
+#define CGU0_DIV_SYSSEL_SHIFT 8
+#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
+#define CGU0_DIV_S1SEL_SHIFT 13
+#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
+#define CGU0_DIV_DSEL_SHIFT 16
+#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
+#define CGU0_DIV_OSEL_SHIFT 22
+#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
+
+#define CLK(_clk, _devname, _conname)                   \
+       {                                               \
+               .clk    = &_clk,                  \
+               .dev_id = _devname,                     \
+               .con_id = _conname,                     \
+       }
+
+#define NEEDS_INITIALIZATION 0x11
+
+static LIST_HEAD(clk_list);
+
+static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
+{
+       u32 val2;
+
+       val2 = bfin_read32(reg);
+       val2 &= ~mask;
+       val2 |= val;
+       bfin_write32(reg, val2);
+}
+
+static void clk_reg_set_bits(u32 reg, uint32_t mask)
+{
+       u32 val;
+
+       val = bfin_read32(reg);
+       val |= mask;
+       bfin_write32(reg, val);
+}
+
+static void clk_reg_clear_bits(u32 reg, uint32_t mask)
+{
+       u32 val;
+
+       val = bfin_read32(reg);
+       val &= ~mask;
+       bfin_write32(reg, val);
+}
+
+int wait_for_pll_align(void)
+{
+       int i = 10000;
+       while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
+
+       if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
+               printk(KERN_DEBUG "fail to align clk\n");
+               return -1;
+       }
+       return 0;
+}
+
+int clk_enable(struct clk *clk)
+{
+       int ret = -EIO;
+       if (clk->ops && clk->ops->enable)
+               ret = clk->ops->enable(clk);
+       return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+       if (clk->ops && clk->ops->disable)
+               clk->ops->disable(clk);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+       unsigned long ret = 0;
+       if (clk->ops && clk->ops->get_rate)
+               ret = clk->ops->get_rate(clk);
+       return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       long ret = -EIO;
+       if (clk->ops && clk->ops->round_rate)
+               ret = clk->ops->round_rate(clk, rate);
+       return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       int ret = -EIO;
+       if (clk->ops && clk->ops->set_rate)
+               ret = clk->ops->set_rate(clk, rate);
+       return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+unsigned long vco_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+
+unsigned long pll_get_rate(struct clk *clk)
+{
+       u32 df;
+       u32 msel;
+       u32 ctl = bfin_read32(CGU0_CTL);
+       u32 stat = bfin_read32(CGU0_STAT);
+       if (stat & CGU0_STAT_PLLBP)
+               return 0;
+       msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+       df = (ctl &  CGU0_CTL_DF);
+       clk->parent->rate = clk_get_rate(clk->parent);
+       return clk->parent->rate / (df + 1) * msel * 2;
+}
+
+unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
+{
+       u32 div;
+       div = rate / clk->parent->rate;
+       return clk->parent->rate * div;
+}
+
+int pll_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 msel;
+       u32 stat = bfin_read32(CGU0_STAT);
+       if (!(stat & CGU0_STAT_PLLEN))
+               return -EBUSY;
+       if (!(stat & CGU0_STAT_PLLLK))
+               return -EBUSY;
+       if (wait_for_pll_align())
+               return -EBUSY;
+       msel = rate / clk->parent->rate / 2;
+       clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
+               CGU0_CTL_MSEL_MASK);
+       clk->rate = rate;
+       return 0;
+}
+
+unsigned long cclk_get_rate(struct clk *clk)
+{
+       if (clk->parent)
+               return clk->parent->rate;
+       else
+               return 0;
+}
+
+unsigned long sys_clk_get_rate(struct clk *clk)
+{
+       unsigned long drate;
+       u32 msel;
+       u32 df;
+       u32 ctl = bfin_read32(CGU0_CTL);
+       u32 div = bfin_read32(CGU0_DIV);
+       div = (div & clk->mask) >> clk->shift;
+       msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+       df = (ctl &  CGU0_CTL_DF);
+
+       if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
+               drate = clk->parent->rate / (df + 1);
+               drate *=  msel;
+               drate /= div;
+               return drate;
+       } else {
+               clk->parent->rate = clk_get_rate(clk->parent);
+               return clk->parent->rate / div;
+       }
+}
+
+unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned long max_rate;
+       unsigned long drate;
+       int i;
+       u32 msel;
+       u32 df;
+       u32 ctl = bfin_read32(CGU0_CTL);
+
+       msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+       df = (ctl &  CGU0_CTL_DF);
+       max_rate = clk->parent->rate / (df + 1) * msel;
+
+       if (rate > max_rate)
+               return 0;
+
+       for (i = 1; i < clk->mask; i++) {
+               drate = max_rate / i;
+               if (rate >= drate)
+                       return drate;
+       }
+       return 0;
+}
+
+int sys_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 div = bfin_read32(CGU0_DIV);
+       div = (div & clk->mask) >> clk->shift;
+
+       rate = clk_round_rate(clk, rate);
+
+       if (!rate)
+               return -EINVAL;
+
+       div = (clk_get_rate(clk) * div) / rate;
+
+       if (wait_for_pll_align())
+               return -EBUSY;
+       clk_reg_write_mask(CGU0_DIV, div << clk->shift,
+                       clk->mask);
+       clk->rate = rate;
+       return 0;
+}
+
+static struct clk_ops vco_ops = {
+       .get_rate = vco_get_rate,
+};
+
+static struct clk_ops pll_ops = {
+       .get_rate = pll_get_rate,
+       .set_rate = pll_set_rate,
+};
+
+static struct clk_ops cclk_ops = {
+       .get_rate = cclk_get_rate,
+};
+
+static struct clk_ops sys_clk_ops = {
+       .get_rate = sys_clk_get_rate,
+       .set_rate = sys_clk_set_rate,
+       .round_rate = sys_clk_round_rate,
+};
+
+static struct clk sys_clkin = {
+       .name       = "SYS_CLKIN",
+       .rate       = CONFIG_CLKIN_HZ,
+       .ops        = &vco_ops,
+};
+
+static struct clk pll_clk = {
+       .name       = "PLLCLK",
+       .rate       = 500000000,
+       .parent     = &sys_clkin,
+       .ops = &pll_ops,
+       .flags = NEEDS_INITIALIZATION,
+};
+
+static struct clk cclk = {
+       .name       = "CCLK",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_CSEL_MASK,
+       .shift      = CGU0_DIV_CSEL_SHIFT,
+       .parent     = &sys_clkin,
+       .ops        = &sys_clk_ops,
+       .flags = NEEDS_INITIALIZATION,
+};
+
+static struct clk cclk0 = {
+       .name       = "CCLK0",
+       .parent     = &cclk,
+       .ops        = &cclk_ops,
+};
+
+static struct clk cclk1 = {
+       .name       = "CCLK1",
+       .parent     = &cclk,
+       .ops        = &cclk_ops,
+};
+
+static struct clk sysclk = {
+       .name       = "SYSCLK",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_SYSSEL_MASK,
+       .shift      = CGU0_DIV_SYSSEL_SHIFT,
+       .parent     = &sys_clkin,
+       .ops        = &sys_clk_ops,
+       .flags = NEEDS_INITIALIZATION,
+};
+
+static struct clk sclk0 = {
+       .name       = "SCLK0",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_S0SEL_MASK,
+       .shift      = CGU0_DIV_S0SEL_SHIFT,
+       .parent     = &sysclk,
+       .ops        = &sys_clk_ops,
+};
+
+static struct clk sclk1 = {
+       .name       = "SCLK1",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_S1SEL_MASK,
+       .shift      = CGU0_DIV_S1SEL_SHIFT,
+       .parent     = &sysclk,
+       .ops        = &sys_clk_ops,
+};
+
+static struct clk dclk = {
+       .name       = "DCLK",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_DSEL_MASK,
+       .shift       = CGU0_DIV_DSEL_SHIFT,
+       .parent     = &pll_clk,
+       .ops        = &sys_clk_ops,
+};
+
+static struct clk oclk = {
+       .name       = "OCLK",
+       .rate       = 500000000,
+       .mask       = CGU0_DIV_OSEL_MASK,
+       .shift      = CGU0_DIV_OSEL_SHIFT,
+       .parent     = &pll_clk,
+};
+
+static struct clk_lookup bf609_clks[] = {
+       CLK(sys_clkin, NULL, "SYS_CLKIN"),
+       CLK(pll_clk, NULL, "PLLCLK"),
+       CLK(cclk, NULL, "CCLK"),
+       CLK(cclk0, NULL, "CCLK0"),
+       CLK(cclk1, NULL, "CCLK1"),
+       CLK(sysclk, NULL, "SYSCLK"),
+       CLK(sclk0, NULL, "SCLK0"),
+       CLK(sclk1, NULL, "SCLK1"),
+       CLK(dclk, NULL, "DCLK"),
+       CLK(oclk, NULL, "OCLK"),
+};
+
+int __init clk_init(void)
+{
+       int i;
+       struct clk *clkp;
+       for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
+               clkp = bf609_clks[i].clk;
+               if (clkp->flags & NEEDS_INITIALIZATION)
+                       clk_get_rate(clkp);
+       }
+       clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
+       return 0;
+}
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
new file mode 100644 (file)
index 0000000..645ff46
--- /dev/null
@@ -0,0 +1,27 @@
+#ifndef __MACH_COMMON_CLKDEV_H
+#define __MACH_COMMON_CLKDEV_H
+
+#include <linux/clk.h>
+
+struct clk_ops {
+       unsigned long (*get_rate)(struct clk *clk);
+       unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+       int (*set_rate)(struct clk *clk, unsigned long rate);
+       int (*enable)(struct clk *clk);
+       int (*disable)(struct clk *clk);
+};
+
+struct clk {
+       const char              *name;
+       unsigned long           rate;
+       spinlock_t              lock;
+       u32                     flags;
+       const struct clk_ops    *ops;
+       const struct params     *params;
+       void __iomem            *reg;
+       u32                     mask;
+       u32                     shift;
+};
+
+#endif
+
index d5cfe61..1e6beca 100644 (file)
@@ -33,6 +33,8 @@ void init_clocks(void)
         * in the middle of reprogramming things, and that'll screw us up.
         * For example, any automatic DMAs left by U-Boot for splash screens.
         */
+
+#if 0
        size_t i;
        for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
                struct dma_register *dma = dma_io_base_addr[i];
@@ -93,4 +95,6 @@ void init_clocks(void)
 #endif
        do_sync();
        bfin_read16(0);
+
+#endif
 }
index 2e6eefd..3b68879 100644 (file)
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/fs.h>
 #include <linux/delay.h>
@@ -17,6 +18,7 @@
 #include <asm/time.h>
 #include <asm/dpmc.h>
 
+
 /* this is the table of CCLK frequencies, in Hz */
 /* .index is the entry in the auxiliary dpm_state_table[] */
 static struct cpufreq_frequency_table bfin_freq_table[] = {
@@ -67,12 +69,22 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
 #else
        min_cclk = sclk;
 #endif
+
+#ifndef CONFIG_BF60x
        csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
+#else
+       csel = bfin_read32(CGU0_DIV) & 0x1F;
+#endif
 
        for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
                bfin_freq_table[index].frequency = cclk >> index;
+#ifndef CONFIG_BF60x
                dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
                dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
+#else
+               dpm_state_table[index].csel = csel;
+               dpm_state_table[index].tscale =  TIME_SCALE >> index;
+#endif
 
                pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
                                                 bfin_freq_table[index].frequency,
@@ -99,6 +111,20 @@ static unsigned int bfin_getfreq_khz(unsigned int cpu)
        return get_cclk() / 1000;
 }
 
+unsigned long cpu_set_cclk(int cpu, unsigned long new)
+{
+       struct clk *clk;
+       int ret;
+
+       clk = clk_get(NULL, "CCLK");
+       if (IS_ERR(clk))
+               return -ENODEV;
+
+       ret = clk_set_rate(clk, new);
+       clk_put(clk);
+       return ret;
+}
+
 static int bfin_target(struct cpufreq_policy *poli,
                        unsigned int target_freq, unsigned int relation)
 {
@@ -107,6 +133,7 @@ static int bfin_target(struct cpufreq_policy *poli,
        struct cpufreq_freqs freqs;
        static unsigned long lpj_ref;
        static unsigned int  lpj_ref_freq;
+       int ret = 0;
 
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
        cycles_t cycles;
@@ -134,9 +161,17 @@ static int bfin_target(struct cpufreq_policy *poli,
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
                if (cpu == CPUFREQ_CPU) {
                        flags = hard_local_irq_save();
+#ifndef CONFIG_BF60x
                        plldiv = (bfin_read_PLL_DIV() & SSEL) |
                                                dpm_state_table[index].csel;
                        bfin_write_PLL_DIV(plldiv);
+#else
+                       ret = cpu_set_cclk(cpu, freqs.new * 1000);
+                       if (ret != 0) {
+                               pr_debug("cpufreq set freq failed %d\n", ret);
+                               break;
+                       }
+#endif
                        on_each_cpu(bfin_adjust_core_timer, &index, 1);
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
                        cycles = get_cycles();
@@ -161,7 +196,7 @@ static int bfin_target(struct cpufreq_policy *poli,
        }
 
        pr_debug("cpufreq: done\n");
-       return 0;
+       return ret;
 }
 
 static int bfin_verify_speed(struct cpufreq_policy *policy)
@@ -169,7 +204,7 @@ static int bfin_verify_speed(struct cpufreq_policy *policy)
        return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 }
 
-static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
+static int __bfin_cpu_init(struct cpufreq_policy *policy)
 {
 
        unsigned long cclk, sclk;