ARM: tegra11: power: Add CPU EDP safety limits
Alex Frid [Sat, 29 Dec 2012 05:18:47 +0000 (21:18 -0800)]
Added fixed absolute CPU EDP safety limits that are applied on top
of calculated EDP limits across all temperatures and process corners.

Bug 1161126

Change-Id: I9cb33a0a94115a83220d9b70950823fcbbf96427
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/187570
(cherry picked from commit 356cec5d26b07603e2014aedaf197354b52ee1d6)
Reviewed-on: http://git-master/r/188919
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/edp.c
arch/arm/mach-tegra/include/mach/edp.h

index ff6d134..0e59df6 100644 (file)
@@ -388,6 +388,7 @@ static struct tegra_edp_cpu_leakage_params leakage_params[] = {
                           {   15618709,   -4576116,   158401,  -1538, },
                         },
                 },
+               .safety_cap = { 1810500, 1810500, 1606500, 1606500 },
        },
        {
                .cpu_speedo_id      = 2, /* A01P+ fast CPU */
@@ -419,6 +420,7 @@ static struct tegra_edp_cpu_leakage_params leakage_params[] = {
                           {   15618709,   -4576116,   158401,  -1538, },
                         },
                 },
+               .safety_cap = { 1912500, 1912500, 1708500, 1708500 },
        },
 };
 
@@ -588,13 +590,22 @@ static int init_cpu_edp_limits_calculated(void)
        for (temp_idx = 0; temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
                edp_calculated_limits[temp_idx].
                        temperature = temperatures[temp_idx];
-               for (n_cores_idx = 0; n_cores_idx < NR_CPUS; n_cores_idx++)
-                       edp_calculated_limits[temp_idx].
-                               freq_limits[n_cores_idx] =
+               for (n_cores_idx = 0; n_cores_idx < NR_CPUS; n_cores_idx++) {
+                       unsigned int cap;
+                       unsigned int limit =
                                edp_calculate_maxf(params,
                                                   temperatures[temp_idx],
                                                   iddq_mA,
                                                   n_cores_idx);
+                       /* apply safety cap if it is specified */
+                       if (n_cores_idx < 4) {
+                               cap = params->safety_cap[n_cores_idx];
+                               if (cap && cap < limit)
+                                       limit = cap;
+                       }
+                       edp_calculated_limits[temp_idx].
+                               freq_limits[n_cores_idx] = limit;
+               }
        }
 
        /*
index 7dfea8d..0e3c218 100644 (file)
@@ -48,6 +48,7 @@ struct tegra_edp_cpu_leakage_params {
        int dyn_consts_n[NR_CPUS];       /* pre-multiplied by 1,000,000 */
        int leakage_consts_n[NR_CPUS];   /* pre-multiplied by 1,000,000 */
        int leakage_consts_ijk[4][4][4]; /* pre-multiplied by 100,000 */
+       unsigned int safety_cap[4];
 };
 
 struct tegra_edp_freq_voltage_table {