regulator: max77620: add support for enable/disable active discharge
Laxman Dewangan [Thu, 29 Oct 2015 09:08:11 +0000 (14:08 +0530)]
Add support for enabling/disabling active discharge through platform
DT node.

Change-Id: I4e2872f4f66747f332d9e86b1efd7ff3cf5f2253
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/824695
(cherry picked from commit 753e63cbeb4e3c3effc406a6e952eb5968726a61)
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/825310
GVS: Gerrit_Virtual_Submit

drivers/regulator/max77620-regulator.c
include/linux/mfd/max77620.h

index 5cd3e2d..59f1417 100644 (file)
@@ -639,6 +639,27 @@ static int max77620_regulator_preinit(struct max77620_regulator *reg, int id)
                return ret;
        }
 
+       if (ridata->constraints.enable_active_discharge ||
+               ridata->constraints.disable_active_discharge) {
+               val = 0;
+               if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
+                       mask = MAX77620_SD_CFG1_ADE_MASK;
+                       if (ridata->constraints.enable_active_discharge)
+                               val = MAX77620_SD_CFG1_ADE_ENABLE;
+               } else {
+                       mask = MAX77620_LDO_CFG2_ADE_MASK;
+                       if (ridata->constraints.enable_active_discharge)
+                               val = MAX77620_LDO_CFG2_ADE_ENABLE;
+               }
+               ret = max77620_reg_update(parent, MAX77620_PWR_SLAVE,
+                               rinfo->cfg_addr, mask, val);
+               if (ret < 0) {
+                       dev_err(reg->dev, "Reg 0x%02x update failed: %d\n",
+                               rinfo->cfg_addr, ret);
+                       return ret;
+               }
+       }
+
        if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
                int slew_rate;
                u8 val_u8;
index 19273a2..c4c55f6 100644 (file)
 /* Device Indentification OTP */
 #define MAX77620_CID5_DIDO(n)                  ((n) & 0xF)
 
-#define MAX77620_SD_FSRADE_MASK                0x01
-#define MAX77620_SD_FSRADE_SHIFT       0
-#define MAX77620_SD_FSRADE_DISABLE     0x40
-
-#define MAX77620_SD_POWER_MODE_MASK    0x30
-#define MAX77620_SD_POWER_MODE_SHIFT   4
-#define MAX77620_LDO_POWER_MODE_MASK   0xC0
-#define MAX77620_LDO_POWER_MODE_SHIFT  6
+/* SD CNFG1 */
 #define MAX77620_SD_SR_MASK            0xC0
 #define MAX77620_SD_SR_SHIFT           6
-#define MAX77620_SD_FORCED_PWM_MODE    0x20
-
+#define MAX77620_SD_POWER_MODE_MASK    0x30
+#define MAX77620_SD_POWER_MODE_SHIFT   4
+#define MAX77620_SD_CFG1_ADE_MASK      BIT(3)
+#define MAX77620_SD_CFG1_ADE_DISABLE   0
+#define MAX77620_SD_CFG1_ADE_ENABLE    BIT(3)
 #define MAX77620_SD_FPWM_MASK          0x04
 #define MAX77620_SD_FPWM_SHIFT         2
+#define MAX77620_SD_FSRADE_MASK                0x01
+#define MAX77620_SD_FSRADE_SHIFT       0
+#define MAX77620_SD_CFG1_FPWM_SD_MASK          BIT(2)
+#define MAX77620_SD_CFG1_FPWM_SD_SKIP          0
+#define MAX77620_SD_CFG1_FPWM_SD_FPWM          BIT(2)
+#define MAX77620_SD_CFG1_FSRADE_SD_MASK                BIT(0)
+#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE     0
+#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE      BIT(0)
+
+/* LDO_CNFG2 */
+#define MAX77620_LDO_POWER_MODE_MASK   0xC0
+#define MAX77620_LDO_POWER_MODE_SHIFT  6
+#define MAX77620_LDO_CFG2_ADE_MASK             BIT(1)
+#define MAX77620_LDO_CFG2_ADE_DISABLE          0
+#define MAX77620_LDO_CFG2_ADE_ENABLE           BIT(1)
+#define MAX77620_LDO_CFG2_SS_MASK              BIT(0)
+#define MAX77620_LDO_CFG2_SS_FAST              BIT(0)
+#define MAX77620_LDO_CFG2_SS_SLOW              0
 
 #define MAX77620_IRQ_TOP_GLBL_MASK     BIT(7)
 #define MAX77620_IRQ_TOP_SD_MASK       BIT(6)