ARM: tegra: ardbeg: SDMMC4 ddr trim,clk limits
Pavan Kunapuli [Wed, 3 Jul 2013 14:00:43 +0000 (07:00 -0700)]
Set DDR50 mode trim delay to 0x4. Also, set the ddr mode and
default mode clock limits for sdmmc4.

Change-Id: I79047c805f7c6ebc66100382199e2778e77675dd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244769
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-sdhci.c

index c369588..11f4175 100644 (file)
@@ -168,11 +168,14 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .is_8bit = 1,
        .tap_delay = 0x4,
        .trim_delay = 0x4,
+       .ddr_trim_delay = 0x4,
        .mmc_data = {
                .built_in = 1,
                .ocr_mask = MMC_OCR_1V8_MASK,
        },
        .uhs_mask = MMC_MASK_HS200,
+       .ddr_clk_limit = 51000000,
+       .max_clk_limit = 102000000,
 /*     .max_clk = 12000000, */
 };