video: tegra: dc: Add edid quirk for denon dvr
Prafull Suryawanshi [Wed, 8 Feb 2017 10:51:44 +0000 (15:51 +0530)]
Denon DVR 2313 have YUV422 bug where it display out
pink screen when set this mode. So adding edid quirk
to filter out YUV422 modes for this DVR.

bug 200265680

Change-Id: I394bcb0df660cf18e460aaad88c0744c9f8ffeff
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-on: http://git-master/r/1301331
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
(cherry picked from commit 665da618c0ab47b13a973d3e3dc5792c7aa4eaae)
(cherry picked from commit ac0d2bfa3b41b83a8cebfede647ace08828cc6ff)
Reviewed-on: http://git-master/r/1458813
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>

drivers/video/tegra/dc/edid.h
drivers/video/tegra/dc/edid_quirks.c
drivers/video/tegra/fb.c

index 7547ac3..d7f56c7 100644 (file)
@@ -134,6 +134,8 @@ enum {
 #define TEGRA_EDID_QUIRK_NO_YUV     (1 << 0)
 /* TV needs us to delay HDCP by a few seconds */
 #define TEGRA_EDID_QUIRK_DELAY_HDCP (1 << 1)
+/* Denon 2313 doesn't support YUV422, but declares support for it */
+#define TEGRA_EDID_QUIRK_NO_YUV_422    (1 << 3)
 
 struct tegra_edid {
        struct tegra_edid_pvt   *data;
index 74a6a26..8bd27e6 100644 (file)
@@ -29,6 +29,8 @@ static const struct hdmi_blacklist {
        { "VIZ", 4120, "P55-C1",    TEGRA_EDID_QUIRK_DELAY_HDCP },
        { "VIZ", 4120, "P65-C1",    TEGRA_EDID_QUIRK_DELAY_HDCP },
        { "VIZ", 4120, "P75-C1",    TEGRA_EDID_QUIRK_DELAY_HDCP },
+       /* Denon 2313 doesn't support YUV422, but declares support for it */
+       { "DON", 48, "DENON-AVR",   TEGRA_EDID_QUIRK_NO_YUV_422 },
 };
 
 u32 tegra_edid_lookup_quirks(const char *manufacturer, u32 model,
index 35614ef..1f6466c 100644 (file)
@@ -6,7 +6,7 @@
  *         Colin Cross <ccross@android.com>
  *         Travis Geiselbrecht <travis@palm.com>
  *
- * Copyright (c) 2010-2016, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2010-2017, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -808,7 +808,9 @@ void tegra_fb_update_fix(struct tegra_fb_info *fb_info,
        BUILD_BUG_ON((TEGRA_DC_Y420_30 << 1) != FB_CAP_Y420_DC_30);
        BUILD_BUG_ON((TEGRA_DC_RGB_48 << 1) != FB_CAP_RGB_DC_48);
        fix->capabilities = (tegra_edid_get_cd_flag(dc_edid) << 1);
-       if (tegra_edid_support_yuv422(dc_edid))
+       if (tegra_edid_support_yuv422(dc_edid) &&
+               (!(tegra_edid_get_quirks(dc_edid) &
+               TEGRA_EDID_QUIRK_NO_YUV_422)))
                fix->capabilities |= FB_CAP_Y422;
        if (tegra_edid_support_yuv444(dc_edid))
                fix->capabilities |= FB_CAP_Y444;