ARM: tegra12: pm: Clear DPD_ENABLE on LP0 exit
Kamal Kannan Balagopalan [Thu, 18 Jul 2013 05:07:46 +0000 (22:07 -0700)]
DPD enable needs to be cleared for subsequent LP0 sequences to
work correctly

Bug 1321719

Change-Id: Iadc3244b84b6abe5b1bec2ff972f03b3d5a48f17
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/250546
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

arch/arm/mach-tegra/pm.c

index f1a8301..88617a4 100644 (file)
@@ -162,7 +162,7 @@ extern int tegra_smmu_suspend(struct device *dev);
 #define PMC_DPAD_ORIDE         0x1C
 #define PMC_WAKE_DELAY         0xe0
 #define PMC_DPD_SAMPLE         0x20
-#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+#if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
 #define PMC_DPD_ENABLE         0x24
 #endif
 #define PMC_IO_DPD_REQ          0x1B8
@@ -912,7 +912,7 @@ static void tegra_common_resume(void)
        void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
 #endif
 
-#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+#if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        /* Clear DPD Enable */
        writel(0x0, pmc + PMC_DPD_ENABLE);
 #endif