ARM: tegra: Split sleep.S for Tegra2
Scott Williams [Mon, 18 Jul 2011 22:20:56 +0000 (15:20 -0700)]
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e

arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/cpuidle-t2.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/sleep-t20.S
arch/arm/mach-tegra/sleep.S
arch/arm/mach-tegra/sleep.h

index dd2c508..2fae66a 100644 (file)
@@ -23,11 +23,11 @@ obj-y                                   += powergate.o
 obj-y                                   += apbio.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-y                                   += cpuidle.o
+obj-y                                   += sleep.o
 ifeq ($(CONFIG_PM_SLEEP),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-t2.o
 endif
 endif
-obj-$(CONFIG_CPU_IDLE)                  += sleep.o
 obj-y                                   += mc.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 obj-$(CONFIG_FIQ)                       += fiq.o
index eefa3b1..bfd9551 100644 (file)
@@ -74,7 +74,7 @@ static int tegra2_reset_sleeping_cpu(int cpu)
        tegra_pen_lock();
 
        if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
-               tegra_cpu_reset(cpu);
+               tegra2_cpu_reset(cpu);
        else
                ret = -EINVAL;
 
@@ -140,7 +140,7 @@ static int tegra2_idle_lp2_last(struct cpuidle_device *dev,
 {
        int i;
 
-       while (tegra_cpu_is_resettable_soon())
+       while (tegra2_cpu_is_resettable_soon())
                cpu_relax();
 
        if (tegra2_reset_other_cpus(dev->cpu))
@@ -176,7 +176,7 @@ void tegra2_idle_lp2(struct cpuidle_device *dev,
                        }
                }
        } else
-               tegra_sleep_wfi(PHYS_OFFSET - PAGE_OFFSET);
+               tegra2_sleep_wfi(PHYS_OFFSET - PAGE_OFFSET);
 
        cpu_pm_exit();
        tegra_clear_cpu_in_lp2(dev->cpu);
index b3cf281..03fd380 100644 (file)
@@ -436,7 +436,7 @@ bool tegra_set_cpu_in_lp2(int cpu)
                last_cpu = true;
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
        else
-               tegra_cpu_set_resettable_soon();
+               tegra2_cpu_set_resettable_soon();
 #endif
 
        spin_unlock(&tegra_lp2_lock);
@@ -515,7 +515,7 @@ static int tegra_common_suspend(void)
 
        /* copy the reset vector and SDRAM shutdown code into IRAM */
        memcpy(iram_save, iram_code, iram_save_size);
-       memcpy(iram_code, &tegra_iram_start, iram_save_size);
+       memcpy(iram_code, tegra_iram_start(), iram_save_size);
 
        return 0;
 }
@@ -592,7 +592,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
                 * tegra_lp1_reset in IRAM, which resumes the CPU to
                 * the address in scratch 41 to tegra_resume
                 */
-               writel(&tegra_lp1_reset - &tegra_iram_start +
+               writel(tegra_lp1_reset() - tegra_iram_start() +
                        TEGRA_IRAM_CODE_AREA, evp_reset);
                __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
                break;
@@ -792,7 +792,7 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
                plat->suspend_mode = TEGRA_SUSPEND_LP1;
        }
 
-       iram_save_size = &tegra_iram_end - &tegra_iram_start;
+       iram_save_size = tegra_iram_end() - tegra_iram_start();
 
        iram_save = kmalloc(iram_save_size, GFP_KERNEL);
        if (!iram_save) {
index 902afeb..f7e0e49 100644 (file)
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/const.h>
+#include <linux/init.h>
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/domain.h>
+#include <asm/memory.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/glue-cache.h>
+#include <asm/glue-proc.h>
+#include <asm/system.h>
 
 #include "sleep.h"
 #include "flowctrl.h"
@@ -106,15 +117,27 @@ ENTRY(tegra20_cpu_shutdown)
 ENDPROC(tegra20_cpu_shutdown)
 #endif
 
-ENTRY(tegra_cpu_set_resettable_soon)
+/*
+ * tegra2_cpu_set_resettable_soon(void)
+ *
+ * Called to set the "resettable soon" flag in PMC_SCRATCH41 when
+ * it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra2_cpu_set_resettable_soon)
        mov32   r3, TEGRA_PMC_VIRT
        add     r1, r3, #PMC_SCRATCH41
        mov     r12, #CPU_RESETTABLE_SOON
        str     r12, [r1]
        mov     pc, lr
-ENDPROC(tegra_cpu_set_resettable_soon)
+ENDPROC(tegra2_cpu_set_resettable_soon)
 
-ENTRY(tegra_cpu_is_resettable_soon)
+/*
+ * tegra2_cpu_is_resettable_soon(void)
+ *
+ * Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
+ * set because it is expected that the secondary CPU will be idle soon.
+ */
+ENTRY(tegra2_cpu_is_resettable_soon)
        mov32   r3, TEGRA_PMC_VIRT
        add     r1, r3, #PMC_SCRATCH41
        ldr     r12, [r1]
@@ -122,30 +145,30 @@ ENTRY(tegra_cpu_is_resettable_soon)
        moveq   r0, #1
        movne   r0, #0
        mov     pc, lr
-ENDPROC(tegra_cpu_is_resettable_soon)
+ENDPROC(tegra2_cpu_is_resettable_soon)
 
 /*
- * tegra_sleep_core(unsigned long v2p)
+ * tegra2_sleep_core(unsigned long v2p)
  *
  * enters suspend in LP0 or LP1 by turning off the mmu and jumping to
- * tegra_tear_down_core in IRAM
+ * tegra2_tear_down_core in IRAM
  */
-ENTRY(tegra_sleep_core)
+ENTRY(tegra2_sleep_core)
        mov     r3, lr                  @ set resume address to lr
        bl      tegra_cpu_save
 
-       mov32   r1, tegra_tear_down_core
-       mov32   r2, tegra_iram_start
+       mov32   r1, tegra2_tear_down_core
+       mov32   r2, tegra2_iram_start
        sub     r1, r1, r2
        mov32   r2, TEGRA_IRAM_CODE_AREA
        add     r1, r1, r2
        b       tegra_turn_off_mmu
-ENDPROC(tegra_sleep_core)
+ENDPROC(tegra2_sleep_core)
 
 /*
- * tegra_sleep_wfi(unsigned long v2p)
+ * tegra2_sleep_wfi(unsigned long v2p)
  */
-ENTRY(tegra_sleep_wfi)
+ENTRY(tegra2_sleep_wfi)
        mov     r3, lr                  @ set resume address to lr
        mrc     p15, 0, r2, c1, c0, 1   @ save actlr before exiting coherency
        bl      tegra_cpu_save
@@ -180,9 +203,6 @@ ENTRY(tegra_sleep_wfi)
        mcr     p15, 0, r11, c1, c0, 1  @ reenable coherency
 
        @ the cpu was running with coherency disabled, caches may be out of date
-       mov     r0, #0
-       mcr     p15, 0, r0, c8, c3, 0   @ invalidate TLB
-       mcr     p15, 0, r0, c7, c5, 6   @ flush BTAC
 #ifdef MULTI_CACHE
        mov32   r10, cpu_cache
        mov     lr, pc
@@ -191,101 +211,30 @@ ENTRY(tegra_sleep_wfi)
        bl      __cpuc_flush_kern_all
 #endif
 
-       b       tegra_cpu_sleep_abort
-ENDPROC(tegra_sleep_wfi)
-
-tegra_tear_down_cpu:
-       bl      tegra_cpu_pllp
-       b       tegra_enter_sleep
-
-/* START OF ROUTINES COPIED TO IRAM */
-       .align L1_CACHE_SHIFT
-       .globl tegra_iram_start
-tegra_iram_start:
-
-/*
- * tegra_tear_down_core
- *
- * copied into and executed from IRAM
- * puts memory in self-refresh for LP0 and LP1
- */
-tegra_tear_down_core:
-       bl      tegra_sdram_self_refresh
-       bl      tegra_cpu_clk32k
-       b       tegra_enter_sleep
-
-/*
- * tegra_cpu_clk32k
- *
- * In LP0 and LP1 all plls will be turned off.  Switch the CPU and system clock
- * to the 32khz clock (clks)
- */
-tegra_cpu_clk32k:
-       /* start by jumping to clkm to safely disable PLLs, then jump
-        * to clks */
-       mov     r0, #(1 << 28)
-       str     r0, [r5, #CLK_RESET_SCLK_BURST]
-       str     r0, [r5, #CLK_RESET_CCLK_BURST]
-       mov     r0, #0
-       str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
-       str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
-
-       /* 2 us delay between changing sclk and disabling PLLs */
-       mov32   r7, TEGRA_TMRUS_BASE
-       ldr     r1, [r7]
-       add     r1, r1, #3
-
-1:     ldr     r0, [r7]
-       cmp     r0, r1
-       dmb
-       bmi     1b
-
-       /* switch to CLKS */
-       mov     r0, #0  /* burst policy = 32KHz */
-       str     r0, [r5, #CLK_RESET_SCLK_BURST]
-
-       /* disable PLLP, PLLM, PLLC in LP0 and LP1 states */
-       ldr     r0, [r5, #CLK_RESET_PLLM_BASE]
-       bic     r0, r0, #(1 << 30)
-       str     r0, [r5, #CLK_RESET_PLLM_BASE]
-       ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
-       bic     r0, r0, #(1 << 30)
-       str     r0, [r5, #CLK_RESET_PLLP_BASE]
-       ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
-       bic     r0, r0, #(1 << 30)
-       str     r0, [r5, #CLK_RESET_PLLC_BASE]
+       ldmfd   sp!, {r4}
+       mcr     p15, 0, r4, c15, c0, 1  @ write diagnostic register
+       ldmfd   sp!, {lr}
+       ldmfd   sp!, {r4 - r11}
        mov     pc, lr
+ENDPROC(tegra2_sleep_wfi)
 
 /*
- * tegra_enter_sleep
+ * tegra2_tear_down_cpu
  *
- * uses flow controller to enter sleep state
- * executes from IRAM with SDRAM in selfrefresh when target state is LP0 and LP1
- * executes from SDRAM with target state is LP2
+ * Switches the CPU cluster to PLL-P and enters sleep.
  */
-tegra_enter_sleep:
-       mov32   r7, TEGRA_TMRUS_BASE
-       ldr     r1, [r7]
-       mov32   r4, TEGRA_PMC_BASE
-       str     r1, [r4, #PMC_SCRATCH38]
-       dsb
-       mov32   r6, TEGRA_FLOW_CTRL_BASE
-
-       mov     r0, #FLOW_CTRL_STOP_UNTIL_IRQ
-       orr     r0, r0, #FLOW_CTRL_IRQ_RESUME | FLOW_CTRL_FIQ_RESUME
-       cpu_id  r1
-       cpu_to_halt_reg r1, r1
-       str     r0, [r6, r1]
-       dsb
-       ldr     r0, [r6, r1] /* memory barrier */
+ENTRY(tegra2_tear_down_cpu)
+       bl      tegra_cpu_pllp
+       b       tegra2_enter_sleep
+ENDPROC(tegra2_tear_down_cpu)
 
-halted: dsb
-       wfe     /* CPU should be power gated here */
-       isb
-       b       halted
+/* START OF ROUTINES COPIED TO IRAM */
+       .align L1_CACHE_SHIFT
+       .globl tegra2_iram_start
+tegra2_iram_start:
 
 /*
- * tegra_lp1_reset
+ * tegra2_lp1_reset
  *
  * reset vector for LP1 restore; copied into IRAM during suspend.
  * brings the system back up to a safe starting point (SDRAM out of
@@ -294,8 +243,10 @@ halted: dsb
  * jumps to tegra_lp2_startup to restore PLLX and virtual addressing.
  * physical address of tegra_lp2_startup expected to be stored in
  * PMC_SCRATCH41
+ *
+ * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA AND MUST BE FIRST.
  */
-ENTRY(tegra_lp1_reset)
+ENTRY(tegra2_lp1_reset)
        /*
         * the CPU and system bus are running at 32KHz and executing from
         * IRAM when this code is executed; immediately switch to CLKM and
@@ -322,8 +273,8 @@ ENTRY(tegra_lp1_reset)
        orreq   r1, r1, #(1 << 30)
        streq   r1, [r0, #CLK_RESET_PLLC_BASE]
 
-       adr     r2, tegra_sdram_pad_address
-       adr     r4, tegra_sdram_pad_save
+       adr     r2, tegra2_sdram_pad_address
+       adr     r4, tegra2_sdram_pad_save
        mov     r5, #0
 
 padload:
@@ -333,7 +284,7 @@ padload:
        str     r1, [r0]                @ set emc register to safe vals
 
        add     r5, r5, #4
-       ldr     r0, tegra_sdram_pad_size
+       ldr     r0, tegra2_sdram_pad_size
        cmp     r0, r5
        bne     padload
 
@@ -347,7 +298,7 @@ padload_done:
        dmb
        bmi     1b
 
-       adr     r4, tegra_sclk_save
+       adr     r4, tegra2_sclk_save
        ldr     r4, [r4]
        mov32   r0, TEGRA_CLK_RESET_BASE
        str     r4, [r0, #CLK_RESET_SCLK_BURST]
@@ -382,16 +333,97 @@ exit_selfrefresh_loop:
        ldr     r0, =TEGRA_PMC_BASE
        ldr     r0, [r0, #PMC_SCRATCH41]
        mov     pc, r0
-ENDPROC(tegra_lp1_reset)
+ENDPROC(tegra2_lp1_reset)
+
+/*
+ * tegra2_tear_down_core
+ *
+ * copied into and executed from IRAM
+ * puts memory in self-refresh for LP0 and LP1
+ */
+tegra2_tear_down_core:
+       bl      tegra2_sdram_self_refresh
+       bl      tegra2_cpu_clk32k
+       b       tegra2_enter_sleep
+
+/*
+ * tegra2_cpu_clk32k
+ *
+ * In LP0 and LP1 all plls will be turned off.  Switch the CPU and system clock
+ * to the 32khz clock (clks)
+ */
+tegra2_cpu_clk32k:
+       /* start by jumping to clkm to safely disable PLLs, then jump
+        * to clks */
+       mov     r0, #(1 << 28)
+       str     r0, [r5, #CLK_RESET_SCLK_BURST]
+       str     r0, [r5, #CLK_RESET_CCLK_BURST]
+       mov     r0, #0
+       str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+       str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
+
+       /* 2 us delay between changing sclk and disabling PLLs */
+       mov32   r7, TEGRA_TMRUS_BASE
+       ldr     r1, [r7]
+       add     r1, r1, #3
+
+1:     ldr     r0, [r7]
+       cmp     r0, r1
+       dmb
+       bmi     1b
+
+       /* switch to CLKS */
+       mov     r0, #0  /* burst policy = 32KHz */
+       str     r0, [r5, #CLK_RESET_SCLK_BURST]
+
+       /* disable PLLP, PLLM, PLLC in LP0 and LP1 states */
+       ldr     r0, [r5, #CLK_RESET_PLLM_BASE]
+       bic     r0, r0, #(1 << 30)
+       str     r0, [r5, #CLK_RESET_PLLM_BASE]
+       ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
+       bic     r0, r0, #(1 << 30)
+       str     r0, [r5, #CLK_RESET_PLLP_BASE]
+       ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
+       bic     r0, r0, #(1 << 30)
+       str     r0, [r5, #CLK_RESET_PLLC_BASE]
+       mov     pc, lr
+
+/*
+ * tegra2_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 and LP1
+ * executes from SDRAM with target state is LP2
+ */
+tegra2_enter_sleep:
+       mov32   r7, TEGRA_TMRUS_BASE
+       ldr     r1, [r7]
+       mov32   r4, TEGRA_PMC_BASE
+       str     r1, [r4, #PMC_SCRATCH38]
+       dsb
+       mov32   r6, TEGRA_FLOW_CTRL_BASE
+
+       mov     r0, #FLOW_CTRL_STOP_UNTIL_IRQ
+       orr     r0, r0, #FLOW_CTRL_IRQ_RESUME | FLOW_CTRL_FIQ_RESUME
+       cpu_id  r1
+       cpu_to_halt_reg r1, r1
+       str     r0, [r6, r1]
+       dsb
+       ldr     r0, [r6, r1] /* memory barrier */
+
+halted: dsb
+       wfe     /* CPU should be power gated here */
+       isb
+       b       halted
 
 /*
- * tegra_sdram_self_refresh
+ * tegra2_sdram_self_refresh
  *
  * called with MMU off and caches disabled
  * puts sdram in self refresh
  * must execute from IRAM
  */
-tegra_sdram_self_refresh:
+tegra2_sdram_self_refresh:
        mov32   r1, TEGRA_EMC_BASE
        mov     r2, #3
        str     r2, [r1, #EMC_REQ_CTRL]         @ stall incoming DRAM requests
@@ -413,9 +445,9 @@ emcself:ldr r3, [r1, #EMC_EMC_STATUS]
        cmp     r3, r2
        bne     emcself                         @ loop until DDR in self-refresh
 
-       adr     r2, tegra_sdram_pad_address
-       adr     r3, tegra_sdram_pad_safe
-       adr     r4, tegra_sdram_pad_save
+       adr     r2, tegra2_sdram_pad_address
+       adr     r3, tegra2_sdram_pad_safe
+       adr     r4, tegra2_sdram_pad_save
        mov     r5, #0
 
 padsave:
@@ -428,19 +460,19 @@ padsave:
        str     r1, [r0]                        @ set emc register to safe vals
 
        add     r5, r5, #4
-       ldr     r0, tegra_sdram_pad_size
+       ldr     r0, tegra2_sdram_pad_size
        cmp     r0, r5
        bne     padsave
 padsave_done:
 
        mov32   r5, TEGRA_CLK_RESET_BASE
        ldr     r0, [r5, #CLK_RESET_SCLK_BURST]
-       adr     r2, tegra_sclk_save
+       adr     r2, tegra2_sclk_save
        str     r0, [r2]
        dsb
        mov     pc, lr
 
-tegra_sdram_pad_address:
+tegra2_sdram_pad_address:
        .word   TEGRA_APB_MISC_BASE + 0x8c8 /* XM2CFGCPADCTRL */
        .word   TEGRA_APB_MISC_BASE + 0x8cc /* XM2CFGDPADCTRL */
        .word   TEGRA_APB_MISC_BASE + 0x8d0 /* XM2CLKCFGPADCTRL */
@@ -449,10 +481,10 @@ tegra_sdram_pad_address:
        .word   TEGRA_APB_MISC_BASE + 0x8e4 /* XM2CFGCPADCTRL2 */
        .word   TEGRA_APB_MISC_BASE + 0x8e8 /* XM2CFGDPADCTRL2 */
 
-tegra_sdram_pad_size:
-       .word   tegra_sdram_pad_size - tegra_sdram_pad_address
+tegra2_sdram_pad_size:
+       .word   tegra2_sdram_pad_size - tegra2_sdram_pad_address
 
-tegra_sdram_pad_safe:
+tegra2_sdram_pad_safe:
        .word   0x8
        .word   0x8
        .word   0x0
@@ -461,10 +493,10 @@ tegra_sdram_pad_safe:
        .word   0x08080040
        .word   0x0
 
-tegra_sclk_save:
+tegra2_sclk_save:
        .word   0x0
 
-tegra_sdram_pad_save:
+tegra2_sdram_pad_save:
        .word   0
        .word   0
        .word   0
@@ -476,6 +508,6 @@ tegra_sdram_pad_save:
        .ltorg
 /* dummy symbol for end of IRAM */
        .align L1_CACHE_SHIFT
-       .globl tegra_iram_end
-tegra_iram_end:
+       .globl tegra2_iram_end
+tegra2_iram_end:
        b       .
index 444da1f..97fa48e 100644 (file)
@@ -150,13 +150,15 @@ ENDPROC(tegra_cpu_save)
  * tegra_sleep_cpu(unsigned long v2p)
  *
  * enters suspend in LP2 by turning off the mmu and jumping to
- * tegra_tear_down_cpu
+ * tegra?_tear_down_cpu
  */
 ENTRY(tegra_sleep_cpu)
        mov     r3, lr                  @ set resume address to lr
        bl      tegra_cpu_save
 
-       mov32   r1, tegra_tear_down_cpu
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+       mov32   r1, tegra2_tear_down_cpu
+#endif
        add     r1, r1, r0
        b       tegra_turn_off_mmu
 ENDPROC(tegra_sleep_cpu)
@@ -176,9 +178,8 @@ tegra_cpu_resume:
        dsb
        isb
 
-       bl cpu_init
+       bl      cpu_init
 
-tegra_cpu_sleep_abort:
        ldmfd   sp!, {r4}
        mcr     p15, 0, r4, c15, c0, 1  @ write diagnostic register
        ldmfd   sp!, {lr}
@@ -191,7 +192,7 @@ tegra_cpu_sleep_abort:
  * r0 = v2p
  * r1 = physical address to jump to with mmu off
  */
-tegra_turn_off_mmu:
+ENTRY(tegra_turn_off_mmu)
        /*
         * change page table pointer to tegra_pgd_phys, so that IRAM
         * and MMU shut-off will be mapped virtual == physical
@@ -217,6 +218,7 @@ tegra_turn_off_mmu:
        add     r3, r3, r0
        mov     r0, r1
        mov     pc, r3
+ENDPROC(tegra_turn_off_mmu)
 
 tegra_pgd_phys_address:
        .word   tegra_pgd_phys
@@ -238,20 +240,19 @@ tegra_shut_off_mmu:
        isb
        mov     pc, r0
 
-       .ltorg
-
 /*
  * tegra_cpu_clk32k
  *
  * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
  */
- tegra_cpu_pllp:
+ENTRY(tegra_cpu_pllp)
        /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
        mov32   r5, TEGRA_CLK_RESET_BASE
-       mov     r0, #(2 << 28)  /* burst policy = run mode */
-       orr     r0, r0, #(4 << 4) /* use PLLP in run mode burst */
+       mov     r0, #(2 << 28)                  @ burst policy = run mode
+       orr     r0, r0, #(4 << 4)               @ use PLLP in run mode burst
        str     r0, [r5, #CLK_RESET_CCLK_BURST]
        mov     r0, #0
        str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
        mov     pc, lr
+ENDPROC(tegra_cpu_pllp)
 
index 65e33c3..a36b98e 100644 (file)
@@ -39,6 +39,9 @@
 #define FLOW_CTRL_IRQ_RESUME           (1 << 10)
 #define FLOW_CTRL_FIQ_RESUME           (1 << 8)
 
+#define FLOW_CTRL_CSR_INTR_FLAG                (1<<15)
+#define FLOW_CTRL_CSR_EVENT_FLAG       (1<<14)
+
 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
                                        + IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
@@ -101,20 +104,51 @@ static inline void tegra20_hotplug_init(void) {}
 static inline void tegra30_hotplug_init(void) {}
 #endif
 
-/* assembly routines implemented in sleep.S */
 void tegra_pen_lock(void);
 void tegra_pen_unlock(void);
 void tegra_cpu_wfi(void);
-void tegra_cpu_set_resettable_soon(void);
-int tegra_cpu_is_resettable_soon(void);
 
-extern void tegra_lp1_reset;
-extern void tegra_iram_start;
-extern void tegra_iram_end;
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra2_iram_start;
+extern void tegra2_iram_end;
+extern void tegra2_lp1_reset;
+int  tegra2_cpu_is_resettable_soon(void);
+void tegra2_cpu_reset(int cpu);
+void tegra2_cpu_set_resettable_soon(void);
+void tegra2_sleep_core(unsigned long v2p);
+void tegra2_sleep_reset(void);
+void tegra2_sleep_wfi(unsigned long v2p);
+#endif
+
+static inline void *tegra_iram_start(void)
+{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+       return &tegra2_iram_start;
+#endif
+}
+
+static inline void *tegra_iram_end(void)
+{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+       return &tegra2_iram_end;
+#endif
+}
+
+static inline void *tegra_lp1_reset(void)
+{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+       return &tegra2_lp1_reset;
+#endif
+}
+
+static inline void tegra_sleep_core(unsigned long v2p)
+{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+       tegra2_sleep_core(v2p);
+#endif
+}
 
-void tegra_sleep_wfi(unsigned long v2p);
 void tegra_sleep_cpu(unsigned long v2p);
-void tegra_sleep_core(unsigned long v2p);
 void tegra_resume(void);
 void tegra_secondary_resume(void);