ARM: tegra: Use 3D power gating sequence for MSENC
Terje Bergstrom [Fri, 28 Sep 2012 07:51:57 +0000 (10:51 +0300)]
Use the 3D power gating sequence for MSENC. Hardware documentation
indicates that they have the same sequence.

Bug 1056631

Change-Id: If9de3dbddc3e0cb8e0fe99facec2a4deaf7e6b9b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/139599
(cherry picked from commit 44b3740357473312f5176b00d82688f5e0ebd5d9)
Reviewed-on: http://git-master/r/146191
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: Rf6201742cba21f2a4a696e43843c872d04fb91d8

arch/arm/mach-tegra/powergate.c

index 5c1d15e..50536bd 100644 (file)
@@ -1496,6 +1496,7 @@ static int tegra11x_check_partition_pg_seq(int id)
 
                break;
        case TEGRA_POWERGATE_3D:
+       case TEGRA_POWERGATE_MPE:
                ret = tegra11x_powergate_3d(id);
                if (ret < 0)
                        return ret;
@@ -1516,7 +1517,8 @@ static int tegra11x_check_partition_pug_seq(int id)
 
                break;
        case TEGRA_POWERGATE_3D:
-               ret = tegra11x_unpowergate_3d(TEGRA_POWERGATE_3D);
+       case TEGRA_POWERGATE_MPE:
+               ret = tegra11x_unpowergate_3d(id);
                if (ret < 0)
                        return ret;
        }